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* Merging MIPS GOT changeset into 3.2 release branch.Pawel Wodnicki2012-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merging r168471: Mips direct object xgot support This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter Merging r168460: [mips] Generate big GOT code. Merging r168458: [mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. Merging r168456: [mips] Add helper functions that create nodes for computing address. Merging r168455: [mips] Add command line option "-mxgot". Merging r168453: [mips] When a node which loads from a GOT is created, pass a MachinePointerInfo referring to a GOT entry. Merging r168450: [mips] Add target operand flag enums for big GOT relocations. Merging r168448: Add relocations used for mips big GOT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@169294 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge in r168799 (PPC bug fix).Hal Finkel2012-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168842 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge in PPC internal-as fixes: r167861, r167862, r167863, r167875, r167860, ↵Hal Finkel2012-11-20
| | | | | | r167864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168351 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert an improper CodeGen test to a MC test.Evan Cheng2012-11-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167663 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RTM from TSX extensionMichael Liao2012-11-08
| | | | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR14264 cause by commit r167237 which did not take into account aKevin Enderby2012-11-05
| | | | | | | | | possible buffer change with a .macro directive. rdar://12637628 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167408 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Stop reserving register AT and use register scavenger when a scratchAkira Hatanaka2012-11-03
| | | | | | | | register is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167341 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix disassembler test cases.Akira Hatanaka2012-11-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167326 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for generating dwarf debugging info with assembly filesKevin Enderby2012-11-01
| | | | | | | | | | | | run through the 'C' preprocessor. That is pick up the file name and line numbers from the cpp hash file line comments for the dwarf file and line numbers tables. rdar://9275556 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167237 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Simple example parser for MC assembly markup.Jim Grosbach2012-10-31
| | | | | | Nothing fancy, just a simple demonstration parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167181 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-30
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-29
| | | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for the [] operator. Essentially, [expr1][expr2] isChad Rosier2012-10-29
| | | | | | | equivalent to [expr1 + expr2]. See test cases for more examples. rdar://12470392 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166949 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial TOC support for PowerPC64 object creationAdhemerval Zanella2012-10-25
| | | | | | | | | | | | | | | | This patch adds initial PPC64 TOC MC object creation using the small mcmodel (a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC, R_PPC64_TOC16, and R_PPC64_TOC16DS). The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter' is meant to avoid the creation of an unreferenced ".TOC." symbol (used in the .odp creation) as well to set the R_PPC64_TOC relocation target as the temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should not point to any symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166677 91177308-0d34-0410-b5e6-96231b3b80d8
* Tell llvm-mc we're using intel syntax, so we don't have to use directives.Chad Rosier2012-10-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166640 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add back-end test case for r166632. Make sure we emit theChad Rosier2012-10-24
| | | | | | | | correct .s output as well as get the correct encoding by the integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166638 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for annotated disassembly output for X86 and arm.Kevin Enderby2012-10-22
| | | | | | | | | | | | Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Depending on the local semantics of .align this test can also emit a ↵Benjamin Kramer2012-10-13
| | | | | | nopl instead of nopw. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165880 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Disable long nops for all cpus prior to pentiumpro/i686.Benjamin Kramer2012-10-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165878 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test cases for correct parsing of register names in 32- and 64-bit modes.David Chisnall2012-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165713 91177308-0d34-0410-b5e6-96231b3b80d8
* Expose move to/from coprocessor instructions in MIPS64 mode.David Chisnall2012-10-11
| | | | | | | | | | | | | Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r165480.Craig Topper2012-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165594 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial assembler implementation of Mips load address macroJack Carter2012-10-09
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides initial implementation of load address macro instruction for Mips. We have implemented two kinds of expansions with their variations depending on the size of immediate operand: 1) load address with immediate value directly: * la d,j => addiu d,$zero,j (for -32768 <= j <= 65535) * la d,j => lui d,hi16(j) ori d,d,lo16(j) (for any other 32 bit value of j) 2) load load address with register offset value * la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535) * la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j) ori d,d,lo16(j) addu d,d,s This patch does not cover the case when the address is loaded from the value of the label or function. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165561 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding support for instructions mfc0, mfc2, mtc0, mtc2Jack Carter2012-10-06
| | | | | | | | | move from and to coprocessors 0 and 2. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement methods that enable expansion of load immediate Jack Carter2012-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | | macro instruction (li) in the assembler. We have identified three possible expansions depending on the size of immediate operand: 1) for 0 ≤ j ≤ 65535. li d,j => ori d,$zero,j 2) for −32768 ≤ j < 0. li d,j => addiu d,$zero,j 3) for any other value of j that is representable as a 32-bit integer. li d,j => lui d,hi16(j) ori d,d,lo16(j) All of the above have been implemented in ths patch. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165199 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch is a partial implementation of mips .set assembler directive. ↵Jack Carter2012-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Directive is defined as follows: .set option The patch implements following options at - lets the assembler use the $at register for macros, but generates warnings if the source program uses $at noat - let source programs use $at without issuingwarnings. noreorder - prevents the assembler from reordering machine language instructions. nomacro - causes the assembler to print a warning whenever an assembler operation generates more than one machine language instruction. macro - lets the assembler generate multiple machine instructions from a single assembler instruction reorder - lets the assembler reorder machine language instructions to improve performance The above variants are parsed and their boolean values set or unset. The code to actually use them will come later. Following options are not implemented yet: nomips16 nomicromips move nomove Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165194 91177308-0d34-0410-b5e6-96231b3b80d8
* MachO: direct-to-object attribute for data-in-code markers.Jim Grosbach2012-10-01
| | | | | | | | | | The target backend can support data-in-code load commands even when the assembler doesn't, or vice-versa. Allow targets to opt-in for direct-to-object. PR13973. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164974 91177308-0d34-0410-b5e6-96231b3b80d8
* X86_32: Large Symbol+Offset relocations.Jim Grosbach2012-09-26
| | | | | | | | | | If the offset is more than 24-bits, it won't fit in a scattered relocation offset field, so we fall back to using a non-scattered relocation. rdar://12358909 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164724 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Darwin BL/BLX relocations to out-of-range symbols.Jim Grosbach2012-09-25
| | | | | | | | | | | When a BL/BLX references a symbol in the same translation unit that is out of range, use an external relocation. The linker will use this to generate a branch island rather than a direct reference, allowing the relocation to resolve correctly. rdar://12359919 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164615 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.Jim Grosbach2012-09-25
| | | | | | rdar://9795790 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit dtors into proper section while compiling in vcpp-compatible mode.Anton Korobeynikov2012-09-23
| | | | | | | Patch by Kai! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164476 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix edge cases of ARM shift operands in arith instructions.Tim Northover2012-09-22
| | | | | | | | | As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-22
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for macro parameters/arguments delimited by spaces,Preston Gurd2012-09-19
| | | | | | | | | | | | to improve compatibility with GNU as. Based on a patch by PaX Team. Fixed assertion failures on non-Darwin and added additional test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164248 91177308-0d34-0410-b5e6-96231b3b80d8
* Support default parameters/arguments for assembler macros.Preston Gurd2012-09-19
| | | | | | | | | | This patch is based on the one by PaX Team. Patch by Andy Zhang! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164246 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance unmatched '.endr' directive error message in assembler.Preston Gurd2012-09-19
| | | | | | | | | | The directive can be matched with directives other than '.rept' Patch by Andy Zhang! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164245 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/MC/X86/x86_nop.s: Make sure -arch=x86 when -mcpu=geode.NAKAMURA Takumi2012-09-19
| | | | | | -mcpu doesn't infer -arch. Consider non-x86 host. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164185 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for r164132.Roman Divacky2012-09-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164134 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembler: Darwin variables defined via .set are no-dead-strip.Jim Grosbach2012-09-13
| | | | | | | | For gas compatibility. rdar://12219394 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163854 91177308-0d34-0410-b5e6-96231b3b80d8
* Add newline.Chad Rosier2012-09-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163565 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for .att_syntax directive.Chad Rosier2012-09-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163542 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer2012-09-07
| | | | | | | | For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163420 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial relocations test for the Mips standalone assembler.Jack Carter2012-09-07
| | | | | | | | | This is not an exhaustive set, but something we can build on. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163419 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-07
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
* PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer2012-09-07
| | | | | | | | | registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163390 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler aliased instruction support.Jack Carter2012-09-07
| | | | | | | | | | | | | | | | The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler intial directive support.Jack Carter2012-09-07
| | | | | | | | | | | | Actually these are just stubs for parsing the directives. Semantic support will come later. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163364 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler fpu instruction support.Jack Carter2012-09-07
| | | | | | | | | Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163363 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler memory instruction support.Jack Carter2012-09-06
| | | | | | | | | | | This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw Test case included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163346 91177308-0d34-0410-b5e6-96231b3b80d8
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-06
| | | | | | Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
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