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* Produce deterministic coff files.Rafael Espindola2013-12-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196341 91177308-0d34-0410-b5e6-96231b3b80d8
* [Stackmap] Specify the triple and cpu to fix the unit test.Juergen Ributzka2013-12-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196339 91177308-0d34-0410-b5e6-96231b3b80d8
* [Stackmap] Emit multi-byte nops for X86.Juergen Ributzka2013-12-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196334 91177308-0d34-0410-b5e6-96231b3b80d8
* Output .eh_frames on COFF too now that the integrated as is used on mingw.Rafael Espindola2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196104 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for issue with microMIPS long branch.Zoran Jovanovic2013-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195976 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert revision 195965.Zoran Jovanovic2013-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195967 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed issue with microMIPS long branch.Zoran Jovanovic2013-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195965 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.Kevin Qin2013-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195936 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: Fix a bug about disassembling post-index load single element to 4 ↵Hao Liu2013-11-28
| | | | | | vectors git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195903 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the same tls section name as msvc.Rafael Espindola2013-11-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently error in clang with: "error: thread-local storage is unsupported for the current target", but we can start to get the llvm level ready. When compiling template<typename T> struct foo { static __declspec(thread) int bar; }; template<typename T> __declspec(therad) int foo<T>::bar; template struct foo<int>; msvc produces SECTION HEADER #3 .tls$ name 0 physical address 0 virtual address 4 size of raw data 12F file pointer to raw data (0000012F to 00000132) 0 file pointer to relocation table 0 file pointer to line numbers 0 number of relocations 0 number of line numbers C0301040 flags Initialized Data COMDAT; sym= "public: static int foo<int>::bar" (?bar@?$foo@H@@2HA) 4 byte align Read Write gcc produces a ".data$__emutls_v.<symbol>" for the testcase with __declspec(thread) replaced with thread_local. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195849 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point absolute difference.Chad Rosier2013-11-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195803 91177308-0d34-0410-b5e6-96231b3b80d8
* Use simple section names for COMDAT sections on COFF.Rafael Espindola2013-11-27
| | | | | | | | | | | | With this patch we use simple names for COMDAT sections (like .text or .bss). This matches the MSVC behavior. When merging it is the COMDAT symbol that is used to decide if two sections should be merged, so there is no point in building a fancy name. This survived a bootstrap on mingw32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195798 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point to integer convertChad Rosier2013-11-26
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195788 91177308-0d34-0410-b5e6-96231b3b80d8
* Use -triple to fix the test on non-ELF hosts.Rafael Espindola2013-11-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195682 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use nopl in cpus that don't support it.Rafael Espindola2013-11-25
| | | | | | | | | | | | | | | Patch by Mikulas Patocka. I added the test. I checked that for cpu names that gas knows about, it also doesn't generate nopl. The modified cpus: i686 - there are i686-class CPUs that don't have nopl: Via c3, Transmeta Crusoe, Microsoft VirtualBox - see https://bbs.archlinux.org/viewtopic.php?pid=775414 k6, k6-2, k6-3, winchip-c6, winchip2 - these are 586-class CPUs via c3 c3-2 - see https://bugs.archlinux.org/task/19733 as a proof that Via c3 and c3-Nehemiah don't have nopl git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195679 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM integrated assembler generates incorrect nop opcodeDavid Peixotto2013-11-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug in the assembler that was causing bad code to be emitted. When switching modes in an assembly file (e.g. arm to thumb mode) we would always emit the opcode from the original mode. Consider this small example: $ cat align.s .code 16 foo: add r0, r0 .align 3 add r0, r0 $ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o $ llvm-objdump -triple thumbv7 -d t.o Disassembly of section .text: foo: 0: 00 44 add r0, r0 2: 00 f0 20 e3 blx #4195904 6: 00 00 movs r0, r0 8: 00 44 add r0, r0 This shows that we have actually emitted an arm nop (e320f000) instead of a thumb nop. Unfortunately, this encodes to a thumb branch which causes bad things to happen when compiling assembly code with align directives. The fix is to notify the ARMAsmBackend when we switch mode. The MCMachOStreamer was already doing this correctly. This patch makes the same change for the MCElfStreamer. There is still a bug in the way nops are emitted for alignment because the MCAlignment fragment does not store the correct mode. The ARMAsmBackend will emit nops for the last mode it knew about. In the example above, we still generate an arm nop if we add a `.code 32` to the end of the file. PR18019 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195677 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix .comm and .lcomm on COFF.Rafael Espindola2013-11-25
| | | | | | | | | | | | | | | | These should not use COMDATs. GNU as uses .bss for .lcomm and section 0 for .comm. Given static int a; int b; MSVC puts both in .bss. This patch then puts both .comm and .lcomm on .bss. With this change we agree with gas on .lcomm, are much closer on .comm and clang-cl matches msvc on the above example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195654 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug about disassembling AArch64 post-index load/store single element ↵Hao Liu2013-11-25
| | | | | | | | | | | instructions. ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble will be disassembled into the same instruction st1 {v0b}[0], [x0], x0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195591 91177308-0d34-0410-b5e6-96231b3b80d8
* Implemented Neon scalar vdup_lane intrinsics.Ana Pazos2013-11-21
| | | | | | | | Fixed scalar dup alias and added test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195330 91177308-0d34-0410-b5e6-96231b3b80d8
* reverts 195057 per requestJack Carter2013-11-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195152 91177308-0d34-0410-b5e6-96231b3b80d8
* Support multiple COFF sections with the same name but different COMDAT.Rafael Espindola2013-11-19
| | | | | | | | | | | | | | | | | | This is the first step to fix pr17918. It extends the .section directive a bit, inspired by what the ELF one looks like. The problem with using linkonce is that given .section foo .linkonce.... .section foo .linkonce we would already have switched sections when getting to .linkonce. The cleanest solution seems to be to add the comdat information in the .section itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195148 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
* implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit ↵Kevin Qin2013-11-19
| | | | | | integer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
* Add predicate for AArch64 crypto instructions.Jiangning Liu2013-11-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] Support for MicroMips STO refactoring.Jack Carter2013-11-19
| | | | | | | | | | | | | | | | | No true functional changes. Change the "hack" name of emitMipsHackSTOCG to emitSymSTO. Remove demonstration code in AsmParser for emitMipsHackSTOCG and emitMipsHackELFFlags. The STO field is in an ELF symbol and is not an explicit directive. That said, we are missing the compliment call in AsmParser and that will need to be addressed soon. XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags. These will built out with following patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "COFF: Emit all MCSymbols rather than filtering out some of them"Reid Kleckner2013-11-18
| | | | | | | | This reverts commit r190888, to fix PR17967. The original change wasn't the right way to get @feat.00 into the object file. The right fix is to make @feat.00 be a global symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Update encoding of bnz.v (typo).Matheus Almeida2013-11-18
| | | | | | | | Note that there's no hardware yet that relies on that encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Fix immediate value of LSA instruction as it was being wrongly ↵Matheus Almeida2013-11-18
| | | | | | | | | | | encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON]Add mov alias for simd copy instructions.Kevin Qin2013-11-18
| | | | | | Set some unspecified bits of INS/DUP to zero as ARMARM requested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
* Use instr mapping for microMIPS in llvm-mc.Zoran Jovanovic2013-11-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case for AArch64 NEON instruction set misc.Kevin Qin2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction class SIMD misc.Kevin Qin2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add the general form of BCRRichard Sandiford2013-11-13
| | | | | | | At the moment this is just the MC support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in .gpword directive parsing.Vladimir Medic2013-11-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194570 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS trap instruction with immediate operands.Zoran Jovanovic2013-11-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch fixes a bug in floating point operands parsing, when instruction ↵Vladimir Medic2013-11-13
| | | | | | alias uses default register operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: diagnose invalid system LDM/STMTim Northover2013-11-12
| | | | | | | | | | | | | The system LDM and STM instructions can't usually writeback to the base register. The one exception is when an LDM is actually an exception-return (i.e. contains PC in the register list). (There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there is no positive test). rdar://problem/15223374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalarChad Rosier2013-11-12
| | | | | | | | copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Add support for MVFR2 which is new in ARMv8Artyom Skrobov2013-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-11
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()Jim Grosbach2013-11-08
| | | | | | | | | | On darwin, when trying to create compact unwind info, a .cfi_cfa_def directive would case an llvm_unreachable() to be hit. Back off when we see this directive and generate the regular DWARF style eh_frame. rdar://15406518 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194285 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-08
| | | | | | ARMv8 (Thumb encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-08
| | | | | | ARMv8 (ARM encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-08
| | | | | | ARMv8 (ARM encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
* Test for microMIPS trap instructions.Zoran Jovanovic2013-11-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194258 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Update encoding of LDI instruction.Matheus Almeida2013-11-08
| | | | | | | | The encoding was updated in MSA r1.07. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 ↵Artyom Skrobov2013-11-08
| | | | | | as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS trap instructions 1.Zoran Jovanovic2013-11-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement gpword directive for mips, test case added. Stype changes using ↵Vladimir Medic2013-11-06
| | | | | | clang-format are also included. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
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