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* Support for microMIPS FPU instructions 1.Zoran Jovanovic2013-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197815 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: add support for the .pool directiveSaleem Abdulrasool2013-12-20
| | | | | | | The .pool directive is an alias for the .ltorg directive used to create a literal pool. Simply treat .pool as if .ltorg was passed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197787 91177308-0d34-0410-b5e6-96231b3b80d8
* Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me withKevin Enderby2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this commit as the only one on the Blamelist so I quickly reverted this. However it was actually Nick's change who has since fixed that issue. Original commit message: Changed the X86 assembler for intel syntax to work with directional labels. The X86 assembler as a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following an Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197744 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert my change to the X86 assembler for intel syntax to work withKevin Enderby2013-12-19
| | | | | | | directional labels. Because it doesn't work for windows :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197731 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed the X86 assembler for intel syntax to work with directional labels.Kevin Enderby2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | The X86 assembler has a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following the Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197728 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the .ltorg directive for ARM assemblyDavid Peixotto2013-12-19
| | | | | | | | | | | | | This directive will write out the assembler-maintained constant pool for the current section. These constant pools are created to support the ldr-pseudo instruction (e.g. ldr r0, =val). The directive can be used by the programmer to place the constant pool in a location that can be reached by a pc-relative offset in the ldr instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197711 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the ldr-pseudo opcode for ARM assemblyDavid Peixotto2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ldr-pseudo opcode is a convenience for loading 32-bit constants. It is converted into a pc-relative load from a constant pool. For example, ldr r0, =0x10001 ldr r1, =bar will generate this output in the final assembly ldr r0, .Ltmp0 ldr r1, .Ltmp1 ... .Ltmp0: .long 0x10001 .Ltmp1: .long bar Sketch of the LDR pseudo implementation: Keep a map from Section => ConstantPool When parsing ldr r0, =val parse val as an MCExpr get ConstantPool for current Section Label = CreateTempSymbol() remember val in ConstantPool at next free slot add operand to ldr that is MCSymbolRef of Label On finishParse() callback Write out all non-empty constant pools for each Entry in ConstantPool Emit Entry.Label Emit Entry.Value Possible improvements to be added in a later patch: 1. Does not convert load of small constants to mov (e.g. ldr r0, =0x1 => mov r0, 0x1) 2. Does reuse constant pool entries for same constant The implementation was tested for ARM, Thumb1, and Thumb2 targets on linux and darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS control instructions.Zoran Jovanovic2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197696 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a disassembler to the PowerPC backendHal Finkel2013-12-19
| | | | | | | | | | | | | | | | | | | | | The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS LL and SC instructions.Zoran Jovanovic2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197692 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS TLS relocations.Zoran Jovanovic2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197685 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support .inst directiveSaleem Abdulrasool2013-12-19
| | | | | | | | | This adds support for the .inst directive. This is an ARM specific directive to indicate an instruction encoded as a constant expression. The major difference between .word, .short, or .byte and .inst is that the latter will be disassembled as an instruction since it does not get flagged as data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197657 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Update format of RUN lines for every MSA MC test.Matheus Almeida2013-12-18
| | | | | | | | | | | 1. The arch directive now appears before the cpu directive 2. Long run lines were split across multiple lines No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197588 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Remove unneeded triple directive in MSA MC tests.Matheus Almeida2013-12-18
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197559 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmParser: add support for .end directiveSaleem Abdulrasool2013-12-18
| | | | | | | | | | | | | | The .end directive indicates the end of the file. No further instructions are processed after a .end directive is encountered. One potential (glaringly obvious) optimisation that could be pursued here is to extend MCAsmParser with a DiscardRemainder method to avoid processing lexemes to the end of the file. It was unclear at this point if that would be worth adding, and could easily be added in a follow on change. Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197547 91177308-0d34-0410-b5e6-96231b3b80d8
* MC COFF: Emit the 'b' section flag for .bss sections in GNU assemblyReid Kleckner2013-12-17
| | | | | | | | | Without this, assembling clang's disassembly would produce an object file with the IMAGE_SCN_CNT_INITIALIZED_DATA section characteristic rather than the uninitialized one. link.exe would warn when merging comdats with different flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197529 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix off by one issue when applying a fixup.Matheus Almeida2013-12-17
| | | | | | | | | The branch offset for a R_MIPS_PC16 relocation is indeed a 16-bit signed immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197506 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in getARMFixupKindMachOInfo() where three ARM fixup kindsKevin Enderby2013-12-13
| | | | | | | | | | | | were falling into the cases for 24-bit branch kinds which are not 24-bit branches. The routine is to return false for fixups are expected to always be resolvable at assembly time. Which these three fixups are as they have limited displacement and are for local references within a function. rdar://15586725 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197282 91177308-0d34-0410-b5e6-96231b3b80d8
* Grow the stackmap/patchpoint format to hold 64-bit IDs.Andrew Trick2013-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197255 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add checks for alignment and maximum displacements for most of theMatheus Almeida2013-12-13
| | | | | | | | | | | | | branch instructions for mips and micromips instruction sets thus avoiding the situation of generating branches to undesired locations if offsets cannot be encoded. This patch also checks if a fixup cannot be applied and returns a fatal error if that's the case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197223 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm] Pass -triple to llvm-mc for ARM ELF test cases.Logan Chien2013-12-11
| | | | | | | | Replace -arch with -triple so that we can guarantee that ELF object files can be generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197062 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm] Implement ARM .arch directive.Logan Chien2013-12-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197052 91177308-0d34-0410-b5e6-96231b3b80d8
* Method parseSetAssignment treats every operand with '$' sign as register and ↵Vladimir Medic2013-12-09
| | | | | | | | | the parsing is directed to set alias for register. This will result in errors reported when expressions containing label references are parsed(for example long jumps) As we can't make a complete solution now it has been decided to enable .set directive to handle long jump expressions. This will cause parser to report errors when parsing integer based register assignments, for example: .set r3, will be reported as error. Still, the need for expressions is higher priority as the integer based register assignments are Mips specific and can be avoided using register names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196773 91177308-0d34-0410-b5e6-96231b3b80d8
* Integrated assembler incorrectly lexes ARM-style commentsDavid Peixotto2013-12-06
| | | | | | | | | | | | | | | | | | | | | | | | | The integrated assembler fails to properly lex arm comments when they are adjacent to an identifier in the input stream. The reason is that the arm comment symbol '@' is also used as symbol variant in other assembly languages so when lexing an identifier it allows the '@' symbol as part of the identifier. Example: $ cat comment.s foo: add r0, r0@got to parse this as a comment $ llvm-mc -triple armv7 comment.s comment.s:4:18: error: unexpected token in argument list add r0, r0@got to parse this as a comment ^ This should be parsed as correctly as `add r0, r0`. This commit modifes the assembly lexer to not include the '@' symbol in identifiers when lexing for targets that use '@' for comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196607 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Fix issue with immediate fields of LD/ST instructionsMatheus Almeida2013-12-05
| | | | | | | | | | | not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196494 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct word hyphenationsAlp Toker2013-12-05
| | | | | | | This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196471 91177308-0d34-0410-b5e6-96231b3b80d8
* Move llvm/test/MC/ELF/thumb-st_other.s to test/MC/ARM.NAKAMURA Takumi2013-12-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196457 91177308-0d34-0410-b5e6-96231b3b80d8
* [mc] Fix ELF st_other flag.Logan Chien2013-12-05
| | | | | | | | | | | | | ELF_Other_Weakref and ELF_Other_ThumbFunc seems to be LLVM internal ELF symbol flags. These should not be emitted to object file. This commit defines ELF_STO_Shift for the target-defined flags for st_other, and increase the value of ELF_Other_Shift to 16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196440 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in darwin's 32-bit X86 handling of evaluating fixups. Kevin Enderby2013-12-04
| | | | | | | | | | | | | | | | Where it would use a scattered relocation entry but falls back to a normal relocation entry because the FixupOffset is more than 24-bits. The bug is in the X86MachObjectWriter::RecordScatteredRelocation() where it changes reference parameter FixedValue but then returns false to indicate it did not create a scattered relocation entry. The fix is simply to save the original value of the parameter FixedValue at the start of the method and restore it if we are returning false in that case. rdar://15526046 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196432 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for parsing ARM symbol variants on ELF targetsDavid Peixotto2013-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196424 91177308-0d34-0410-b5e6-96231b3b80d8
* Produce deterministic coff files.Rafael Espindola2013-12-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196341 91177308-0d34-0410-b5e6-96231b3b80d8
* [Stackmap] Specify the triple and cpu to fix the unit test.Juergen Ributzka2013-12-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196339 91177308-0d34-0410-b5e6-96231b3b80d8
* [Stackmap] Emit multi-byte nops for X86.Juergen Ributzka2013-12-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196334 91177308-0d34-0410-b5e6-96231b3b80d8
* Output .eh_frames on COFF too now that the integrated as is used on mingw.Rafael Espindola2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196104 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for issue with microMIPS long branch.Zoran Jovanovic2013-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195976 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert revision 195965.Zoran Jovanovic2013-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195967 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed issue with microMIPS long branch.Zoran Jovanovic2013-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195965 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.Kevin Qin2013-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195936 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: Fix a bug about disassembling post-index load single element to 4 ↵Hao Liu2013-11-28
| | | | | | vectors git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195903 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the same tls section name as msvc.Rafael Espindola2013-11-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently error in clang with: "error: thread-local storage is unsupported for the current target", but we can start to get the llvm level ready. When compiling template<typename T> struct foo { static __declspec(thread) int bar; }; template<typename T> __declspec(therad) int foo<T>::bar; template struct foo<int>; msvc produces SECTION HEADER #3 .tls$ name 0 physical address 0 virtual address 4 size of raw data 12F file pointer to raw data (0000012F to 00000132) 0 file pointer to relocation table 0 file pointer to line numbers 0 number of relocations 0 number of line numbers C0301040 flags Initialized Data COMDAT; sym= "public: static int foo<int>::bar" (?bar@?$foo@H@@2HA) 4 byte align Read Write gcc produces a ".data$__emutls_v.<symbol>" for the testcase with __declspec(thread) replaced with thread_local. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195849 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point absolute difference.Chad Rosier2013-11-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195803 91177308-0d34-0410-b5e6-96231b3b80d8
* Use simple section names for COMDAT sections on COFF.Rafael Espindola2013-11-27
| | | | | | | | | | | | With this patch we use simple names for COMDAT sections (like .text or .bss). This matches the MSVC behavior. When merging it is the COMDAT symbol that is used to decide if two sections should be merged, so there is no point in building a fancy name. This survived a bootstrap on mingw32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195798 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point to integer convertChad Rosier2013-11-26
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195788 91177308-0d34-0410-b5e6-96231b3b80d8
* Use -triple to fix the test on non-ELF hosts.Rafael Espindola2013-11-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195682 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use nopl in cpus that don't support it.Rafael Espindola2013-11-25
| | | | | | | | | | | | | | | Patch by Mikulas Patocka. I added the test. I checked that for cpu names that gas knows about, it also doesn't generate nopl. The modified cpus: i686 - there are i686-class CPUs that don't have nopl: Via c3, Transmeta Crusoe, Microsoft VirtualBox - see https://bbs.archlinux.org/viewtopic.php?pid=775414 k6, k6-2, k6-3, winchip-c6, winchip2 - these are 586-class CPUs via c3 c3-2 - see https://bugs.archlinux.org/task/19733 as a proof that Via c3 and c3-Nehemiah don't have nopl git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195679 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM integrated assembler generates incorrect nop opcodeDavid Peixotto2013-11-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug in the assembler that was causing bad code to be emitted. When switching modes in an assembly file (e.g. arm to thumb mode) we would always emit the opcode from the original mode. Consider this small example: $ cat align.s .code 16 foo: add r0, r0 .align 3 add r0, r0 $ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o $ llvm-objdump -triple thumbv7 -d t.o Disassembly of section .text: foo: 0: 00 44 add r0, r0 2: 00 f0 20 e3 blx #4195904 6: 00 00 movs r0, r0 8: 00 44 add r0, r0 This shows that we have actually emitted an arm nop (e320f000) instead of a thumb nop. Unfortunately, this encodes to a thumb branch which causes bad things to happen when compiling assembly code with align directives. The fix is to notify the ARMAsmBackend when we switch mode. The MCMachOStreamer was already doing this correctly. This patch makes the same change for the MCElfStreamer. There is still a bug in the way nops are emitted for alignment because the MCAlignment fragment does not store the correct mode. The ARMAsmBackend will emit nops for the last mode it knew about. In the example above, we still generate an arm nop if we add a `.code 32` to the end of the file. PR18019 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195677 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix .comm and .lcomm on COFF.Rafael Espindola2013-11-25
| | | | | | | | | | | | | | | | These should not use COMDATs. GNU as uses .bss for .lcomm and section 0 for .comm. Given static int a; int b; MSVC puts both in .bss. This patch then puts both .comm and .lcomm on .bss. With this change we agree with gas on .lcomm, are much closer on .comm and clang-cl matches msvc on the above example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195654 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug about disassembling AArch64 post-index load/store single element ↵Hao Liu2013-11-25
| | | | | | | | | | | instructions. ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble will be disassembled into the same instruction st1 {v0b}[0], [x0], x0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195591 91177308-0d34-0410-b5e6-96231b3b80d8
* Implemented Neon scalar vdup_lane intrinsics.Ana Pazos2013-11-21
| | | | | | | | Fixed scalar dup alias and added test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195330 91177308-0d34-0410-b5e6-96231b3b80d8
* reverts 195057 per requestJack Carter2013-11-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195152 91177308-0d34-0410-b5e6-96231b3b80d8
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