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* Add disassembler support for VPERMIL2PD and VPERMIL2PS.Craig Topper2011-12-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FMA4 instructions to disassembler.Craig Topper2011-12-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement cfi_restore. Patch by Brian Anderson!Rafael Espindola2011-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147356 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 ↵Craig Topper2011-12-29
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement .cfi_escape. Patch by Brian Anderson!Rafael Espindola2011-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147352 91177308-0d34-0410-b5e6-96231b3b80d8
* Expose FMA3 instructions to the disassembler.Craig Topper2011-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-22
| | | | | | rdar://10558523 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix incorrect relocation generation. Patch by Kristof Beyls.Rafael Espindola2011-12-22
| | | | | | Fixes PR11214. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler should accept shift-by-zero for any shifted-immediate operand.Jim Grosbach2011-12-22
| | | | | | | | Just treat it as-if the shift wasn't there at all. 'as' compatibility. rdar://10604767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
* Local dynamic TLS model for direct object output. Create the correct TLS MIPSAkira Hatanaka2011-12-22
| | | | | | | | | | ELF relocations. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147118 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP optional data type on VMOV GPR<-->SPR.Jim Grosbach2011-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing of 'mov rd, rn, rrx'.Jim Grosbach2011-12-21
| | | | | | | | Maps to the RRX instruction. Missed this case earlier. rdar://10615373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing of 'mov(register shifted register)' aliases.Jim Grosbach2011-12-21
| | | | | | | | These map to the ASR, LSR, LSL, ROR instruction definitions. rdar://10615373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON assmebly parsing for VLD2 to all lanes instructions.Jim Grosbach2011-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable and fix a test.Jim Grosbach2011-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VST2 single-element, double spaced.Jim Grosbach2011-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM enable a few more tests.Jim Grosbach2011-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VLD2 single-element, double spaced.Jim Grosbach2011-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly shifts by zero should be plain 'mov' instructions.Jim Grosbach2011-12-20
| | | | | | | | | | "mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's not strictly legal UAL syntax. It's a common extension and the friendly thing to do. rdar://10604663 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-19
| | | | | | rdar://9932658 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON two-operand aliases for VPADD.Jim Grosbach2011-12-19
| | | | | | rdar://10602276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON implied destination aliases for VMAX/VMIN.Jim Grosbach2011-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON relax parse time diagnostics for alignment specifiers.Jim Grosbach2011-12-19
| | | | | | | There's more variation that we need to handle. Error checking will need to be on operand predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
* Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added theRafael Espindola2011-12-17
| | | | | | asm parsing and testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we correctly note the existence of an i8 immediate for vblendvps ↵Eli Friedman2011-12-15
| | | | | | and friends, so we compute fixups correctly. PR11586. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.Jim Grosbach2011-12-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VTBL/VTBX assembly parsing and encoding.Jim Grosbach2011-12-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.Jim Grosbach2011-12-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the implementation of .incbin directive by replacing a loop by usingKevin Enderby2011-12-14
| | | | | | | getStreamer().EmitBytes. Suggestion by Benjamin Kramer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146599 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON fix alignment encoding for VST2 w/ writeback.Jim Grosbach2011-12-14
| | | | | | Add tests for w/ writeback instruction parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the .incbin directive which takes the binary data from a file and emitsKevin Enderby2011-12-14
| | | | | | | it to the streamer. rdar://10383898 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146592 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-14
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM/Thumb2 'cmp rn, #imm' alias to cmn.Jim Grosbach2011-12-14
| | | | | | | | | | When 'cmp rn #imm' doesn't match due to the immediate not being representable, but 'cmn rn, #-imm' does match, use the latter in place of the former, as it's equivalent. rdar://10552389 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler support for the target-specific .req directive.Jim Grosbach2011-12-14
| | | | | | | rdar://10549683 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembler aliases for "mov(shifted register)"Jim Grosbach2011-12-13
| | | | | | | rdar://10549767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM LDM/STM system instruction variants.Jim Grosbach2011-12-13
| | | | | | rdar://10550269 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
* Test for 146516Jim Grosbach2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM thumb2 parsing of "rsb rd, rn, #0".Jim Grosbach2011-12-13
| | | | | | | rdar://10549741 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON two-operand aliases for VQDMULH.Jim Grosbach2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM pre-UAL NEG mnemonic for convenience when porting old code.Jim Grosbach2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test/MC/Mips/dg.exp.Akira Hatanaka2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146472 91177308-0d34-0410-b5e6-96231b3b80d8
* Move direct object emitter test to directory test/MC/Mips. Rename it toAkira Hatanaka2011-12-13
| | | | | | | elf-relsym.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146470 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't rely on a particular version string for llvm.Nick Lewycky2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146456 91177308-0d34-0410-b5e6-96231b3b80d8
* XOP instructions and encoding tests.Jan Sjödin2011-12-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146407 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for gnu_indirect_function.Roman Divacky2011-12-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146377 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assume things about the exact details of the LLVM version number,Chandler Carruth2011-12-10
| | | | | | such as what VCS information is attached. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146333 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gasRafael Espindola2011-12-10
| | | | | | | | does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC, but it doesn't change the immediate in the same way as when the expression has no right hand side symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly aliases for BIC<-->AND (immediate).Jim Grosbach2011-12-09
| | | | | | | | | | | | When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-09
| | | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
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