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* [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinterBradley Smith2014-04-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207219 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Support crc predicate on ARM64.Kevin Qin2014-04-25
| | | | | | | According to the specification, CRC is an optional extension of the architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207214 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add ARM64 runs to more MC tests.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207120 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too.Tim Northover2014-04-24
| | | | | | | | This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207119 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: print NEON lists with a space.Tim Northover2014-04-24
| | | | | | | This matches ARM64 behaviour, which I think is clearer. It also puts all the churn from that difference into one easily ignored commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207116 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: enable remaining MC elf tests.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207112 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: allow negative addends, at least on ELF.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207111 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: support relocated "TBZ/TBNZ" instructions.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207110 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: support relocated ADR instructionTim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207109 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiersTim Northover2014-04-24
| | | | | | We only need assembly support, so it's fairly easy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207108 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operandsTim Northover2014-04-24
| | | | | | | | | | | | | These can have different relocations in ELF. In particular both: b.eq global ldr x0, global are valid, giving different relocations. The only possible way to distinguish them is via a different fixup, so the operands had to be separated throughout the backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207105 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: enable some MC tests on ARM64Tim Northover2014-04-24
| | | | | | | This will also (as with CodeGen) disable testing when the ARM64 backend is not present. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207104 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18921, "vmov" part.Stepan Dyatkovskiy2014-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | Added support for bytes replication feature, so it could be GAS compatible. E.g. instructions below: "vmov.i32 d0, 0xffffffff" "vmvn.i32 d0, 0xabababab" "vmov.i32 d0, 0xabababab" "vmov.i16 d0, 0xabab" are incorrect, but we could deal with such cases. For first one we should emit: "vmov.i8 d0, 0xff" For second one ("vmvn"): "vmov.i8 d0, 0x54" For last two instructions it should emit: "vmov.i8 d0, 0xab" P.S.: In ARMAsmParser.cpp I have also fixed few nearby style issues in old code. Just for keeping method bodies in harmony with themselves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207080 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: disable test on thumbv7-windowsSaleem Abdulrasool2014-04-23
| | | | | | | This is dependent on changes that are not fully ready to be merged yet (WoA object file emission). The test can be re-enabled for that target later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207038 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: move test from Generic to COFFSaleem Abdulrasool2014-04-23
| | | | | | This is a COFF specific test, move it to COFF to fix the Hexagon buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207030 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: move ARM64 test from AArch64 directorySaleem Abdulrasool2014-04-23
| | | | | | | The test was changed from aarch64 to arm64 but not moved. The test would fail if the backend was not built. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207029 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: honour IMAGE_SCN_CNT_INITIALIZED_DATASaleem Abdulrasool2014-04-23
| | | | | | | Emit the flag to indicate to the assembler that a section contains data if there is pre-populated data present. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207028 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Disassembler - fixed a bug in immediate printElena Demikhovsky2014-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206953 91177308-0d34-0410-b5e6-96231b3b80d8
* Integrated assbemler, macros: added 'vararg' argument qualifier support.Stepan Dyatkovskiy2014-04-23
| | | | | | | | Note, currently we have no 'vararg' support for darwin macros. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206951 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin2014-04-23
| | | | | | | | AArch64 has feature predicates for NEON, FP and CRYPTO instructions. This allows the compiler to generate code without using FP, NEON or CRYPTO instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206949 91177308-0d34-0410-b5e6-96231b3b80d8
* Follow aliases when determining if a symbol is thumb.Rafael Espindola2014-04-22
| | | | | | This fixes pr19484. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206917 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the assembler to print a better relocatable expression errorKevin Enderby2014-04-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | diagnostic that includes location information. Currently if one has this assembly: .quad (0x1234 + (4 * SOME_VALUE)) where SOME_VALUE is undefined ones gets the less than useful error message with no location information: % clang -c x.s clang -cc1as: fatal error: error in backend: expected relocatable expression With this fix one now gets a more useful error message with location information: % clang -c x.s x.s:5:8: error: expected relocatable expression .quad (0x1234 + (4 * SOME_VALUE)) ^ To do this I plumbed the SMLoc through the MCObjectStreamer EmitValue() and EmitValueImpl() interfaces so it could be used when creating the MCFixup. rdar://12391022 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206906 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX512] Implemented integer conversions up/down with masking.Robert Khasanov2014-04-22
| | | | | | | Added encoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206884 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: Improve diagnostics for malformed reg+reg addressing mode.Jim Grosbach2014-04-21
| | | | | | | Make sure only general purpose registers are valid for offset regs and that 32-bit regs are only valid for sxtw and uxtw extends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206799 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode.Rafael Espindola2014-04-21
| | | | | | | | | With this MC is able to handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode, which is needed for medium and large code models. This fixes pr19470. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206793 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch by Ray Donnelly to print register names instead of numbers.Yaron Keren2014-04-19
| | | | | | | | http://reviews.llvm.org/D3422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206683 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the ARM assembler to require a :lower16: or :upper16 on non-constantKevin Enderby2014-04-18
| | | | | | | | | | | | | | | | | | | | | | | expressions for mov instructions instead of silently truncating by default. For the ARM assembler, we want to avoid misleadingly allowing something like "mov r0, <symbol>" especially when we turn it into a movw and the expression <symbol> does not have a :lower16: or :upper16" as part of the expression. We don't want the behavior of silently truncating, which can be unexpected and lead to bugs that are difficult to find since this is an easy mistake to make. This does change the previous behavior of llvm but actually matches an older gnu assembler that would not allow this but print less useful errors of like “invalid constant (0x927c0) after fixup” and “unsupported relocation on symbol foo”. The error for llvm is "immediate expression for mov requires :lower16: or :upper16" with correct location information on the operand as shown in the added test cases. rdar://12342160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206669 91177308-0d34-0410-b5e6-96231b3b80d8
* Compress debug sections only when beneficial.David Blaikie2014-04-18
| | | | | | | | | Both ZLIB and the debug info compressed section header ("ZLIB" + the size of the uncompressed data) take some constant overhead so in some cases the compressed data is actually larger than the uncompressed data. In these cases, just don't compress or rename the section at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206659 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the fragments of symbols in compressed sections.David Blaikie2014-04-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While unnamed relocations are already cached in side tables in ELFObjectWriter::RecordRelocation, symbols still need their fragments updated to refer to the newly compressed fragment (even if that fragment isn't big enough to fit the offset). Even though we only create temporary symbols in debug info sections this comes up in 32 bit builds where even temporary symbols in mergeable sections (such as debug_str) have to be emitted as named symbols. I tried a few other ways to do this but they all didn't work for various reasons: 1) Canonicalize the MCSymbolData in RecordRelocation, nulling out the Fragment (so it didn't have to be updated by CompressDebugSection). This doesn't work because some code relies on symbols having fragments to indicate that they're defined, I think. 2) Canonicalize the MCSymbolData in RecordRelocation to be "first fragment + absolute offset" so it would be cheaper to just test and update the fragment in CompressDebugSections. This doesn't work because the offset computed in RecordRelocation isn't that of the symbol's fragment, it's the passed in fragment (I haven't figured out what that fragment is - perhaps it's the location where the relocation is to be written). And if the fragment offset has to be computed only for this use we might as well just do it when we need to, in CompressDebugSection. I also added an assert to help catch this a bit more clearly, even though it is UB. The test case improvements would either assert fail and/or valgrind vail without the fix, even if they wouldn't necessarily fail the FileCheck output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206653 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r206565 (and r206566 which updated tests).Chandler Carruth2014-04-18
| | | | | | | | | | | | | | This commit was attributed to a different person from the person who posted the patch to the list, and the person who posted it the list claimed when they did that they were not the author, but that the author was yet a third person. I don't know what is going on here, but reverting until the attribution is clear and the author has explicitly contributed the patch. Also, the review hasn't really involved any of the MC maintainers and that seems questionable too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206576 91177308-0d34-0410-b5e6-96231b3b80d8
* Updated test with register names following r206565.Yaron Keren2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206566 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: [su]xtw use W regs as inputs, not X regs.Jim Grosbach2014-04-17
| | | | | | | | | Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206495 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.Craig Topper2014-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206447 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit - Added a new lineKonrad Anheim2014-04-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206399 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use TwoOperandAliasConstraint for shift instructions.Matheus Almeida2014-04-16
| | | | | | | | | | | This enables TableGen to generate an additional two operand matcher for our shift_rotate_imm and shift_rotate_reg class of instructions. The tests were also updated so that they include now encoding information for all affected instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206398 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add initial support for NaN2008 in the back-end.Matheus Almeida2014-04-16
| | | | | | | | | | | | | This is so that EF_MIPS_NAN2008 is set if we are using IEEE 754-2008 NaN encoding (-mnan=2008). This patch also adds support for parsing '.nan legacy' and '.nan 2008' assembly directives. The handling of these directives should match GAS' behaviour i.e., the last directive in use sets the ELF header bit (EF_MIPS_NAN2008). Differential Revision: http://reviews.llvm.org/D3346 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206396 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: produce correct relocation for conditional branches.Tim Northover2014-04-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206391 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: fix an off by one errorSaleem Abdulrasool2014-04-16
| | | | | | | | | | Adjust the tests to validate the number of auxiliary entries used to store the filename. Thanks to majnemer's sharp eye for catching the missing - 1 in the round up calculation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206359 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: add support for .file symbolsSaleem Abdulrasool2014-04-16
| | | | | | | | | | | | | Add support for emitting .file records. This is mostly a quality of implementation change (more complete support for COFF file emission) that was noticed while working on COFF file emission for Windows on ARM. A .file record is emitted as a symbol with storage class FILE (103) and the name ".file". A series of auxiliary format 4 records follow which contain the file name. The filename is stored as an ANSI string and is padded with NULL if the length is not a multiple of COFF::SymbolSize (18). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206355 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: only mangle MOVZ/MOVN during encoding when neededTim Northover2014-04-15
| | | | | | | | Sometimes we need emit the bits that would actually be a MOVN when producing a relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got wrong until now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206289 91177308-0d34-0410-b5e6-96231b3b80d8
* Optional hash symbol feature support for ARM64Stepan Dyatkovskiy2014-04-15
| | | | | | | | http://reviews.llvm.org/D3328 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206276 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC] Emit an error if cfi_startproc is used before a symbol is defined.Quentin Colombet2014-04-15
| | | | | | | | | | Currently, we bind those directives with the last symbol, so if none has been defined, this would lead to a crash of the compiler. <rdar://problem/15939159> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206236 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up MCFixup::getAccessVariant to handle unary expressions.Kaelyn Takata2014-04-14
| | | | | | | | | | | | This allows correct relocations to be generated for a symbolic address that is being adjusted by a negative constant. Since r204294, such expressions have triggered undefined behavior when LLVM was built without assertions. Credit goes to Rafael for this patch; I'm submitting it on his behalf as he is on vacation this week. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206192 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't lose the thumb bit by using relocations with sections.Rafael Espindola2014-04-11
| | | | | | This fixes a regression from r205076. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206047 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert: r205182 - llvm/test/MC/Mips/mips64r2/valid-xfail.s: This REQUIRES ↵Daniel Sanders2014-04-11
| | | | | | | | | | asserts. Seems it doesn't fail with -Asserts. This was most likely caused by an uninitialized value and the relevant code was re-written in r205292. Reverting to see if it still fails on any of the buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206033 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the use of "%e" as it is not a valid expansion like "%t".Kaelyn Takata2014-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205991 91177308-0d34-0410-b5e6-96231b3b80d8
* Reimplement debug info compression by compressing the whole section, rather ↵David Blaikie2014-04-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | than a fragment. To support compressing the debug_line section that contains multiple fragments (due, I believe, to variation in choices of line table encoding depending on the size of instruction ranges in the actual program code) we needed to support compressing multiple MCFragments in a single pass. This patch implements that behavior by mutating the post-relaxed and relocated section to be the compressed form of its former self, including renaming the section. This is a more flexible (and less invasive, to a degree) implementation that will allow for other features such as "use compression only if it's smaller than the uncompressed data". Compressing debug_frame would be a possible further extension to this work, but I've left it for now. The hurdle there is alignment sections - which might require going as far as to refactor MCAssembler.cpp:writeFragment to handle writing to a byte buffer or an MCObjectWriter (there's already a virtual call there, so it shouldn't add substantial compile-time cost) which could in turn involve refactoring MCAsmBackend::writeNopData to use that same abstraction... which involves touching all the backends. This would remove the limited handling of fragment writing seen in ELFObjectWriter.cpp:getUncompressedData which would be nice - but it's more invasive. I did discover that I (perhaps obviously) don't need to handle relocations when I rewrite the fragments - since the relocations have already been applied and computed (and stored into ELFObjectWriter::Relocations) by this stage (necessarily, because we need to have written any immediate values or assembly-time relocations into the data already before we compress it, which we have). The test case doesn't necessarily cover that in detail - I can add more test coverage if that's preferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205990 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert debug info compression support.David Blaikie2014-04-10
| | | | | | | | | | To support compression for debug_line and debug_frame a different approach is required. To simplify review, revert the old implementation and XFAIL the test case. New implementation to follow shortly. Reverts r205059 and r204958. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205989 91177308-0d34-0410-b5e6-96231b3b80d8
* For the ARM integrated assembler add checking of theKevin Enderby2014-04-10
| | | | | | | | | | | | | | | | | | | | alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205986 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4.Daniel Sanders2014-04-10
| | | | | | | | | | | | | | | | | | Summary: It is now the smallest superset for these ISA's. FeatureMips4 now contains FeatureFPIdx since [ls][dw]xc1 were added in MIPS-IV. Made the FPIdx feature bit lowercase so that it can be used in the -mattr option. Depends on D3274 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3275 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205964 91177308-0d34-0410-b5e6-96231b3b80d8
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