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* Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose ↵Artyom Skrobov2014-01-10
| | | | | | (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198946 91177308-0d34-0410-b5e6-96231b3b80d8
* Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)Artyom Skrobov2014-01-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198945 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix regression caused by r198914Saleem Abdulrasool2014-01-10
| | | | | | | | The disassembler would no longer be able to disambiguage between the two variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt, ldrbt, strbt mnemonics as both versions indicated the disassembler routine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198944 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support #:{lower,upper}16: for GNU compatibilitySaleem Abdulrasool2014-01-10
| | | | | | | | The GNU assembler supports prefixing the expression with a '#' to indiciate that the value that is being moved is infact a constant. This improves the compatibility of the integrated assembler's parser for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198916 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support GNU extension for ldrd, strdSaleem Abdulrasool2014-01-10
| | | | | | | | | The GNU assembler has an extension that allows for the elision of the paired register (dt2) for the LDRD and STRD mnemonics. Add support for this in the assembly parser. Canonicalise the usage during the instruction parsing from the specified version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198915 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}TSaleem Abdulrasool2014-01-10
| | | | | | | | | | | | | | | | The ARM ARM indicates the mnemonics as follows: ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>} ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>} strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} This improves the parser to deal with the implicit immediate 0 for the mnemonics as per the specification. Thanks to Joerg Sonnenberger for the tests! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198914 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing jmpl instruction and make indirect call and ↵Venkatraman Govindaraju2014-01-10
| | | | | | jmp instructions as aliases to jmpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198909 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug with the ARM thumb2 CBNZ and CBNZ instructions thatKevin Enderby2014-01-10
| | | | | | | | | | branch to the next instruction. This can not be encoded but can be turned into a NOP. rdar://15062072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198904 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64][NEON] Added UXTL and UXTL2 instruction aliasesAna Pazos2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198791 91177308-0d34-0410-b5e6-96231b3b80d8
* Force emit a relocation for @gnu_indirect_function symbols so that the indirectRoman Divacky2014-01-08
| | | | | | | resolution works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198780 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Support R_386_PC8, R_386_PC16 and R_X86_64_PC8David Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198763 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Do not relax PUSHi16 to PUSHi32 (PR18414)David Woodhouse2014-01-08
| | | | | | | | They do *different* things to %esp, so they are not equivalent. Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198761 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Make AsmParser validate registers for memory operands a bit betterDavid Woodhouse2014-01-08
| | | | | | | | | | | | We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198760 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-08
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Use 16-bit addressing where possible in 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | | | Where "where possible" means that it's an immediate value and it's below 0x10000. In fact GAS will either truncate or error with larger values, and will insist on using the addr32 prefix to get 32-bit addressing. So perhaps we should do that, in a later patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198758 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix JCXZ,JECXZ_32 for 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that appropriately conditional. And JECXZ needs the prefix instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198757 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Disambiguate RET[QL] and fix aliases for 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | | | | I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198756 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliasesDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliasesDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198754 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit modeDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198753 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-08
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198752 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9] Rename operands in some sparc64 instructions so that TableGen can ↵Venkatraman Govindaraju2014-01-08
| | | | | | encode them correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198740 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing branch instructions and conditional moves.Venkatraman Govindaraju2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198738 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: properly handle expression operandsSaleem Abdulrasool2014-01-08
| | | | | | | Operands which involved label arithemetic would previously fail to parse. This corrects that by adding the additional case for the shift operand validation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198735 91177308-0d34-0410-b5e6-96231b3b80d8
* In the ELFWriter when writing aliased (.set) symbols dont blindlyRoman Divacky2014-01-07
| | | | | | | | | | | | | take type from the new symbol but merge them so that the type is never "downgraded". This is probably quite rare, except for IFUNC symbols which we used to misassemble, losing the IFUNC type. Fixes #18372. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198706 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64David Peixotto2014-01-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the pre-UAL aliases of fconsts and fconstd for vmov.f32 and vmov.f64. They use an InstAlias rather than a MnemonicAlias to properly support the predicate operand. We need to support encoded 8-bit constants in order to implement the pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this commit also fixes parsing of encoded floating point constants used in vmov.f32/vmov.f64 instructions. Now we can support assembly code like this: fconsts s0, #0x70 which is equivalent to vmov.f32 s0, #1.0. Most of the code was already in place to support this feature. Previously the code was trying to accept encoded 8-bit float constants for the vmov.f32/vmov.f64 instructions. It looks like the support for parsing encoded floats was lost in a refactoring in commit r148556 and we did not have any tests in place to catch it. The change in this commit is to keep the parsed value as a 32-bit float instead of a 64-bit double because that is what the isFPImm() function expects to find. There is no loss of precision by using a 32-bit float here because we are still limited to an 8-bit encoded value in the end. Additionally, we explicitly reject encoded 8-bit floats for vmovf.32/64. This is the same as the current behavior, but we now do it explicitly rather than accidently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198697 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc., Venkatraman Govindaraju2014-01-07
| | | | | | | Also, correct the offsets for FixupsKindInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198681 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: allow more depth in contextual diagnosticsSaleem Abdulrasool2014-01-07
| | | | | | | Switch the context to be SmallVectors. This allows for saving additional context when providing previous emission sites. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198665 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: refactor unwind contextSaleem Abdulrasool2014-01-07
| | | | | | | | Move the unwinding context for the ARM IAS into a helper class. This is purely a structural refactoring. A follow up change allows for recording additional depth to improve diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198664 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: improve .eabi_attribute handlingSaleem Abdulrasool2014-01-07
| | | | | | | | Parse tag names as well as expressions. The former is part of the specification, the latter is for improved compatibility with the GNU assembler. Fix attribute value handling to be comformant to the specification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198662 91177308-0d34-0410-b5e6-96231b3b80d8
* MCParser: introduce Note and use it for ARM AsmParserSaleem Abdulrasool2014-01-07
| | | | | | | | Introduce a new virtual method Note into the AsmParser. This completements the existing Warning and Error methods. Use the new method to clean up the output of the unwind routines in the ARM AsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198661 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing memory operands in sparc AsmParser.Venkatraman Govindaraju2014-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198658 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] TargetStreamer Support for .abicalls and .set pic0.Jack Carter2014-01-06
| | | | | | | | | | | This patch adds .abicalls and .set pic0 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that both the integrated and standalone assemblers will use for the output for these directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198646 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add initial implementation of disassembler for sparcVenkatraman Govindaraju2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198591 91177308-0d34-0410-b5e6-96231b3b80d8
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-06
| | | | | | | | | | | | | | | | | | | The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198586 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add basic support for .code16Craig Topper2014-01-06
| | | | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198584 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ModR/M byte output for 16-bit addressing modes (PR18220)Craig Topper2014-01-05
| | | | | | | | | | | Add some tests to validate correct register selection, including a fix to an existing test which was requiring the *wrong* output. Patch from David Woodhouse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198566 91177308-0d34-0410-b5e6-96231b3b80d8
* Add lit.local.cfg for MC/SparcVenkatraman Govindaraju2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198536 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add initial implementation of MC Code emitter for sparc.Venkatraman Govindaraju2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198533 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the ↵Craig Topper2014-01-05
| | | | | | corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198530 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64][NEON] Added SXTL and SXTL2 instruction aliasesAna Pazos2014-01-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198437 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm] Add softvfp to supported FPU names.Logan Chien2014-01-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198313 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-01
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
* Add two fp test cases I missed in my previous commit.Craig Topper2013-12-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198269 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more X86 FP stack disassembler test cases.Craig Topper2013-12-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198268 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-31
| | | | | | realized we had no FP disassembler test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: account for predicated pre-UAL mnemonicsSaleem Abdulrasool2013-12-30
| | | | | | | | Checking the trailing letter of the mnemonic is insufficient. Be more thorough in the scanning of the instruction to ensure that we correctly work with the predicated mnemonics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198235 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: provide VFP aliases for pre-V6 mnemonicsSaleem Abdulrasool2013-12-29
| | | | | | | In order to provide compatibility with the GNU assembler, provide aliases for pre-UAL mnemonics for floating point operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198172 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmParser: cleanup diagnostics for .rep/.reptSaleem Abdulrasool2013-12-28
| | | | | | | Avoid double diagnostics for invalid expressions for count. Improve caret location for negative count. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198099 91177308-0d34-0410-b5e6-96231b3b80d8
* IAS: support .rep as an alias for .reptSaleem Abdulrasool2013-12-28
| | | | | | | The GNU assembler supports .rep as an alias for .rept. This simply creates the alias for it and introduces a test for both .rept and .rep. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198097 91177308-0d34-0410-b5e6-96231b3b80d8
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