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* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag ↵Johnny Chen2011-04-11
| | | | | | | | | them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r129235 pending a vetting of the EH rewrite.Bill Wendling2011-04-10
| | | | | | | | | | | | | | | | | | --- Reverse-merging r129235 into '.': D test/Feature/bb_attrs.ll U include/llvm/BasicBlock.h U include/llvm/Bitcode/LLVMBitCodes.h U lib/VMCore/AsmWriter.cpp U lib/VMCore/BasicBlock.cpp U lib/AsmParser/LLParser.cpp U lib/AsmParser/LLLexer.cpp U lib/AsmParser/LLToken.h U lib/Bitcode/Reader/BitcodeReader.cpp U lib/Bitcode/Writer/BitcodeWriter.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129259 91177308-0d34-0410-b5e6-96231b3b80d8
* Beginning of the Great Exception Handling Rewrite.Bill Wendling2011-04-10
| | | | | | | | | | | | | | * Add a "landing pad" attribute to the BasicBlock. * Modify the bitcode reader and writer to handle said attribute. Later: The verifier will ensure that the landing pad attribute is used in the appropriate manner. I.e., not applied to the entry block, and applied only to basic blocks that are branched to via a `dispatch' instruction. (This is a work-in-progress.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129235 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,Chris Lattner2011-04-09
| | | | | | | | InstAlias doesn't allow matching immediate operands, so we have to write C++ code to do this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
* look for the verboten argument slot access in any order, thanks to FritsChris Lattner2011-04-09
| | | | | | | for pointing this out git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129217 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't store Twine temporaries, it's not safe.Benjamin Kramer2011-04-09
| | | | | | And don't append the name over and over again in the loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129210 91177308-0d34-0410-b5e6-96231b3b80d8
* Add back a couple checks removed by r129128; the fact that an intitializerEli Friedman2011-04-09
| | | | | | | | | is an array of structures doesn't imply it's a ConstantArray of ConstantStruct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129207 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR9523, a crash in looprotate on a non-canonical loop made out of ↵Chris Lattner2011-04-09
| | | | | | indirectbr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129203 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug where RecursivelyDeleteTriviallyDeadInstructions couldChris Lattner2011-04-09
| | | | | | | | delete the instruction pointed to by CGP's current instruction iterator, leading to a crash on the testcase. This fixes PR9578. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129200 91177308-0d34-0410-b5e6-96231b3b80d8
* PR9604; try to deal with RAUW updates correctly in the AST. I'm not convincedEli Friedman2011-04-09
| | | | | | | | | it's completely safe to cache the AST across LICM runs even with this fix, but this fix can't hurt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129198 91177308-0d34-0410-b5e6-96231b3b80d8
* Test for r129190.Eli Friedman2011-04-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129197 91177308-0d34-0410-b5e6-96231b3b80d8
* fix two completely broken tests, which were matching due to PR9629.Chris Lattner2011-04-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129195 91177308-0d34-0410-b5e6-96231b3b80d8
* remove a bunch of CHECK lines that aren't checking whatChris Lattner2011-04-09
| | | | | | | | | they thought they were, because alternation was expanding wrong in {{}}'s. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129194 91177308-0d34-0410-b5e6-96231b3b80d8
* have dag combine zap "store undef", which can be formed during call loweringChris Lattner2011-04-09
| | | | | | | with undef arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129185 91177308-0d34-0410-b5e6-96231b3b80d8
* don't test for codegen of 'store undef'Chris Lattner2011-04-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129184 91177308-0d34-0410-b5e6-96231b3b80d8
* Add radar number for future reference.Devang Patel2011-04-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129172 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not emit DW_AT_upper_bound and DW_AT_lower_bound for unbouded array.Devang Patel2011-04-08
| | | | | | | | | If lower bound is more then upper bound then consider it is an unbounded array. An array is unbounded if non-zero lower bound is same as upper bound. If lower bound and upper bound are zero than array has one element. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129156 91177308-0d34-0410-b5e6-96231b3b80d8
* Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng2011-04-08
| | | | | | is lowered into a call to the specified trap function at sdisel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-08
| | | | | | | | PR9650 rdar://problem/9257565 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-08
| | | | | | | | PR9648 rdar://problem/9257634 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
* MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.Johnny Chen2011-04-08
| | | | | | | Add tests for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129137 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-08
| | | | | | | Add more test cases to exercise the logical branches related to the above change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
* Update testsRafael Espindola2011-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129116 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not let debug info interfer with branch folding.Devang Patel2011-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129114 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a VEXT test.Johnny Chen2011-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
* Add option to emit @llvm.trap as a function call instead of a trap ↵Evan Cheng2011-04-07
| | | | | | instruction. rdar://9249183. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for .skip.Rafael Espindola2011-04-07
| | | | | | | Patch by Roman Divacky. Fixes PR9361. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129106 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-07
| | | | | | | | | | induction variable. The preRA scheduler is unaware of induction vars, so we look for potential "virtual register cycles" instead. Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix handling of functions with internal linkage.Akira Hatanaka2011-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129099 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checking for invalid register encodings for signed/unsigned ↵Johnny Chen2011-04-07
| | | | | | | | | extend instructions. Add some test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-07
| | | | | | | And two test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
* While hoisting common code from if/else, hoist debug info intrinsics if they ↵Devang Patel2011-04-07
| | | | | | match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129078 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal ↵Tanya Lattner2011-04-07
| | | | | | vector type (vectors of size 3). Also included test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-07
| | | | | | | rdar://problem/9246844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
* PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoadEli Friedman2011-04-07
| | | | | | | | | | | | | is equivalent to any other relevant value; it isn't true in general. If it is equivalent, the LoopPromoter will tell the AST the equivalence. Also, delete the PreheaderLoad if it is unused. Chris, since you were the last one to make major changes here, can you check that this is sane? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129049 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-07
| | | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
* Change -arm-divmod-libcall to a target neutral option.Evan Cheng2011-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-07
| | | | | | | rdar://problem/9246650 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ↵Owen Anderson2011-04-06
| | | | | | folded comparisons, just like ADD and SUB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129038 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.393Johnny Chen2011-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-06
| | | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-06
| | | | | | | | | | Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
* This testcase passed even without the fix. Added the target info to make theNadav Rotem2011-04-06
| | | | | | | | test fail (without the fix). Thanks Dan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128999 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-06
| | | | | | | | | | | Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for ↵Johnny Chen2011-04-05
| | | | | | | | | | | illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
* A7.3 register encodingJohnny Chen2011-04-05
| | | | | | | | | | | | | | Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-05
| | | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
* remove postdom frontiers, because it is dead. Forward dom frontiers areChris Lattner2011-04-05
| | | | | | | still used by RegionInfo :( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128943 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-05
| | | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
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