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* Merging r200202:Tom Stellard2014-04-08
| | | | | | | | | | | ------------------------------------------------------------------------ r200202 | stpworld | 2014-01-27 04:43:10 -0500 (Mon, 27 Jan 2014) | 2 lines Additional fix for 200201: due to dependence on bitwidth test was moved to X86 directory. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205807 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200201:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r200201 | stpworld | 2014-01-27 04:18:31 -0500 (Mon, 27 Jan 2014) | 31 lines Fix for PR18102. Issue outcomes from DAGCombiner::MergeConsequtiveStores, more precisely from mem-ops sequence sorting. Consider, how MergeConsequtiveStores works for next example: store i8 1, a[0] store i8 2, a[1] store i8 3, a[1] ; a[1] again. return ; DAG starts here 1. Method will collect all the 3 stores. 2. It sorts them by distance from the base pointer (farthest with highest index). 3. It takes first consecutive non-overlapping stores and (if possible) replaces them with a single store instruction. The point is, we can't determine here which 'store' instruction would be the second after sorting ('store 2' or 'store 3'). It happens that 'store 3' would be the second, and 'store 2' would be the third. So after merging we have the next result: store i16 (1 | 3 << 8), base ; is a[0] but bit-casted to i16 store i8 2, a[1] So actually we swapped 'store 3' and 'store 2' and got wrong contents in a[1]. Fix: In sort routine just also take into account mem-op sequence number. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205806 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203725:Tom Stellard2014-04-08
| | | | | | | | | | | ------------------------------------------------------------------------ r203725 | rafael.espindola | 2014-03-12 18:03:43 -0400 (Wed, 12 Mar 2014) | 2 lines This test need the X86 backend, move it to the X86 sub directory. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205798 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203719:Tom Stellard2014-04-08
| | | | | | | | | | | | | ------------------------------------------------------------------------ r203719 | mzolotukhin | 2014-03-12 17:31:05 -0400 (Wed, 12 Mar 2014) | 4 lines PR17473: Don't normalize an expression during postinc transformation unless it's invertible. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205797 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r202273:Tom Stellard2014-04-08
| | | | | | | | | | | | | ------------------------------------------------------------------------ r202273 | atrick | 2014-02-26 11:31:56 -0500 (Wed, 26 Feb 2014) | 4 lines Fix PR18165: LSR must avoid scaling factors that exceed the limit on truncated use. Patch by Michael Zolotukhin! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205796 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r198863:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r198863 | stpworld | 2014-01-09 07:26:12 -0500 (Thu, 09 Jan 2014) | 6 lines Fixed old typo in ScalarEvolution, that caused wrong SCEVs zext operation. Detailed description is here: http://llvm.org/bugs/show_bug.cgi?id=18000#c16 For participation in bugfix process special thanks to David Wiberg. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205794 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r198744:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r198744 | iain | 2014-01-08 05:22:54 -0500 (Wed, 08 Jan 2014) | 8 lines [patch] Adjust behavior of FDE cross-section relocs for targets that don't support abs-differences. Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs. This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff". At present, this is only enabled for modern x86 OSX ports. test changes by David Fang. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205768 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197572:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197572 | rafael.espindola | 2013-12-18 09:35:37 -0500 (Wed, 18 Dec 2013) | 6 lines One ppc32-darwin, a i64 inside a structure can have 32 bit alignment. Thanks for Iain Sandoe for testing this with the original gcc. Clang was already getting this right. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205766 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203818:Tom Stellard2014-03-24
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r203818 | thomas.stellard | 2014-03-13 10:13:04 -0700 (Thu, 13 Mar 2014) | 7 lines R600: LDS instructions shouldn't implicitly define OQAP LDS instructions are pseudo instructions which model the OQAP defs and uses within a single instruction. This fixes a hang in the opencv MedianFilter tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204650 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r201097:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r201097 | thomas.stellard | 2014-02-10 08:58:30 -0800 (Mon, 10 Feb 2014) | 9 lines R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used DS instructions that access local memory can only uses addresses that are less than or equal to the value of M0. When M0 is uninitialized, then we experience undefined behavior. This patch also changes the behavior to emit S_WQM_B64 on pixel shaders no matter what kind of DS instruction is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204648 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200830:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r200830 | michel.daenzer | 2014-02-05 01:48:05 -0800 (Wed, 05 Feb 2014) | 8 lines R600/SI: Add pattern for zero-extending i1 to i32 Fixes opencl-example if_* tests with radeonsi. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74469 Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204646 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200743:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r200743 | michel.daenzer | 2014-02-03 23:12:38 -0800 (Mon, 03 Feb 2014) | 11 lines R600/SI: Fix fneg for 0.0 V_ADD_F32 with source modifier does not produce -0.0 for this. Just manipulate the sign bit directly instead. Also add a pattern for (fneg (fabs ...)). Fixes a bunch of bit encoding piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204643 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200283:Tom Stellard2014-03-24
| | | | | | | | | | | | | ------------------------------------------------------------------------ r200283 | michel.daenzer | 2014-01-27 19:01:16 -0800 (Mon, 27 Jan 2014) | 6 lines R600/SI: Add pattern for truncating i32 to i1 Fixes half a dozen piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204642 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199918:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r199918 | thomas.stellard | 2014-01-23 10:49:33 -0800 (Thu, 23 Jan 2014) | 8 lines R600: Disable the BFE pattern This pattern uses an SDNodeXForm, which isn't being emitted for some reason. I can get it to work by attaching the PatLeaf that has the XForm to the argument in the output pattern, but this results in an immediate being used in a register operand, which the backend can't handle yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204640 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199917:Tom Stellard2014-03-24
| | | | | | | | | | | | | ------------------------------------------------------------------------ r199917 | thomas.stellard | 2014-01-23 10:49:31 -0800 (Thu, 23 Jan 2014) | 6 lines R600: Correctly handle vertex fetch clauses the precede ENDIFs The control flow finalizer would sometimes use an ALU_POP_AFTER instruction before the vetex fetch clause instead of using a POP instruction after it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204639 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r202336:Tom Stellard2014-03-24
| | | | | | | | | | | ------------------------------------------------------------------------ r202336 | michel.daenzer | 2014-02-26 17:47:02 -0800 (Wed, 26 Feb 2014) | 4 lines R600/SI: Allow SI_KILL for geometry shaders Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204638 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200196:Tom Stellard2014-03-24
| | | | | | | | | | | ------------------------------------------------------------------------ r200196 | michel.daenzer | 2014-01-26 23:20:51 -0800 (Sun, 26 Jan 2014) | 4 lines R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204637 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200195:Tom Stellard2014-03-24
| | | | | | | | | | | ------------------------------------------------------------------------ r200195 | michel.daenzer | 2014-01-26 23:20:44 -0800 (Sun, 26 Jan 2014) | 4 lines R600/SI: Add intrinsic for S_SENDMSG instruction Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204636 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197503, r197505, r197520:Tom Stellard2014-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197520 | dexonsmith | 2013-12-17 12:28:21 -0800 (Tue, 17 Dec 2013) | 7 lines Assert that the last operand is actually EFLAGS This is another follow-up to r197503, after a post-commit review by Andy. <rdar://problem/15627766> ------------------------------------------------------------------------ r197505 | dexonsmith | 2013-12-17 08:20:37 -0800 (Tue, 17 Dec 2013) | 6 lines Setting the CPU in the new vaargs test Trying to fix buildbots after r197503 (test passes locally). <rdar://problem/15627766> ------------------------------------------------------------------------ r197503 | dexonsmith | 2013-12-17 07:54:45 -0800 (Tue, 17 Dec 2013) | 17 lines Revert "Revert "Mark vastart_save_xmm_regs as changing EFLAGS"" This reverts commit r197481, recommiting r197469 with an extra fix. The vastart_save_xmm_regs pseudo-instruction expands to a test and a branch, so it modifies EFLAGS. Mark it so, or else the scheduler might place it in the middle of another test+branch. This fixes a bug exposed by r192750, which changed the initial scheduler to source-order as part of enabling the MI Scheduler for X86. This re-commit changes the VASTART_SAVE_XMM_REGS custom inserter not to try to save %flags, and adds a test that catches the bad behavior of r197469. <rdar://problem/15627766> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@202060 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197492:Bill Wendling2013-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197492 | dyatkovskiy | 2013-12-17 04:07:33 -0800 (Tue, 17 Dec 2013) | 26 lines Fix for PR18045: http://llvm.org/bugs/show_bug.cgi?id=18045 Short issue description: For X86 machines with sse < sse4.1 we got failures for some particular load/store vector sequences: $ clang-trunk -m32 -O2 test-case.c fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850, 0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82] [ID=58] 0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43] 0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23] 0x41dcb10: i32 = undef [ID=2] The reason is that EltsFromConsecutiveLoads could emit such load instruction both before and after legalize stage. Though this instruction is not legal for machines with SSSE3 and lower. The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we check whether nodes it emits are legal. P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8), perhaps I'll slow with response, so you better reject this commit. Thanks! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197779 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197449:Bill Wendling2013-12-17
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197449 | arnolds | 2013-12-16 17:11:01 -0800 (Mon, 16 Dec 2013) | 7 lines LoopVectorizer: Don't if-convert constant expressions that can trap A phi node operand or an instruction operand could be a constant expression that can trap (division). Check that we don't vectorize such cases. PR16729 radar://15653590 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197453 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197216:Bill Wendling2013-12-15
| | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197216 | chandlerc | 2013-12-13 00:00:01 -0800 (Fri, 13 Dec 2013) | 9 lines [inliner] Fix PR18206 by preventing inlining functions that call setjmp through an invoke instruction. The original patch for this was written by Mark Seaborn, but I've reworked his test case into the existing returns_twice test case and implemented the fix by the prior refactoring to actually run the cost analysis over invoke instructions, and then here fixing our detection of the returns_twice attribute to work for both calls and invokes. We never noticed because we never saw an invoke. =[ ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197352 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197215:Bill Wendling2013-12-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197215 | chandlerc | 2013-12-12 23:59:56 -0800 (Thu, 12 Dec 2013) | 24 lines [inliner] Completely change (and fix) how the inline cost analysis handles terminator instructions. The inline cost analysis inheritted some pretty rough handling of terminator insts from the original cost analysis, and then made it much, much worse by factoring all of the important analyses into a separate instruction visitor. That instruction visitor never visited the terminator. This works fine for things like conditional branches, but for many other things we simply computed The Wrong Value. First example are unconditional branches, which should be free but were counted as full cost. This is most significant for conditional branches where the condition simplifies and folds during inlining. We paid a 1 instruction tax on every branch in a straight line specialized path. =[ Oh, we also claimed that the unreachable instruction had cost. But it gets worse. Let's consider invoke. We never applied the call penalty. We never accounted for the cost of the arguments. Nope. Worse still, we didn't handle the *correctness* constraints of not inlining recursive invokes, or exception throwing returns_twice functions. Oops. See PR18206. Sadly, PR18206 requires yet another fix, but this refactoring is at least a huge step in that direction. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197351 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197178:Bill Wendling2013-12-14
| | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197178 | hfinkel | 2013-12-12 12:45:24 -0800 (Thu, 12 Dec 2013) | 9 lines Fix a use-after-free error in GlobalOpt CleanupConstantGlobalUsers GlobalOpt's CleanupConstantGlobalUsers function uses a worklist array to manage constant users to be visited. The pointers in this array need to be weak handles because when we delete a constant array, we may also be holding a pointer to one of its elements (or an element of one of its elements if we're dealing with an array of arrays) in the worklist. Fixes PR17347. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197322 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197228:Bill Wendling2013-12-14
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197228 | d0k | 2013-12-13 05:40:24 -0800 (Fri, 13 Dec 2013) | 8 lines X86: When lowering shl_parts, don't emit shift amounts larger than the bit width. While it's safe for the X86-specific shift nodes, dag combining will kill generic nodes. Insert an AND to make it safe, isel will nuke it as x86's shift instructions have an implicit AND. Fixes PR16108, which contains a contraption to hit this case in between constant folders. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197321 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197089:Bill Wendling2013-12-12
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197089 | hfinkel | 2013-12-11 15:12:25 -0800 (Wed, 11 Dec 2013) | 6 lines Fix the PPC subsumes-predicate check For one predicate to subsume another, they must both check the same condition register. Failure to check this prerequisite was causing miscompiles. Fixes PR18003. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197126 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196858:Bill Wendling2013-12-10
| | | | | | | | | | | ------------------------------------------------------------------------ r196858 | nadav | 2013-12-09 17:13:59 -0800 (Mon, 09 Dec 2013) | 1 line Fix PR18162 - Incorrect assertion assumed that the SDValue resno is zero. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196886 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196806:Bill Wendling2013-12-10
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r196806 | apazos | 2013-12-09 11:29:14 -0800 (Mon, 09 Dec 2013) | 11 lines Fix pattern match for movi with 0D result Patch by Jiangning Liu. With some test case changes: - intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll. - New test cases to cover movi 1D scenario without using the intrinsic in test/CodeGen/AArch64/neon-mov.ll. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196872 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196158:Manman Ren2013-12-09
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r196158 | mren | 2013-12-02 13:29:56 -0800 (Mon, 02 Dec 2013) | 12 lines Debug Info: drop debug info via upgrading path if version number does not match. Add a helper function getDebugInfoVersionFromModule to return the debug info version number for a module. "Verifier/module-flags-1.ll" checks for verification errors. It will seg fault when calling getDebugInfoVersionFromModule because of the incorrect format for module flags in the testing case. We make getModuleFlagsMetadata more robust by checking for error conditions. PR17982 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196822 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196156:Manman Ren2013-12-09
| | | | | | | | | | | | ------------------------------------------------------------------------ r196156 | mren | 2013-12-02 13:25:56 -0800 (Mon, 02 Dec 2013) | 2 lines Update Ocaml/vmcore.ml to emit a "Debug Info Version" module flag. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196821 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195535:Manman Ren2013-12-09
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195535 | mren | 2013-11-22 17:16:29 -0800 (Fri, 22 Nov 2013) | 8 lines Debug Info: update testing cases to specify the debug info version number. We are going to drop debug info without a version number or with a different version number, to make sure we don't crash when we see bitcode files with different debug info metadata format. Make tests more robust by removing hard-coded metadata numbers in CHECK lines. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196817 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195504:Manman Ren2013-12-09
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195504 | mren | 2013-11-22 13:49:45 -0800 (Fri, 22 Nov 2013) | 6 lines Debug Info: update testing cases to specify the debug info version number. We are going to drop debug info without a version number or with a different version number, to make sure we don't crash when we see bitcode files with different debug info metadata format. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196815 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge rest of r196210. Some bits strayed into r196701, turning 3.4 red. ThisTim Northover2013-12-09
| | | | | | | | | | | | | | should fix the issue. ------------------------------------------------------------------------ r196210 | haoliu | 2013-12-03 06:06:55 +0000 (Tue, 03 Dec 2013) | 3 lines [AArch64]Add missing floating point convert, round and misc intrinsics. E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196772 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge r196725 (conflicts on same API as before):Tim Northover2013-12-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r196725 | tnorthover | 2013-12-08 15:56:50 +0000 (Sun, 08 Dec 2013) | 19 lines ARM: fix folding of stack-adjustment (yet again). When trying to eliminate an "sub sp, sp, #N" instruction by folding it into an existing push/pop using dummy registers, we need to account for the fact that this might affect precisely how "fp" gets set in the prologue. We were attempting this, but assuming that *whenever* we performed a fold it would make a difference. This is false, for example, in: push {r4, r7, lr} add fp, sp, #4 vpush {d8} sub sp, sp, #8 we can fold the "sub" into the "vpush", forming "vpush {d7, d8}". However, in that case the "add fp" instruction mustn't change, which we were getting wrong before. Should fix PR18160. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196769 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196751:Bill Wendling2013-12-09
| | | | | | | | | | | | | ------------------------------------------------------------------------ r196751 | venkatra | 2013-12-08 20:02:15 -0800 (Sun, 08 Dec 2013) | 3 lines [Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196766 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196755:Bill Wendling2013-12-09
| | | | | | | | | | | | ------------------------------------------------------------------------ r196755 | venkatra | 2013-12-08 21:13:25 -0800 (Sun, 08 Dec 2013) | 2 lines [SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196764 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196735:Bill Wendling2013-12-09
| | | | | | | | | | | | | ------------------------------------------------------------------------ r196735 | venkatra | 2013-12-08 14:06:07 -0800 (Sun, 08 Dec 2013) | 3 lines [SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9. This fixes PR18150. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196744 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196493. Simple conflict due to change API of updatedTim Northover2013-12-08
| | | | | | | function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196717 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196638:Bill Wendling2013-12-08
| | | | | | | | | | | ------------------------------------------------------------------------ r196638 | arsenm | 2013-12-06 18:58:45 -0800 (Fri, 06 Dec 2013) | 1 line Fix assert with copy from global through addrspacecast ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196709 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r196668 into '.':Bill Wendling2013-12-08
| | | | | | | | | U lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp U test/Transforms/InstCombine/addrspacecast.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196705 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196588:Bill Wendling2013-12-08
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r196588 | weimingz | 2013-12-06 09:56:48 -0800 (Fri, 06 Dec 2013) | 7 lines Bug 18149: [AArch32] VSel instructions has no ARMCC field The current peephole optimizing for compare inst assumes an instr that uses CPSR has an MO for ARM Cond code.However, for VSEL instructions (vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do they support the modification of Cond Code. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196704 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196456:Bill Wendling2013-12-08
| | | | | | | | | | | | ------------------------------------------------------------------------ r196456 | jiangning | 2013-12-04 18:12:01 -0800 (Wed, 04 Dec 2013) | 2 lines For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196700 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196362:Bill Wendling2013-12-08
| | | | | | | | | | | ------------------------------------------------------------------------ r196362 | kevinqin | 2013-12-04 00:02:34 -0800 (Wed, 04 Dec 2013) | 1 line [AArch64 Neon] Add ACLE intrinsic vceqz_f64. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196699 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196360:Bill Wendling2013-12-08
| | | | | | | | | | | ------------------------------------------------------------------------ r196360 | kevinqin | 2013-12-03 23:53:28 -0800 (Tue, 03 Dec 2013) | 1 line [AArch64 NEON] Add missing compare intrinsics. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196697 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196208:Bill Wendling2013-12-08
| | | | | | | | | | | | | ------------------------------------------------------------------------ r196208 | haoliu | 2013-12-02 21:58:30 -0800 (Mon, 02 Dec 2013) | 3 lines AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions. E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196693 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196198:Bill Wendling2013-12-08
| | | | | | | | | | | | | ------------------------------------------------------------------------ r196198 | haoliu | 2013-12-02 19:39:47 -0800 (Mon, 02 Dec 2013) | 3 lines AArch64: Add missing scalar pair intrinsics. E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s". ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196691 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196192:Bill Wendling2013-12-08
| | | | | | | | | | | | ------------------------------------------------------------------------ r196192 | jiangning | 2013-12-02 17:33:52 -0800 (Mon, 02 Dec 2013) | 2 lines Add some missing pattern matches for AArch64 Neon intrinsics like vuqadd_s64 and friends. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196690 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196190:Bill Wendling2013-12-08
| | | | | | | | | | | | ------------------------------------------------------------------------ r196190 | jiangning | 2013-12-02 17:29:32 -0800 (Mon, 02 Dec 2013) | 2 lines Add some missing pattern matches for AArch64 Neon intrinsics like vmull_high_n_s16 and friends. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196688 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196638:Bill Wendling2013-12-07
| | | | | | | | | | | ------------------------------------------------------------------------ r196638 | arsenm | 2013-12-06 18:58:45 -0800 (Fri, 06 Dec 2013) | 1 line Fix assert with copy from global through addrspacecast ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196668 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196261:Bill Wendling2013-12-07
| | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r196261 | hliao | 2013-12-03 01:17:32 -0800 (Tue, 03 Dec 2013) | 13 lines Enhance the fix of PR17631 - The fix to PR17631 fixes part of the cases where 'vzeroupper' should not be issued before 'call' insn. There're other cases where helper calls will be inserted not limited to epilog. These helper calls do not follow the standard calling convention and won't clobber any YMM registers. (So far, all call conventions will clobber any or part of YMM registers.) This patch enhances the previous fix to cover more cases 'vzerosupper' should not be inserted by checking if that function call won't clobber any YMM registers and skipping it if so. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196652 91177308-0d34-0410-b5e6-96231b3b80d8
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