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* [objc-arc] KnownSafe does not imply that it is safe to perform code motion ↵Michael Gottesman2013-05-24
| | | | | | | | across CFG edges since even if it is safe to remove RR pairs, we may still be able to move a retain/release into a loop. rdar://13949644 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182670 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc] Make sure that multiple owners is propogated correctly through ↵Michael Gottesman2013-05-24
| | | | | | | | the pass via the usage of a global data structure. rdar://13750319 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182669 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: LoopSimplify can't canonicalize loops with an indirectbr in ↵Benjamin Kramer2013-05-24
| | | | | | | | it, don't assert on those cases. Fixes PR16139. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182656 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve AsmParser handling of invalid instructionsRichard Sandiford2013-05-24
| | | | | | | | | | | | | | | | | | | | | | | | Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve AsmParser register parsingRichard Sandiford2013-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea is to make sure that: (1) "register expected" is restricted to cases where ParseRegister() is called and the token obviously isn't a register. (2) "invalid register" is restricted to cases where a register-like "%..." sequence is found, but the "..." makes no sense. (3) the generic "invalid operand for instruction" is used in cases where the wrong register type is used (GPR instead of FPR, etc.). (4) the new "invalid register pair" is used if the register has the right type, but is not a valid register pair. Testing of (1)-(3) is now restricted to regs-bad.s. It uses a representative instruction for each register class to make sure that only registers from that class are accepted. (4) is tested by both regs-bad.s (which checks all invalid register pairs) and insn-bad.s (which tests one invalid pair for each instruction that requires a pair). While there, I changed "Number" to "Num" for consistency with the operand class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182643 91177308-0d34-0410-b5e6-96231b3b80d8
* scalarizePHI needs to insert the next ExtractElement in the same blockJoey Gouly2013-05-24
| | | | | | | | | as the BinaryOperator, *not* in the block where the IRBuilder is currently inserting into. Fixes a bug where scalarizePHI would create instructions that would not dominate all uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182639 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new function attribute 'cold' to functions.Diego Novillo2013-05-24
| | | | | | | | | | | Other than recognizing the attribute, the patch does little else. It changes the branch probability analyzer so that edges into blocks postdominated by a cold function are given low weight. Added analysis and code generation tests. Added documentation for the new attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182638 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MCSymbolizer for symbolic/annotated disassembly.Ahmed Bougacha2013-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a basic first step towards symbolization of disassembled instructions. This used to be done using externally provided (C API) callbacks. This patch introduces: - the MCSymbolizer class, that mimics the same functions that were used in the X86 and ARM disassemblers to symbolize immediate operands and to annotate loads based off PC (for things like c string literals). - the MCExternalSymbolizer class, which implements the old C API. - the MCRelocationInfo class, which provides a way for targets to translate relocations (either object::RelocationRef, or disassembler C API VariantKinds) to MCExprs. - the MCObjectSymbolizer class, which does symbolization using what it finds in an object::ObjectFile. This makes simple symbolization (with no fancy relocation stuff) work for all object formats! - x86-64 Mach-O and ELF MCRelocationInfos. - A basic ARM Mach-O MCRelocationInfo, that provides just enough to support the C API VariantKinds. Most of what works in otool (the only user of the old symbolization API that I know of) for x86-64 symbolic disassembly (-tvV) works, namely: - symbol references: call _foo; jmp 15 <_foo+50> - relocations: call _foo-_bar; call _foo-4 - __cf?string: leaq 193(%rip), %rax ## literal pool for "hello" Stub support is the main missing part (because libObject doesn't know, among other things, about mach-o indirect symbols). As for the MCSymbolizer API, instead of relying on the disassemblers to call the tryAdding* methods, maybe this could be done automagically using InstrInfo? For instance, even though PC-relative LEAs are used to get the address of string literals in a typical Mach-O file, a MOV would be used in an ELF file. And right now, the explicit symbolization only recognizes PC-relative LEAs. InstrInfo should have already have most of what is needed to know what to symbolize, so this can definitely be improved. I'd also like to remove object::RelocationRef::getValueString (it seems only used by relocation printing in objdump), as simply printing the created MCExpr is definitely enough (and cleaner than string concats). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182625 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: implement @llvm.readcyclecounter intrinsicTim Northover2013-05-23
| | | | | | | | | | | | | This implements the @llvm.readcyclecounter intrinsic as the specific MRC instruction specified in the ARM manuals for CPUs with the Power Management extensions. Older CPUs had slightly different methods which may also have to be implemented eventually, but this should cover all v7 cases. rdar://problem/13939186 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182603 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst regTom Stellard2013-05-23
| | | | | | | | | | Patch by: Vincent Lejeune https://bugs.freedesktop.org/show_bug.cgi?id=64877 NOTE: This is a candidate for the 3.3 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182600 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR16110: Handle DBG_VALUE in ConnectedVNInfoEqClasses::Distribute().Jakob Stoklund Olesen2013-05-23
| | | | | | | | | | | | Now that the LiveDebugVariables pass is running *after* register coalescing, the ConnectedVNInfoEqClasses class needs to deal with DBG_VALUE instructions. This only comes up when rematerialization during coalescing causes the remaining live range of a virtual register to separate into two connected components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182592 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing test from r175092.Nick Lewycky2013-05-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182564 91177308-0d34-0410-b5e6-96231b3b80d8
* Solidify the assumption that a DW_TAG_subprogram's type is a ↵David Blaikie2013-05-22
| | | | | | | | | | | | | DW_TAG_subroutine_type There were bits & pieces of code lying around that may've given the impression that debug info metadata supported the possibility that a subprogram's type could be specified by a non-subroutine type describing the return type of a void function. This support was incomplete & unnecessary. Asserts & API have been changed to make the desired usage more clear. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182532 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: Change the order in which new instructions are added to the ↵Nadav Rotem2013-05-22
| | | | | | | | | | | | | | function. We are not working on a DAG and I ran into a number of problems when I enabled the vectorizations of 'diamond-trees' (trees that share leafs). * Imroved the numbering API. * Changed the placement of new instructions to the last root. * Fixed a bug with external tree users with non-zero lane. * Fixed a bug in the placement of in-tree users. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182508 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix a bug in EltsFromConsecutiveLoads. We can't generate new loads ↵Nadav Rotem2013-05-22
| | | | | | without chains. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182507 91177308-0d34-0410-b5e6-96231b3b80d8
* This is an update to a previous commit (r181216).Jean-Luc Duprat2013-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | The earlier change list introduced the following inst combines: B * (uitofp i1 C) —> select C, B, 0 A * (1 - uitofp i1 C) —> select C, 0, A select C, 0, B + select C, A, 0 —> select C, A, B Together these 3 changes would simplify : A * (1 - uitofp i1 C) + B * uitofp i1 C down to : select C, B, A In practice we found that the first two substitutions can have a negative effect on performance, because they reduce opportunities to use FMA contractions; between the two options FMAs are often the better choice. This change list amends the previous one to enable just these inst combines: select C, B, 0 + select C, 0, A —> select C, B, A A * (1 - uitofp i1 C) + B * uitofp i1 C —> select C, B, A git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182499 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower ↵Benjamin Kramer2013-05-22
| | | | | | | | halves as unsigned. Take #2 on fixing PR15977. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182486 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: Make Value pointers that could be RAUW'ed a VHArnold Schwaighofer2013-05-22
| | | | | | | | | | The Value pointers we store in the induction variable list can be RAUW'ed by a call to SCEVExpander::expandCodeFor, use a TrackingVH instead. Do the same thing in some other places where we store pointers that could potentially be RAUW'ed. Fixes PR16073. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182485 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Remove test instructions proceeding shift by immediate instructionsDavid Majnemer2013-05-22
| | | | | | | | Allow LLVM to take advantage of shift instructions that set the ZF flag, making instructions that test the destination superfluous. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182454 91177308-0d34-0410-b5e6-96231b3b80d8
* Use std::list so that we have a stable iterator.Rafael Espindola2013-05-21
| | | | | | | I will try to avoid creating these std::strings, but for now this gets the tests passing with libc++. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182405 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename option to make it compatible with gcc.Akira Hatanaka2013-05-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182397 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add instruction selection patterns for blez and bgez.Akira Hatanaka2013-05-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add @llvm.nvvm.sqrt.f() intrinsicJustin Holewinski2013-05-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182394 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.Justin Holewinski2013-05-21
| | | | | | | | | | The intrinsic calls are dropped, but the annotated value is propagated. Fixes PR 15253 Original patch by Zeng Bin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182387 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] A no-op implementation of VarArg handling.Evgeniy Stepanov2013-05-21
| | | | | | | | This stuff is used on platforms where MSan does not have a proper VarArg implementation (anything other than x86_64 at the moment). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182375 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the ↵Benjamin Kramer2013-05-21
| | | | | | | | | smaller type. Otherwise we'll get a mix of signed and unsigned compares. Fixes PR15977. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182364 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Tighten branch testsRichard Sandiford2013-05-21
| | | | | | | After r182274, the branches in these tests must always be short. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182358 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & ↵Benjamin Kramer2013-05-21
| | | | | | | | 0) == 0. Fixes PR16083. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182357 91177308-0d34-0410-b5e6-96231b3b80d8
* Add checks that the proper predeined stubs are being called to the test case.Reed Kotler2013-05-21
| | | | | | | | These were accidentally omitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182347 91177308-0d34-0410-b5e6-96231b3b80d8
* Dwarf: use a single line table to generate assembly when .loc is used.Manman Ren2013-05-21
| | | | | | | | | | This is to fix PR15408 where an undefined symbol Lline_table_start1 is used. Since we do not generate the debug_line section when .loc is used, Lline_table_start1 is not emitted and we can't refer to it when calculating at_stmt_list for a compile unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182344 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some additional functions to the list of helper functions forReed Kotler2013-05-21
| | | | | | | | | | | | pic calls. These need to be there so we don't try and use helper functions when we call those. As part of this, make sure that we properly exclude helper functions in pic mode when indirect calls are involved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182343 91177308-0d34-0410-b5e6-96231b3b80d8
* PR14606: Debug Info for namespace aliases/DW_TAG_imported_moduleDavid Blaikie2013-05-20
| | | | | | | | | This resolves the last of the PR14606 failures in the GDB 7.5 test suite by implementing an optional name field for DW_TAG_imported_modules/DIImportedEntities and using that to implement C++ namespace aliases (eg: "namespace X = Y;"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182328 91177308-0d34-0410-b5e6-96231b3b80d8
* add polly to check-allSebastian Pop2013-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182308 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add (setne $lhs, 0) instruction selection pattern.Akira Hatanaka2013-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182307 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Trap on integer division by zero.Akira Hatanaka2013-05-20
| | | | | | | | | By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a ↵Justin Holewinski2013-05-20
| | | | | | symbol name error in the output PTX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182298 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix rotr.ll on non-asserts buildsTom Stellard2013-05-20
| | | | | | The -debug-only option is only available on asserts builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182291 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for rotrTom Stellard2013-05-20
| | | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Swap the legality of rotl and rotrTom Stellard2013-05-20
| | | | | | The hardware supports rotr and not rotl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add patterns for 64-bit shift operationsTom Stellard2013-05-20
| | | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182284 91177308-0d34-0410-b5e6-96231b3b80d8
* VSTn instructions have a number of encoding constraints which are not ↵Mihai Popa2013-05-20
| | | | | | implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8
* Q registers are encoded in fields of the same length as D registers. As Q ↵Mihai Popa2013-05-20
| | | | | | registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add long branch passRichard Sandiford2013-05-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change, the SystemZ backend would use BRCL for all branches and only consider shortening them to BRC when generating an object file. E.g. a branch on equal would use the JGE alias of BRCL in assembly output, but might be shortened to the JE alias of BRC in ELF output. This was a useful first step, but it had two problems: (1) The z assembler isn't traditionally supposed to perform branch shortening or branch relaxation. We followed this rule by not relaxing branches in assembler input, but that meant that generating assembly code and then assembling it would not produce the same result as going directly to object code; the former would give long branches everywhere, whereas the latter would use short branches where possible. (2) Other useful branches, like COMPARE AND BRANCH, do not have long forms. We would need to do something else before supporting them. (Although COMPARE AND BRANCH does not change the condition codes, the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction during codegen, so that we can safely lower it to a separate compare and long branch where necessary. This is not a valid transformation for the assembler proper to make.) This patch therefore moves branch relaxation to a pre-emit pass. For now, calls are still shortened from BRASL to BRAS by the assembler, although this too is not really the traditional behaviour. The first test takes about 1.5s to run, and there are likely to be more tests in this vein once further branch types are added. The feeling on IRC was that 1.5s is a bit much for a single test, so I've restricted it to SystemZ hosts for now. The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests. A later patch will remove the {{g}}s from that directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182274 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputsJustin Holewinski2013-05-20
| | | | | | | | | | | | | | | This converter currently only handles global variables in address space 0. For these variables, they are promoted to address space 1 (global memory), and all uses are updated to point to the result of a cvta.global instruction on the new variable. The motivation for this is address space 0 global variables are illegal since we cannot declare variables in the generic address space. Instead, we place the variables in address space 1 and explicitly convert the pointer to address space 0. This is primarily intended to help new users who expect to be able to place global variables in the default address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182254 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we ↵Justin Holewinski2013-05-20
| | | | | | need to use .u8 for i1 parameters for kernels. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182253 91177308-0d34-0410-b5e6-96231b3b80d8
* PR15868 fix.Stepan Dyatkovskiy2013-05-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduction: In case when stack alignment is 8 and GPRs parameter part size is not N*8: we add padding to GPRs part, so part's last byte must be recovered at address K*8-1. We need to do it, since remained (stack) part of parameter starts from address K*8, and we need to "attach" "GPRs head" without gaps to it: Stack: |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes... [ [padding] [GPRs head] ] [ ------ Tail passed via stack ------ ... FIX: Note, once we added padding we need to correct *all* Arg offsets that are going after padded one. That's why we need this fix: Arg offsets were never corrected before this patch. See new test-cases included in patch. We also don't need to insert padding for byval parameters that are stored in GPRs only. We need pad only last byval parameter and only in case it outsides GPRs and stack alignment = 8. Though, stack area, allocated for recovered byval params, must satisfy "Size mod 8 = 0" restriction. This patch reduces stack usage for some cases: We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be "packed" with alignment 4 in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182237 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable remote MCJIT on pre-v6 ARMRenato Golin2013-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182235 91177308-0d34-0410-b5e6-96231b3b80d8
* Also expand 64-bit bitcasts.Jakob Stoklund Olesen2013-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182229 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement spill and fill of I64Regs.Jakob Stoklund Olesen2013-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182228 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark i64 SETCC as expand so it is turned into a SELECT_CC.Jakob Stoklund Olesen2013-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182227 91177308-0d34-0410-b5e6-96231b3b80d8
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