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* Merging r168361, r168346 and r168227 into 3.2 branch releasePawel Wodnicki2012-11-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merging r168361: Fix PR14132 and handle OOB loads speculated throuh PHI nodes. The issue is that we may end up with newly OOB loads when speculating a load into the predecessors of a PHI node, and this confuses the new integer splitting logic in some cases, triggering an assertion failure. In fact, the branch in question must be dead code as it loads from a too-narrow alloca. Add code to handle this gracefully and leave the requisite FIXMEs for both optimizing more aggressively and doing more to aid sanitizing invalid code which triggers these patterns. Merging r168346: ------------------------------------------------------------------------ Rework the rewriting of loads and stores for vector and integer allocas to properly handle the combinations of these with split integer loads and stores. This essentially replaces Evan's r168227 by refactoring the code in a different way, and trynig to mirror that refactoring in both the load and store sides of the rewriting. Generally speaking there was some really problematic duplicated code here that led to poorly founded assumptions and then subtle bugs. Now much of the code actually flows through and follows a more consistent style and logical path. There is still a tiny bit of duplication on the store side of things, but it is much less bad. This also changes the logic to never re-use a load or store instruction as that was simply too error prone in practice. I've added a few tests (one a reduction of the one in Evan's original patch, which happened to be the same as the report in PR14349). I'm going to look at adding a few more tests for things I found and fixed in passing (such as the volatile tests in the vectorizable predicate). This patch has survived bootstrap, and modulo one bugfix survived Duncan's test suite, but let me know if anything else explodes. Merging r168227: Teach SROA rewriteVectorizedStoreInst to handle cases when the loaded value is narrower than the stored value. rdar://12713675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168443 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r168197: into 3.2 release branchPawel Wodnicki2012-11-21
| | | | | | | | | | | | | | Preserve address space of forward-referenced global variables in the LL parser Before, the parser would assert on the following code: @a2 = global i8 addrspace(1)* @a @a = addrspace(1) global i8 0 because the type of @a was "i8*" instead of "i8 addrspace(1)*" when parsing the initializer for @a2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168435 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge in r168364 to disable MCJIT execution engine tests on ppc32 (which ↵Andrew Kaylor2012-11-20
| | | | | | doesn't currently support MCJIT). git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168392 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge in PPC internal-as fixes: r167861, r167862, r167863, r167875, r167860, ↵Hal Finkel2012-11-20
| | | | | | r167864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168351 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge in r168316 so that the proper JIT tests are run on PPC.Hal Finkel2012-11-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168349 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r167718 into 3.2 release branchPawel Wodnicki2012-11-19
| | | | | | | | | | | Fix PR14314 - Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168336 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r167948, r168198: into the 3.2 release branchPawel Wodnicki2012-11-19
| | | | | | | | | | | | | | | | r168198 [NVPTX] Order global variables in def-use order before emiting them in the final assembly r167948 [NVPTX] Implement custom lowering of loads/stores for i1 Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168335 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r167855 into 3.2 relase branchPawel Wodnicki2012-11-19
| | | | | | | | | | | | Do not consider a machine instruction that uses and defines the same physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168334 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge r168147 from trunk:Hans Wennborg2012-11-16
| | | | | | | | | | | | | | Constant::IsThreadDependent(): Use dyn_cast<Constant> instead of cast It turns out that the operands of a Constant are not always themselves Constant. For example, one of the operands of BlockAddress is BasicBlock, which is not a Constant. This should fix the dragonegg-x86_64-linux-gcc-4.6-test build which broke in r168037. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168193 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge r168037 from trunk:Hans Wennborg2012-11-16
| | | | | | | | | | | | | | | | | Make GlobalOpt be conservative with TLS variables (PR14309) For global variables that get the same value stored into them everywhere, GlobalOpt will replace them with a constant. The problem is that a thread-local GlobalVariable looks like one value (the address of the TLS var), but is different between threads. This patch introduces Constant::isThreadDependent() which returns true for thread-local variables and constants which depend on them (e.g. a GEP into a thread-local array), and teaches GlobalOpt not to track such values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168192 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge BBVectorizer changes r167731, r167743, r167750, r167784, r167811, r167817.Hal Finkel2012-11-14
| | | | | | | | | These changes fix a serious interaction problem with the cost model on x86 that could cause the vectorizer to enter an infinite loop (and sometimes crash in other ways). git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@167993 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add more precise PTX/SM target attributesJustin Holewinski2012-11-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove hard-coded constant in Transforms/InstCombine/memcmp-1.llMeador Inge2012-11-11
| | | | | | | | | | | | | | | | | | | | | | | | | | Transforms/InstCombine/memcmp-1.ll has a test case that looks like: @foo = constant [4 x i8] c"foo\00" @hel = constant [4 x i8] c"hel\00" ... %mem1 = getelementptr [4 x i8]* @hel, i32 0, i32 0 %mem2 = getelementptr [4 x i8]* @foo, i32 0, i32 0 %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 3) ret i32 %ret ; CHECK: ret i32 2 The folded return value (2 above) is computed using the system memcmp that the compiler is linked with. This can return different values on different systems. The test was originally written on an OS X 10.7.5 x86-64 box and passed. However, it failed on one of the x86-64 FreeBSD buildbots because the system memcpy on that machine returned a different value (1 instead of 2). I fixed the test by checking the folding constants with regexes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167691 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Migrate memset optimizationsMeador Inge2012-11-11
| | | | | | | This patch migrates the memset optimizations from the simplify-libcalls pass into the instcombine library call simplifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167689 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Migrate memmove optimizationsMeador Inge2012-11-11
| | | | | | | This patch migrates the memmove optimizations from the simplify-libcalls pass into the instcombine library call simplifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167687 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Migrate memcpy optimizationsMeador Inge2012-11-11
| | | | | | | This patch migrates the memcpy optimizations from the simplify-libcalls pass into the instcombine library call simplifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167686 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Migrate memcmp optimizationsMeador Inge2012-11-11
| | | | | | | This patch migrates the memcmp optimizations from the simplify-libcalls pass into the instcombine library call simplifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167683 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Migrate strstr optimizationsMeador Inge2012-11-11
| | | | | | | This patch migrates the strstr optimizations from the simplify-libcalls pass into the instcombine library call simplifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167682 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Migrate strcspn optimizationsMeador Inge2012-11-10
| | | | | | | This patch migrates the strcspn optimizations from the simplify-libcalls pass into the instcombine library call simplifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167675 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert an improper CodeGen test to a MC test.Evan Cheng2012-11-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167663 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Query target library information to gate libcall simplificationsMeador Inge2012-11-10
| | | | | | | | | Several of the simplifiers migrated from the simplify-libcalls pass to the instcombine pass were not correctly checking the target library information to gate the simplifications. This patch ensures that the check is made. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167660 91177308-0d34-0410-b5e6-96231b3b80d8
* xfail a bad test. This is a MC test but it's dependent on a codegen ↵Evan Cheng2012-11-10
| | | | | | optimization which is now disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167658 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the Thumb no-return call optimization:Evan Cheng2012-11-10
| | | | | | | | | | | | | mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.Craig Topper2012-11-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Use ABI alignment for parameters when alignment is not specified.Justin Holewinski2012-11-09
| | | | | | Affects SM 2.0+. Fixes bug 13324. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167646 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assertions in updateRegMaskSlots().Jakob Stoklund Olesen2012-11-09
| | | | | | | | | The RegMaskSlots contains 'r' slots while NewIdx and OldIdx are 'B' slots. This broke the checks in the assertions. This fixes PR14302. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167625 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: switch to new memory_order constants (ABI compatible)Dmitry Vyukov2012-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167615 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: instrument all atomics (including fetch_add, exchange, cas, etc)Dmitry Vyukov2012-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167612 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for memory runtime check. When we can, we calculate array bounds.Nadav Rotem2012-11-09
| | | | | | | | | If the arrays are found to be disjoint then we run the vectorized version of the loop. If they are not, we run the scalar code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167608 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/ConstantFolding.cpp: Make ReadDataFromGlobal() and ↵NAKAMURA Takumi2012-11-08
| | | | | | FoldReinterpretLoadFromConstPtr() Big-endian-aware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167595 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit modified r167540.Amara Emerson2012-11-08
| | | | | | | | Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167574 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RTM from TSX extensionMichael Liao2012-11-08
| | | | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Migrate strspn optimizationsMeador Inge2012-11-08
| | | | | | | This patch migrates the strspn optimizations from the simplify-libcalls pass into the instcombine library call simplifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167568 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a relocation visitor to lib object. This works via caching relocatedEric Christopher2012-11-07
| | | | | | | values in a map that can be passed to consumers. Add a testcase that ensures this works for llvm-dwarfdump. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167558 91177308-0d34-0410-b5e6-96231b3b80d8
* Only do switch-to-lookup table transformation when TargetTransformInfoHans Wennborg2012-11-07
| | | | | | is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167552 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.Akira Hatanaka2012-11-07
| | | | | | | Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167548 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bad test IR in switch_to_lookup_table.llHans Wennborg2012-11-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167543 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Heuristics based on the machine model.Andrew Trick2012-11-07
| | | | | | | | | | | | | | misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8
* CostModel: add another known vector trunc optimization.Nadav Rotem2012-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167488 91177308-0d34-0410-b5e6-96231b3b80d8
* Cost Model: add tables for some avx type-conversion hacks.Nadav Rotem2012-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167480 91177308-0d34-0410-b5e6-96231b3b80d8
* CostModel: Add tables for the common x86 compares.Nadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167421 91177308-0d34-0410-b5e6-96231b3b80d8
* Code Model: Improve the accuracy of the zext/sext/trunc vector cost estimation.Nadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167412 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR14264 cause by commit r167237 which did not take into account aKevin Enderby2012-11-05
| | | | | | | | | possible buffer change with a .macro directive. rdar://12637628 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167408 91177308-0d34-0410-b5e6-96231b3b80d8
* Cost Model: Normalize the insert/extract index when splitting typesNadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167402 91177308-0d34-0410-b5e6-96231b3b80d8
* Cost Model: teach the cost model about expanding integers.Nadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167401 91177308-0d34-0410-b5e6-96231b3b80d8
* On PowerPC64, integer return values (as well as arguments) are supposedUlrich Weigand2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | to be extended to a full register. This is modeled in the IR by marking the return value (or argument) with a signext or zeroext attribute. However, while these attributes are respected for function arguments, they are currently ignored for function return values by the PowerPC back-end. This patch updates PPCCallingConv.td to ask for the promotion to i64, and fixes LowerReturn and LowerCallResult to implement it. The new test case verifies that both arguments and return values are properly extended when passing them; and also that the optimizers understand incoming argument and return values are in fact guaranteed by the ABI to be extended. The patch caused a spurious breakage in CodeGen/PowerPC/coalesce-ext.ll, since the test case used a "ret" instruction to create a use of an i32 value at the end of the function (to set up data flow as required for what the test is intended to test). Since there's now an implicit promotion to i64, that data flow no longer works as expected. To fix this, this patch now adds an extra "add" to ensure we have an appropriate use of the i32 value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167396 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the cost of abnormal x86 instruction lowering as a table.Nadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167395 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the PowerPC-specific inline asm Z constraint and y modifier.Hal Finkel2012-11-05
| | | | | | | | | | The Z constraint specifies an r+r memory address, and the y modifier expands to the "r, r" in the asm string. For this initial implementation, the base register is forced to r0 (which has the special meaning of 0 for r+r addressing on PowerPC) and the full address is taken in the second register. In the future, this should be improved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167388 91177308-0d34-0410-b5e6-96231b3b80d8
* [PATCH] PowerPC: Expand load extend vector operationsAdhemerval Zanella2012-11-05
| | | | | | | | | This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for vector types when altivec is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167386 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't infer whether a value is captured in the current function from theRichard Osborne2012-11-05
| | | | | | | | | | 'nocapture' attribute. The nocapture attribute only specifies that no copies are made that outlive the function. This isn't the same as there being no copies at all. This fixes PR14045. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167381 91177308-0d34-0410-b5e6-96231b3b80d8
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