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path: root/utils/TableGen/CodeGenDAGPatterns.cpp
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* [TableGen] Handle ValueType in CodeGenDAGPatterns GetNumNodeResultsHal Finkel2014-01-02
| | | | | | | | | | | | A ValueType in a pattern dag is a type cast, and GetNumNodeResults should handle it (the type cast has only one result). This comes up, for example, during the type checking of pattern fragments, for example, AArch64's Neon_combine_2d fragment is: dag Operands = (ops node:$Rm, node:$Rn); dag Fragment = (v2f64 (concat_vectors (v1f64 node:$Rm), (v1f64 node:$Rn))); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198347 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: remove unused variable.Ahmed Bougacha2013-10-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193527 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Refactor DAG patterns to enable parsing one pattern at a time.Ahmed Bougacha2013-10-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193526 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace EVT with MVT in CodeGenDAGAPatterns.cpp.Craig Topper2013-09-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191355 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix formatting to match coding standards.Craig Topper2013-09-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191280 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-04
| | | | | | specifying the vector size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow types to be omitted in output patterns.Jakob Stoklund Olesen2013-03-24
| | | | | | | | | | This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow direct value types to be used in instruction 'set' patterns.Jakob Stoklund Olesen2013-03-24
| | | | | | | | | | | | This makes it possible to define instruction patterns like this: def LDri : F3_2<3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRri:$addr))]>; ~~~ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow direct value types in pattern definitions.Jakob Stoklund Olesen2013-03-23
| | | | | | | | | | | | | | | | | Just like register classes, value types can be used in two ways in patterns: (sext_inreg i32:$src, i16) In a named leaf node like i32:$src, the value type simply provides the type of the node directly. This simplifies type inference a lot compared to the current practice of specifiying types indirectly with register classes. As an unnamed leaf node, like i16 above, the value type represents itself as an MVT::Other immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828 91177308-0d34-0410-b5e6-96231b3b80d8
* Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.Jakob Stoklund Olesen2013-03-23
| | | | | | | | | | | | | | | | | | | | | A register class can appear as a leaf TreePatternNode with and without a name: (COPY_TO_REGCLASS GPR:$src, F8RC) In a named leaf node like GPR:$src, the register class provides type information for the named variable represented by the node. The TypeSet for such a node is the set of value types that the register class can represent. In an unnamed leaf node like F8RC above, the register class represents itself as a kind of immediate. Such a node has the type MVT::i32, we'll never create a virtual register representing it. This change makes it possible to remove the special handling of COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend TableGen instruction selection matcher to improve handlingUlrich Weigand2013-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177428 91177308-0d34-0410-b5e6-96231b3b80d8
* Extract a method.Jakob Stoklund Olesen2013-03-18
| | | | | | | This computes the type of an instruction operand or result based on the records in the instruction's ins and outs lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177244 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-17
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
* Sort the #include lines for utils/...Chandler Carruth2012-12-04
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't return false when the function's return type is a pointer.Kaelyn Uhrain2012-10-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166719 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-25
| | | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-10
| | | | | | Also, some minor cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-10
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
* Soften the pattern-can-never-match error in TableGen into a warning. This ↵Owen Anderson2012-09-19
| | | | | | pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164256 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor Record* by-ID comparator to Record.hSean Silva2012-09-19
| | | | | | | | | | | This is a generally useful utility; there's no reason to have it hidden in CodeGenDAGPatterns.cpp. Also, rename it to fit the other comparators in Record.h Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164189 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve tblgen code cleanliness: create an unknown_class, from which the ↵Owen Anderson2012-09-11
| | | | | | unknown def inherits. Make tblgen check for that class, rather than checking for the def itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163664 91177308-0d34-0410-b5e6-96231b3b80d8
* Tablegen: Add OperandWithDefaultOps Operand typeTom Stellard2012-09-06
| | | | | | | This Operand type takes a default argument, and is initialized to this value if it does not appear in a patter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163315 91177308-0d34-0410-b5e6-96231b3b80d8
* Check all patterns for missing instruction flags.Jakob Stoklund Olesen2012-08-28
| | | | | | | Both single-instruction and multi-instruction patterns can be checked for missing mayLoad / mayStore, and hasSideEffects flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162734 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-24
| | | | | | | Reviewed offline by chandlerc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
* Infer instruction properties from single-instruction patterns.Jakob Stoklund Olesen2012-08-24
| | | | | | | | | | | | | | | | | | | | | Previously, instructions without a primary patterns wouldn't get their properties inferred. Now, we use all single-instruction patterns for inference, including 'def : Pat<>' instances. This causes a lot of instruction flags to change. - Many instructions no longer have the UnmodeledSideEffects flag because their flags are now inferred from a pattern. - Instructions with intrinsics will get a mayStore flag if they already have UnmodeledSideEffects and a mayLoad flag if they already have mayStore. This is because intrinsics properties are linear. - Instructions with atomic_load patterns get a mayStore flag because atomic loads can't be reordered. The correct workaround is to create pseudo-instructions instead of using normal loads. PR13693. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop inferring isVariadic from instruction patterns.Jakob Stoklund Olesen2012-08-24
| | | | | | | | | | | | | | | | | | Instructions are now only marked as variadic if they use variable_ops in their ins list. A variadic SDNode is typically used for call nodes that have the call arguments as operands. A variadic MachineInstr can actually encode a variable number of operands, for example ARM's stm/ldm instructions. A call instruction does not have to be variadic. The call argument registers are added as implicit operands. This change remove the MCID::Variadic flags from most call and return instructions, allowing us to better verify their operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162599 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify explicit instruction properties when they can be inferred.Jakob Stoklund Olesen2012-08-24
| | | | | | | | | It is now allowed to explicitly set hasSideEffects, mayStore, and mayLoad on instructions with patterns. Verify that the patterns are consistent with the explicit flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162569 91177308-0d34-0410-b5e6-96231b3b80d8
* Heed guessInstructionProperties, and stop warning on redundant flags.Jakob Stoklund Olesen2012-08-24
| | | | | | | | | | | | Emit TableGen errors if guessInstructionProperties is 0 and instruction properties can't be inferred from patterns. Allow explicit instruction properties even when they can be inferred. This patch doesn't change the TableGen output. Redundant properties are not yet verified because the tree has errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162516 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Pattern<> references to null_frag are a nop.Jim Grosbach2012-07-17
| | | | | | | | A standalone pattern defined in a multiclass expansion should handle null_frag references just like patterns on instructions. Follow-up to r160333. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160384 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Allow conditional instruction pattern in multiclass.Jim Grosbach2012-07-17
| | | | | | | | | | | | | | | | | | | Define a 'null_frag' SDPatternOperator node, which if referenced in an instruction Pattern, results in the pattern being collapsed to be as-if '[]' had been specified instead. This allows supporting a multiclass definition where some instaniations have ISel patterns associated and others do not. For example, multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> { def _x : myI<(outs rc:), (ins rc:), []>; def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>; } defm foo : myMulti<GRa, not>; defm bar : myMulti<GRb>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: remove duplicated newlines.Benjamin Kramer2012-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155038 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. No need for a Twine here, as it's just constants.Jim Grosbach2012-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155026 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up warning text. Remove extraneous prefix.Jim Grosbach2012-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155015 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen use PrintWarning rather than fprintf(stderr,...) for warnings.Jim Grosbach2012-04-18
| | | | | | That way we get source line number information from the diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155014 91177308-0d34-0410-b5e6-96231b3b80d8
* Include cstdio in a few place that depended on getting it transitively ↵Benjamin Kramer2012-03-23
| | | | | | through StringExtras.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153328 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide better messages in llvm_unreachable.David Blaikie2012-01-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148293 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unreachable code. (replace with llvm_unreachable to help GCC where ↵David Blaikie2012-01-17
| | | | | | necessary) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148284 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete CodeInit and CodeRecTy from TableGen.Jakob Stoklund Olesen2012-01-13
| | | | | | | The code type was always identical to a string anyway. Now it is simply a synonym. The code literal syntax [{...}] is still valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148092 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
* Ban rematerializable instructions with side effects.Jakob Stoklund Olesen2011-10-14
| | | | | | | | | | TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-01
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
* Unconstify InitsDavid Greene2011-07-29
| | | | | | | | Remove const qualifiers from Init references, per Chris' request. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Create Inits Via Factory MethodDavid Greene2011-07-29
| | | | | | | Replace uses of new *Init with *Init::get. This hides the allocation implementation so that we can unique Inits in various ways. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136486 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Constify InitsDavid Greene2011-07-29
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
* Intern all RecTy subclass instances to avoid duplicates.Jakob Stoklund Olesen2011-07-18
| | | | | | | | | | | | | | | | | Make all of the RecTy constructors private, and use get() factory methods instead. Return singleton instances when it makes sense. ListTy instance pointers are stored in the element RecTy instance. BitsRecTy instance pointers, one per length, are stored in a static vector. Also unique DefInit instances. A Record has a unique DefInit which has a unique RecordRecTy instance. This saves some 200k-300k RecTy allocations when parsing ARM.td. It reduces TableGen's heap usage by almost 50%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135399 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-11
| | | | | | | in multiple buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
* Use get(0 Instead of Create()David Greene2011-07-11
| | | | | | | | Respond to some feedback asking for a name change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134921 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Make Inits FoldableDavid Greene2011-07-11
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo.Jim Grosbach2011-07-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134563 91177308-0d34-0410-b5e6-96231b3b80d8
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