| Commit message (Collapse) | Author | Age |
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121196 91177308-0d34-0410-b5e6-96231b3b80d8
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CodeGenInstruction into its own helper class. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116069 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116030 91177308-0d34-0410-b5e6-96231b3b80d8
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to IntrReadWriteArgMem, as it's for reading as well as writing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
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This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101881 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101880 91177308-0d34-0410-b5e6-96231b3b80d8
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comment in the generated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99794 91177308-0d34-0410-b5e6-96231b3b80d8
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where an incorrect number of operands is provided to an sdnode instead
of just a few cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99761 91177308-0d34-0410-b5e6-96231b3b80d8
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and those derived from them. These are obnoxious because
they were written as: PatLeaf<(bitconvert). Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99759 91177308-0d34-0410-b5e6-96231b3b80d8
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transforming it into (add (i32 GPR), 4). This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align. This allows us to fold an extra load
in the changed testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99756 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99747 91177308-0d34-0410-b5e6-96231b3b80d8
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by rotating it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99746 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99744 91177308-0d34-0410-b5e6-96231b3b80d8
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same vt multiple times for a register. For example,
ECX is in 5 different i32 reg classes, just return
1 i32 instead of 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99727 91177308-0d34-0410-b5e6-96231b3b80d8
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from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99726 91177308-0d34-0410-b5e6-96231b3b80d8
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results forward. We can now handle an instruction that
produces one implicit def and one result instead of one or
the other when not at the root of the pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99725 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99703 91177308-0d34-0410-b5e6-96231b3b80d8
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in some more places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99366 91177308-0d34-0410-b5e6-96231b3b80d8
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instead of reimplementing it wrong and poorly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99357 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99354 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99353 91177308-0d34-0410-b5e6-96231b3b80d8
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instead of as a single element list with VoidTy. Now with a fix
for the verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99206 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99111 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99011 91177308-0d34-0410-b5e6-96231b3b80d8
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instead of as a single element list with VoidTy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99009 91177308-0d34-0410-b5e6-96231b3b80d8
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ApplyTypeConstraint) and make it handle multiple result nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99003 91177308-0d34-0410-b5e6-96231b3b80d8
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to maintain a list of types (one for each result of
the node) instead of a single type. There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98999 91177308-0d34-0410-b5e6-96231b3b80d8
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we don't blow the smallvector as often. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98968 91177308-0d34-0410-b5e6-96231b3b80d8
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from the pattern if present, and we use it instead of the bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98938 91177308-0d34-0410-b5e6-96231b3b80d8
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dag isel gen instead of instruction properties. This
allows the oh-so-useful behavior of matching a variadic
non-root node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98933 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98927 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98918 91177308-0d34-0410-b5e6-96231b3b80d8
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to a vector that CGT stores instead of synthesizing it on every
call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98906 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98900 91177308-0d34-0410-b5e6-96231b3b80d8
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like this:
def : Pat<(add ...),
(FOOINST)>;
When fooinst only has a single implicit def (e.g. to R1). This will be handled
as if written as (set R1, (FOOINST ...))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98897 91177308-0d34-0410-b5e6-96231b3b80d8
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shouldn't change this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98872 91177308-0d34-0410-b5e6-96231b3b80d8
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Add checking that the input/output operand list in spelled right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98865 91177308-0d34-0410-b5e6-96231b3b80d8
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now enforces that input/output named values have hte same type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98535 91177308-0d34-0410-b5e6-96231b3b80d8
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changing the primary datastructure from being a
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!
This changes more things than I remember, but one major
innovation here is that it enforces that named input
values agree in type with their output values.
This also eliminates code that transparently assumes (in
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.
This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.
With all the recent target changes, this causes no
functionality change!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98534 91177308-0d34-0410-b5e6-96231b3b80d8
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needs to be majorly refactored, but this spot bugfix allows
things like:
def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle (v4i32 node:$lhs), node:$rhs), [{
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97952 91177308-0d34-0410-b5e6-96231b3b80d8
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(set GPR, somecomplexpattern)
if somecomplexpattern doesn't declare what it can match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97513 91177308-0d34-0410-b5e6-96231b3b80d8
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ordered correctly. Previously it would get in trouble when
two patterns were too similar and give them nondet ordering.
We force this by using the record ID order as a fallback.
The testsuite diff is due to alpha patterns being ordered
slightly differently, the change is a semantic noop afaict:
< lda $0,-100($16)
---
> subq $16,100,$0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97509 91177308-0d34-0410-b5e6-96231b3b80d8
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node is always guaranteed to have a particular type
instead of hacking in ISD::STORE explicitly. This allows
us to use implied types for a broad range of nodes, even
target specific ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97355 91177308-0d34-0410-b5e6-96231b3b80d8
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respects -debug-only=something-else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97307 91177308-0d34-0410-b5e6-96231b3b80d8
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input/output patterns have the same type. It turns out that
this triggers all the time because we don't infer types
between these boundaries. Until we do, don't turn this on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96905 91177308-0d34-0410-b5e6-96231b3b80d8
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