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path: root/utils/TableGen/CodeGenInstruction.h
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* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-17
| | | | | | | | | | | | | | | | | | | | | | and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
* add (and document) the ability for alias results to haveChris Lattner2010-11-06
| | | | | | | | | fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
* generalize alias support to allow the result of an alias toChris Lattner2010-11-06
| | | | | | | | add fixed immediate values. Move the aad and aam aliases to use this, and document it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118350 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a bug where we had an implicit assumption that theChris Lattner2010-11-06
| | | | | | | | | result instruction operand numbering matched the result pattern. Fixing this allows us to move the xchg/test aliases to the .td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118334 91177308-0d34-0410-b5e6-96231b3b80d8
* Reimplement BuildResultOperands to be in terms of the result instruction'sChris Lattner2010-11-06
| | | | | | | | | | | | | | | | | | | operand list instead of the operand list redundantly declared on the alias or instruction. With this change, we finally remove the ins/outs list on the alias. Before: def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), "movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; After: def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; This also makes the alias mechanism more general and powerful, which will be exploited in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118329 91177308-0d34-0410-b5e6-96231b3b80d8
* disolve a hack, having CodeGenInstAlias decode the alias in the .tdChris Lattner2010-11-06
| | | | | | | file instead of the asmmatcher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118324 91177308-0d34-0410-b5e6-96231b3b80d8
* rewrite EmitConvertToMCInst to iterate over the MCInst operands,Chris Lattner2010-11-02
| | | | | | | | | filling them in one at a time. Previously this iterated over the asmoperands, which left the problem of "holes". The new approach simplifies things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118104 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement enough of the missing instalias support to getChris Lattner2010-11-01
| | | | | | | | | | | | | | | | | | | | aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
* define a new CodeGenInstAlias. It has an asmstring and operand list for now,Chris Lattner2010-11-01
| | | | | | | todo: the result field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117894 91177308-0d34-0410-b5e6-96231b3b80d8
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-01
| | | | | | | CodeGenInstruction into its own helper class. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
* avoid needless throw/catch/rethrow, stringref'ize some simple stuff.Chris Lattner2010-11-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117892 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate the old InstFormatName which is always "AsmString",Chris Lattner2010-11-01
| | | | | | | simplify CodeGenInstruction. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891 91177308-0d34-0410-b5e6-96231b3b80d8
* move FlattenVariants out of AsmMatcherEmitter into a sharedChris Lattner2010-11-01
| | | | | | | | | CodeGenInstruction::FlattenAsmStringVariants method. Use it to simplify the code in AsmWriterInst, which now no longer needs to worry about variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117886 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow targets to optionally specify custom binary encoder functions forJim Grosbach2010-10-12
| | | | | | | | | | operand values. This is useful for operands which require additional trickery to encode into the instruction. For example, the ARM shifted immediate and shifted register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8
* When figuring out which operands match which encoding fields in an instruction,Jim Grosbach2010-10-11
| | | | | | | | | try to match them by name first. If there is no by-name match, fall back to assuming they are in order (this was the previous behavior). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116211 91177308-0d34-0410-b5e6-96231b3b80d8
* trailing whitespaceJim Grosbach2010-10-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116068 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r114703 and r114702, removing the isConditionalMove flag from ↵Owen Anderson2010-09-23
| | | | | | | | | instructions. After further reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an TargetInstrDesc bit to indicate that a given instruction is a ↵Owen Anderson2010-09-23
| | | | | | | | | conditional move. Not intended functionality change, as nothing uses this yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114702 91177308-0d34-0410-b5e6-96231b3b80d8
* Add back in r109901, which adds a Compare flag to the target instructions. It'sBill Wendling2010-08-08
| | | | | | | useful after all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn'tBill Wendling2010-08-06
| | | | | | | | | | | | | | | need the Compare flag after all. --- Reverse-merging r109901 into '.': U include/llvm/Target/TargetInstrDesc.h U include/llvm/Target/Target.td U utils/TableGen/InstrInfoEmitter.cpp U utils/TableGen/CodeGenInstruction.cpp U utils/TableGen/CodeGenInstruction.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110424 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a "Compare" flag to the target instruction descriptor. This will be usedBill Wendling2010-07-30
| | | | | | | | later to identify and possibly remove superfluous compare instructions -- those that are testing for and setting a status flag that should already be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
* hoist some funky logic into CodeGenInstructionChris Lattner2010-03-27
| | | | | | | | | | from two places in CodeGenDAGPatterns.cpp, and use it in DAGISelMatcherGen.cpp instead of using an incorrect predicate that happened to get lucky on our current targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99726 91177308-0d34-0410-b5e6-96231b3b80d8
* capture implicit uses and defs in CodeGenInstructionChris Lattner2010-03-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98879 91177308-0d34-0410-b5e6-96231b3b80d8
* remove some code that was working around old sparc v9 backend bugs.Chris Lattner2010-03-18
| | | | | | | Add checking that the input/output operand list in spelled right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98865 91177308-0d34-0410-b5e6-96231b3b80d8
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
* work around a gcc bug with -Wuninitialized.Chris Lattner2010-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95808 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce a new CodeGenInstruction::ConstraintInfo classChris Lattner2010-02-10
| | | | | | | | | | for representing constraint info semantically instead of as a c expression that will be blatted out to the .inc file. Fix X86RecognizableInstr to use this instead of parsing C code :). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95753 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-29
| | | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. WhenEvan Cheng2009-10-01
| | | | | | | | | | | set, these flags indicate the instructions source / def operands have special register allocation requirement that are not captured in their register classes. Post-allocation passes (e.g. post-alloc scheduler) should not change their allocations. e.g. ARM::LDRD require the two definitions to be allocated even / odd register pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling2008-05-28
| | | | | | | | | | instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-10
| | | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
* add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner2008-01-08
| | | | | | | This is currently not set by anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45748 91177308-0d34-0410-b5e6-96231b3b80d8
* rename hasVariableOperands() -> isVariadic(). Add some comments.Chris Lattner2008-01-07
| | | | | | | | Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8
* the name field of instructions is never set to a non-empty string, Chris Lattner2008-01-07
| | | | | | | just unconditionally use the def name of the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45684 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the impl of CodeGenInstruction out to its own .cpp file, add a ↵Chris Lattner2008-01-06
| | | | | | getName() accessor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45645 91177308-0d34-0410-b5e6-96231b3b80d8
* remove attributions from utils.Chris Lattner2007-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-14
| | | | | | | side effects for machine instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45022 91177308-0d34-0410-b5e6-96231b3b80d8
* Oops. Forgot these.Evan Cheng2007-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44969 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag for indirect branch instructions.Owen Anderson2007-11-12
| | | | | | | Target maintainers: please check that the instructions for your target are correctly marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
* No need for noResults anymore.Evan Cheng2007-07-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40075 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-19
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* Try committing again. Add OptionalDefOperand. Remove clobbersPred.Evan Cheng2007-07-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38498 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-26
| | | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-19
| | | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
* Add clobbersPred - instruction that clobbers condition code / register which ↵Evan Cheng2007-06-06
| | | | | | are used to predicate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8
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