summaryrefslogtreecommitdiff
path: root/utils/TableGen/EDEmitter.cpp
Commit message (Expand)AuthorAge
...
* ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach2011-07-25
* ARM SSAT instruction 5-bit immediate handling.Jim Grosbach2011-07-22
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn n...Owen Anderson2011-07-21
* Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowi...Owen Anderson2011-07-21
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-20
* ARM assembly parsing for MOV (immediate).Jim Grosbach2011-07-19
* Range checking for CDP[2] immediates.Jim Grosbach2011-07-13
* Give the ARM BKPT instruction the right operand type.Jim Grosbach2011-07-13
* Resynchronize EDInfo.h and EDEmitter.cpp.Shantonu Sen2011-07-11
* Don't require pseudo-instructions to carry encoding information.Jim Grosbach2011-07-06
* ARM Assembly support for Thumb mov-immediate.Jim Grosbach2011-06-27
* Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes2011-05-31
* Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane...Mon P Wang2011-05-09
* Remove unused STL header includes.Jay Foad2011-04-23
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-24
* Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson2011-03-18
* Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling2011-03-07
* Narrow right shifts need to encode their immediates differently from a normalBill Wendling2011-03-01
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-14
* Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim2011-02-04
* TableGen: PointerLikeRegClass can be accepted to operand.NAKAMURA Takumi2011-01-26
* Add support for parsing and encoding ARM's official syntax for the BFI instru...Bruno Cardoso Lopes2011-01-18
* Add support to the ARM MC infrastructure to support mcr and friends. This req...Owen Anderson2011-01-13
* Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng2011-01-13
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-14
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-14
* Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ...Owen Anderson2010-12-14
* Revert r121721, which broke buildbots.Owen Anderson2010-12-13
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provid...Owen Anderson2010-12-13
* In Thumb2, direct branches can be encoded as either a "short" conditional bra...Owen Anderson2010-12-13
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-13
* Thumb unconditional branch binary encoding. rdar://8754994Jim Grosbach2010-12-10
* Thumb conditional branch binary encodings. rdar://8745367Jim Grosbach2010-12-10
* Thumb needs a few different encoding schemes for branch targets. RenameJim Grosbach2010-12-09
* The BLX instruction is encoded differently than the BL, because why not? InBill Wendling2010-12-09
* Support the "target" encodings for the CB[N]Z instructions.Bill Wendling2010-12-08
* Add support for loading from a constant pool.Bill Wendling2010-12-08
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-06
* Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach2010-12-01
* Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ...Owen Anderson2010-11-30
* Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson2010-11-30
* Fix the encoding of VLD4-dup alignment.Bob Wilson2010-11-30
* Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ...Jason W Kim2010-11-18
* Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling2010-11-17
* ARM fixup encoding for direct call instructions (BL).Jim Grosbach2010-11-11
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-03
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-01
* Shifter ops are not always free. Do not fold them (especially to formEvan Cheng2010-10-27
* Provide correct encodings for NEON vcvt, which has its own special immediate ...Owen Anderson2010-10-27
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-26
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-08 16:32:30 +0000