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* Constant propagate MachineInstrClassName.Roman Divacky2014-01-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198969 91177308-0d34-0410-b5e6-96231b3b80d8
* All backends use MC now.Rafael Espindola2014-01-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198959 91177308-0d34-0410-b5e6-96231b3b80d8
* reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; ↵Kostya Serebryany2014-01-10
| | | | | | this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198922 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Disable LeakSanitizer in TableGen binaries, see PR18325"Alp Toker2014-01-09
| | | | | | | | | | | To declare or define reserved identifers is undefined behaviour in standard C++. This needs to be addressed in compiler-rt before it can be used in LLVM. See the list discussion for details. This reverts commit r198858. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198884 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable LeakSanitizer in TableGen binaries, see PR18325Kostya Serebryany2014-01-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198858 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-08
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
* The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't ↵Craig Topper2014-01-06
| | | | | | being used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198589 91177308-0d34-0410-b5e6-96231b3b80d8
* Use patterns to remove some duplicate instructions.Craig Topper2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198550 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.Craig Topper2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198547 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove no longer needed x86 disassembler hack.Craig Topper2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198546 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark x86 _alt instructions as AsmParserOnly so they will be omitted from ↵Craig Topper2014-01-05
| | | | | | disassembler without string matches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198545 91177308-0d34-0410-b5e6-96231b3b80d8
* Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode ↵Craig Topper2014-01-05
| | | | | | and remove disassmbler table emitter hack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198544 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-05
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the ↵Craig Topper2014-01-05
| | | | | | corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198530 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. ↵Craig Topper2014-01-05
| | | | | | Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198529 91177308-0d34-0410-b5e6-96231b3b80d8
* Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. ↵Craig Topper2014-01-04
| | | | | | Remove disassembler hack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198515 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it ↵Craig Topper2014-01-04
| | | | | | won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198475 91177308-0d34-0410-b5e6-96231b3b80d8
* [TableGen] Handle ValueType in CodeGenDAGPatterns GetNumNodeResultsHal Finkel2014-01-02
| | | | | | | | | | | | A ValueType in a pattern dag is a type cast, and GetNumNodeResults should handle it (the type cast has only one result). This comes up, for example, during the type checking of pattern fragments, for example, AArch64's Neon_combine_2d fragment is: dag Operands = (ops node:$Rm, node:$Rn); dag Fragment = (v2f64 (concat_vectors (v1f64 node:$Rm), (v1f64 node:$Rn))); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198347 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.Craig Topper2014-01-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198336 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused HasFROperands field from disassembler.Craig Topper2014-01-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198332 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack ↵Craig Topper2014-01-02
| | | | | | from the disassembler table builder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198327 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary stirng comparison from disassembler.Craig Topper2014-01-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198325 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler ↵Craig Topper2014-01-02
| | | | | | table builder doesn't need to string match them to exclude them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198323 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function argument.Craig Topper2014-01-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198291 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper2014-01-01
| | | | | | used. Removes ~11.5K from static tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198284 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-01
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-01
| | | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-01
| | | | | | instructions. These instructions can be handled by MRMXr instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198276 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-31
| | | | | | realized we had no FP disassembler test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-30
| | | | | | can be handled by MRMXr instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198238 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove EscapeFilter. It's funcionality can be covered by correctly using ↵Craig Topper2013-12-30
| | | | | | ExtendedFilter and ExactFilter. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198226 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify filter accepts function to just return 'condition' instead of ↵Craig Topper2013-12-30
| | | | | | branching to return true/false. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198221 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198013 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-20
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197768 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for positionally-encoded operands to FixedLenDecoderEmitterHal Finkel2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, the PowerPC instruction definitions make heavy use of the positional operand encoding heuristic to map operands onto bitfield variables in the instruction definitions. Changing this to use name-based mapping is not trivial, however, because additional infrastructure needs to be designed to handle mapping of complex operands (with multiple suboperands) onto multiple bitfield variables. In the mean time, this adds support for positionally encoded operands to FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC backend. To prevent an accidental reliance on this feature, and to prevent an undesirable interaction with existing disassemblers, a backend must opt-in to this support by setting the new decodePositionallyEncodedOperands instruction-set bit to true. When enabled, this iterates the variables that contribute to the instruction encoding, just as the encoder does, and emulates the procedure the encoder uses to map "numbered" operands to variables. The bit range for each variable is also determined as the encoder determines them. This map is then consulted during the decoder-generator's loop over operands to decode, allowing the decoder to understand both position-based and name-based operand-to-variable mappings. As noted in the comment on the decodePositionallyEncodedOperands definition, this support should be removed once it is no longer needed. There should be no change to existing disassemblers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197691 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for PointerLikeRegClass to FixedLenDecoderEmitterHal Finkel2013-12-19
| | | | | | | | This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter should recognize PointerLikeRegClass operands as register types, and generate register-like decoding calls instead of treating them like immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197680 91177308-0d34-0410-b5e6-96231b3b80d8
* Support little-endian encodings in the FixedLenDecoderEmitterHal Finkel2013-12-17
| | | | | | | | | | | | | | | The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197532 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-16
| | | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct word hyphenationsAlp Toker2013-12-05
| | | | | | | This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196471 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code.Rafael Espindola2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196066 91177308-0d34-0410-b5e6-96231b3b80d8
* [weak vtables] Place class definitions into anonymous namespaces to prevent ↵Juergen Ributzka2013-11-19
| | | | | | | | | | weak vtables. This patch places class definitions in implementation files into anonymous namespaces to prevent weak vtables. This eliminates the need of providing an out-of-line definition to pin the vtable explicitly to the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195092 91177308-0d34-0410-b5e6-96231b3b80d8
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-19
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r194865 and r194874.Alexey Samsonov2013-11-18
| | | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo.Ahmed Bougacha2013-11-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194978 91177308-0d34-0410-b5e6-96231b3b80d8
* Small improvement to InstrinsicEmitter::EmitAttributes. This change removes ↵Owen Anderson2013-11-16
| | | | | | | | | the “pushing” and “clearing” of the SmallVector and instead uses const arrays to pass the attributeKinds to AttributeSet::get . Patch by Aditya Nandakumar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194899 91177308-0d34-0410-b5e6-96231b3b80d8
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-15
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-03
| | | | | | | added EVEX_KZ to tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193959 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower stackmap intrinsics directly to their target opcode in the DAG builder.Andrew Trick2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193769 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable variable arguments support for intrinsics.Andrew Trick2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193766 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193765 91177308-0d34-0410-b5e6-96231b3b80d8
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