From 0b74e32c2e345b9b151ee809505475914bbfd5eb Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Thu, 16 May 2013 00:27:17 +0000 Subject: Merging r181577: ------------------------------------------------------------------------ r181577 | tstellar | 2013-05-09 19:09:29 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand SRA for v4i32/v2i32 v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard Signed-off-by: Aaron Watry NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181951 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/R600ISelLowering.cpp | 2 ++ test/CodeGen/R600/sra.ll | 13 +++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 test/CodeGen/R600/sra.ll diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index 6dec4d1dbe..ac56ed8643 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -50,6 +50,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : setOperationAction(ISD::SHL, MVT::v2i32, Expand); setOperationAction(ISD::SRL, MVT::v4i32, Expand); setOperationAction(ISD::SRL, MVT::v2i32, Expand); + setOperationAction(ISD::SRA, MVT::v4i32, Expand); + setOperationAction(ISD::SRA, MVT::v2i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand); setOperationAction(ISD::UDIV, MVT::v4i32, Expand); setOperationAction(ISD::UREM, MVT::v4i32, Expand); diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll new file mode 100644 index 0000000000..972542d346 --- /dev/null +++ b/test/CodeGen/R600/sra.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @ashr_v4i32 +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { + %result = ashr <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} -- cgit v1.2.3