From 189fe78e2f8be4e1eb166c495788aa4d4c87517c Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Wed, 21 May 2014 23:40:26 +0000 Subject: Make early if conversion dependent upon the subtarget and add a subtarget hook to enable. Unconditionally add to the pass pipeline for targets that might want to use it. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209340 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetSubtargetInfo.h | 3 +++ lib/CodeGen/EarlyIfConversion.cpp | 4 ++++ lib/Target/ARM64/ARM64Subtarget.cpp | 8 ++++++++ lib/Target/ARM64/ARM64Subtarget.h | 2 ++ lib/Target/ARM64/ARM64TargetMachine.cpp | 7 +------ lib/Target/PowerPC/PPCSubtarget.h | 2 ++ lib/Target/PowerPC/PPCTargetMachine.cpp | 8 ++------ lib/Target/X86/X86Subtarget.cpp | 12 ++++++++++++ lib/Target/X86/X86Subtarget.h | 2 ++ lib/Target/X86/X86TargetMachine.cpp | 13 ++----------- 10 files changed, 38 insertions(+), 23 deletions(-) diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h index e3febfb40f..c0c342b22e 100644 --- a/include/llvm/Target/TargetSubtargetInfo.h +++ b/include/llvm/Target/TargetSubtargetInfo.h @@ -94,6 +94,9 @@ public: /// scheduling, DAGCombine, etc.). virtual bool useAA() const; + /// \brief Enable the use of the early if conversion pass. + virtual bool enableEarlyIfConversion() const { return false; } + /// \brief Reset the features for the subtarget. virtual void resetSubtargetFeatures(const MachineFunction *MF) { } }; diff --git a/lib/CodeGen/EarlyIfConversion.cpp b/lib/CodeGen/EarlyIfConversion.cpp index e3190241cd..b621e10177 100644 --- a/lib/CodeGen/EarlyIfConversion.cpp +++ b/lib/CodeGen/EarlyIfConversion.cpp @@ -776,6 +776,10 @@ bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) { bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n" << "********** Function: " << MF.getName() << '\n'); + // Only run if conversion if the target wants it. + if (!MF.getTarget().getSubtarget().enableEarlyIfConversion()) + return true; + TII = MF.getTarget().getInstrInfo(); TRI = MF.getTarget().getRegisterInfo(); SchedModel = diff --git a/lib/Target/ARM64/ARM64Subtarget.cpp b/lib/Target/ARM64/ARM64Subtarget.cpp index 528cfc97cb..d81e21b51d 100644 --- a/lib/Target/ARM64/ARM64Subtarget.cpp +++ b/lib/Target/ARM64/ARM64Subtarget.cpp @@ -26,6 +26,10 @@ using namespace llvm; #define GET_SUBTARGETINFO_TARGET_DESC #include "ARM64GenSubtargetInfo.inc" +static cl::opt +EnableEarlyIfConvert("arm64-early-ifcvt", cl::desc("Enable the early if " + "converter pass"), cl::init(true), cl::Hidden); + ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool LittleEndian) : ARM64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), @@ -105,3 +109,7 @@ void ARM64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, Policy.OnlyTopDown = false; Policy.OnlyBottomUp = false; } + +bool ARM64Subtarget::enableEarlyIfConversion() const override { + return EnableEarlyIfConvert; +} diff --git a/lib/Target/ARM64/ARM64Subtarget.h b/lib/Target/ARM64/ARM64Subtarget.h index 88b9c2e7aa..9cea3c387d 100644 --- a/lib/Target/ARM64/ARM64Subtarget.h +++ b/lib/Target/ARM64/ARM64Subtarget.h @@ -102,6 +102,8 @@ public: void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const override; + + bool enableEarlyIfConversion() const override; }; } // End llvm namespace diff --git a/lib/Target/ARM64/ARM64TargetMachine.cpp b/lib/Target/ARM64/ARM64TargetMachine.cpp index f5c187ceb2..5a8c5c6015 100644 --- a/lib/Target/ARM64/ARM64TargetMachine.cpp +++ b/lib/Target/ARM64/ARM64TargetMachine.cpp @@ -24,10 +24,6 @@ static cl::opt EnableCCMP("arm64-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden); -static cl::opt -EnableEarlyIfConvert("arm64-early-ifcvt", cl::desc("Enable the early if " - "converter pass"), cl::init(true), cl::Hidden); - static cl::opt EnableStPairSuppress("arm64-stp-suppress", cl::desc("Suppress STP for ARM64"), cl::init(true), cl::Hidden); @@ -169,8 +165,7 @@ bool ARM64PassConfig::addInstSelector() { bool ARM64PassConfig::addILPOpts() { if (EnableCCMP) addPass(createARM64ConditionalCompares()); - if (EnableEarlyIfConvert) - addPass(&EarlyIfConverterID); + addPass(&EarlyIfConverterID); if (EnableStPairSuppress) addPass(createARM64StorePairSuppressPass()); return true; diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h index 76f4a318e8..ee43fd5f80 100644 --- a/lib/Target/PowerPC/PPCSubtarget.h +++ b/lib/Target/PowerPC/PPCSubtarget.h @@ -205,6 +205,8 @@ public: TargetSubtargetInfo::AntiDepBreakMode& Mode, RegClassVector& CriticalPathRCs) const override; + bool enableEarlyIfConversion() const override { return hasISEL(); } + // Scheduling customization. bool enableMachineScheduler() const override; void overrideSchedPolicy(MachineSchedPolicy &Policy, diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index fdfb8c9bfc..e9c7797b50 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -148,12 +148,8 @@ bool PPCPassConfig::addPreISel() { } bool PPCPassConfig::addILPOpts() { - if (getPPCSubtarget().hasISEL()) { - addPass(&EarlyIfConverterID); - return true; - } - - return false; + addPass(&EarlyIfConverterID); + return true; } bool PPCPassConfig::addInstSelector() { diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index b94bd712ff..a6ad386b0a 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -35,6 +35,13 @@ using namespace llvm; #define GET_SUBTARGETINFO_CTOR #include "X86GenSubtargetInfo.inc" +// Temporary option to control early if-conversion for x86 while adding machine +// models. +static cl::opt +X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, + cl::desc("Enable early if-conversion on X86")); + + /// ClassifyBlockAddressReference - Classify a blockaddress reference for the /// current subtarget according to how we should reference it in a non-pcrel /// context. @@ -310,3 +317,8 @@ X86Subtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, CriticalPathRCs.clear(); return PostRAScheduler && OptLevel >= CodeGenOpt::Default; } + +bool +X86Subtarget::enableEarlyIfConversion() const override { + return hasCMOV() && X86EarlyIfConv; +} diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index 8ec680efff..703559a476 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -430,6 +430,8 @@ public: bool postRAScheduler() const { return PostRAScheduler; } + bool enableEarlyIfConversion() const override; + /// getInstrItins = Return the instruction itineraries based on the /// subtarget selection. const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index d0449f4232..dae6d4b2e1 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -126,12 +126,6 @@ UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, cl::desc("Minimize AVX to SSE transition penalty"), cl::init(true)); -// Temporary option to control early if-conversion for x86 while adding machine -// models. -static cl::opt -X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, - cl::desc("Enable early if-conversion on X86")); - //===----------------------------------------------------------------------===// // X86 Analysis Pass Setup //===----------------------------------------------------------------------===// @@ -192,11 +186,8 @@ bool X86PassConfig::addInstSelector() { } bool X86PassConfig::addILPOpts() { - if (X86EarlyIfConv && getX86Subtarget().hasCMov()) { - addPass(&EarlyIfConverterID); - return true; - } - return false; + addPass(&EarlyIfConverterID); + return true; } bool X86PassConfig::addPreRegAlloc() { -- cgit v1.2.3