From 27df434c5e8c78e8b3e6e9596b55a6a6bd8d5116 Mon Sep 17 00:00:00 2001 From: Kevin Qin Date: Thu, 14 Nov 2013 06:45:17 +0000 Subject: Add test case for AArch64 NEON instruction set misc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AArch64/neon-misc.ll | 1609 +++++++++++++++++++++++++++++++++++++ test/MC/AArch64/neon-simd-misc.s | 646 +++++++++++++++ 2 files changed, 2255 insertions(+) create mode 100644 test/CodeGen/AArch64/neon-misc.ll create mode 100644 test/MC/AArch64/neon-simd-misc.s diff --git a/test/CodeGen/AArch64/neon-misc.ll b/test/CodeGen/AArch64/neon-misc.ll new file mode 100644 index 0000000000..3fd9a500f4 --- /dev/null +++ b/test/CodeGen/AArch64/neon-misc.ll @@ -0,0 +1,1609 @@ +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s + + +define <8 x i8> @test_vrev16_s8(<8 x i8> %a) #0 { +; CHECK: rev16 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_vrev16q_s8(<16 x i8> %a) #0 { +; CHECK: rev16 v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <8 x i8> @test_vrev32_s8(<8 x i8> %a) #0 { +; CHECK: rev32 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <4 x i16> @test_vrev32_s16(<4 x i16> %a) #0 { +; CHECK: rev32 v{{[0-9]+}}.4h, v{{[0-9]+}}.4h + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <16 x i8> @test_vrev32q_s8(<16 x i8> %a) #0 { +; CHECK: rev32 v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <8 x i16> @test_vrev32q_s16(<8 x i16> %a) #0 { +; CHECK: rev32 v{{[0-9]+}}.8h, v{{[0-9]+}}.8h + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_vrev64_s8(<8 x i8> %a) #0 { +; CHECK: rev64 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <4 x i16> @test_vrev64_s16(<4 x i16> %a) #0 { +; CHECK: rev64 v{{[0-9]+}}.4h, v{{[0-9]+}}.4h + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <2 x i32> @test_vrev64_s32(<2 x i32> %a) #0 { +; CHECK: rev64 v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> undef, <2 x i32> + ret <2 x i32> %shuffle.i +} + +define <2 x float> @test_vrev64_f32(<2 x float> %a) #0 { +; CHECK: rev64 v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %shuffle.i = shufflevector <2 x float> %a, <2 x float> undef, <2 x i32> + ret <2 x float> %shuffle.i +} + +define <16 x i8> @test_vrev64q_s8(<16 x i8> %a) #0 { +; CHECK: rev64 v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <8 x i16> @test_vrev64q_s16(<8 x i16> %a) #0 { +; CHECK: rev64 v{{[0-9]+}}.8h, v{{[0-9]+}}.8h + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_vrev64q_s32(<4 x i32> %a) #0 { +; CHECK: rev64 v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_vrev64q_f32(<4 x float> %a) #0 { +; CHECK: rev64 v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <4 x i16> @test_vpaddl_s8(<8 x i8> %a) #0 { +; CHECK: saddlp v{{[0-9]+}}.4h, v{{[0-9]+}}.8b + %vpaddl.i = tail call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %a) #4 + ret <4 x i16> %vpaddl.i +} + +define <2 x i32> @test_vpaddl_s16(<4 x i16> %a) #0 { +; CHECK: saddlp v{{[0-9]+}}.2s, v{{[0-9]+}}.4h + %vpaddl1.i = tail call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %a) #4 + ret <2 x i32> %vpaddl1.i +} + +define <1 x i64> @test_vpaddl_s32(<2 x i32> %a) #0 { +; CHECK: saddlp v{{[0-9]+}}.1d, v{{[0-9]+}}.2s + %vpaddl1.i = tail call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %a) #4 + ret <1 x i64> %vpaddl1.i +} + +define <4 x i16> @test_vpaddl_u8(<8 x i8> %a) #0 { +; CHECK: uaddlp v{{[0-9]+}}.4h, v{{[0-9]+}}.8b + %vpaddl.i = tail call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %a) #4 + ret <4 x i16> %vpaddl.i +} + +define <2 x i32> @test_vpaddl_u16(<4 x i16> %a) #0 { +; CHECK: uaddlp v{{[0-9]+}}.2s, v{{[0-9]+}}.4h + %vpaddl1.i = tail call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %a) #4 + ret <2 x i32> %vpaddl1.i +} + +define <1 x i64> @test_vpaddl_u32(<2 x i32> %a) #0 { +; CHECK: uaddlp v{{[0-9]+}}.1d, v{{[0-9]+}}.2s + %vpaddl1.i = tail call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %a) #4 + ret <1 x i64> %vpaddl1.i +} + +define <8 x i16> @test_vpaddlq_s8(<16 x i8> %a) #0 { +; CHECK: saddlp v{{[0-9]+}}.8h, v{{[0-9]+}}.16b + %vpaddl.i = tail call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %a) #4 + ret <8 x i16> %vpaddl.i +} + +define <4 x i32> @test_vpaddlq_s16(<8 x i16> %a) #0 { +; CHECK: saddlp v{{[0-9]+}}.4s, v{{[0-9]+}}.8h + %vpaddl1.i = tail call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %a) #4 + ret <4 x i32> %vpaddl1.i +} + +define <2 x i64> @test_vpaddlq_s32(<4 x i32> %a) #0 { +; CHECK: saddlp v{{[0-9]+}}.2d, v{{[0-9]+}}.4s + %vpaddl1.i = tail call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %a) #4 + ret <2 x i64> %vpaddl1.i +} + +define <8 x i16> @test_vpaddlq_u8(<16 x i8> %a) #0 { +; CHECK: uaddlp v{{[0-9]+}}.8h, v{{[0-9]+}}.16b + %vpaddl.i = tail call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %a) #4 + ret <8 x i16> %vpaddl.i +} + +define <4 x i32> @test_vpaddlq_u16(<8 x i16> %a) #0 { +; CHECK: uaddlp v{{[0-9]+}}.4s, v{{[0-9]+}}.8h + %vpaddl1.i = tail call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %a) #4 + ret <4 x i32> %vpaddl1.i +} + +define <2 x i64> @test_vpaddlq_u32(<4 x i32> %a) #0 { +; CHECK: uaddlp v{{[0-9]+}}.2d, v{{[0-9]+}}.4s + %vpaddl1.i = tail call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %a) #4 + ret <2 x i64> %vpaddl1.i +} + +define <4 x i16> @test_vpadal_s8(<4 x i16> %a, <8 x i8> %b) #0 { +; CHECK: sadalp v{{[0-9]+}}.4h, v{{[0-9]+}}.8b + %vpadal1.i = tail call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %a, <8 x i8> %b) #4 + ret <4 x i16> %vpadal1.i +} + +define <2 x i32> @test_vpadal_s16(<2 x i32> %a, <4 x i16> %b) #0 { +; CHECK: sadalp v{{[0-9]+}}.2s, v{{[0-9]+}}.4h + %vpadal2.i = tail call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %a, <4 x i16> %b) #4 + ret <2 x i32> %vpadal2.i +} + +define <1 x i64> @test_vpadal_s32(<1 x i64> %a, <2 x i32> %b) #0 { +; CHECK: sadalp v{{[0-9]+}}.1d, v{{[0-9]+}}.2s + %vpadal2.i = tail call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %a, <2 x i32> %b) #4 + ret <1 x i64> %vpadal2.i +} + +define <4 x i16> @test_vpadal_u8(<4 x i16> %a, <8 x i8> %b) #0 { +; CHECK: uadalp v{{[0-9]+}}.4h, v{{[0-9]+}}.8b + %vpadal1.i = tail call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %a, <8 x i8> %b) #4 + ret <4 x i16> %vpadal1.i +} + +define <2 x i32> @test_vpadal_u16(<2 x i32> %a, <4 x i16> %b) #0 { +; CHECK: uadalp v{{[0-9]+}}.2s, v{{[0-9]+}}.4h + %vpadal2.i = tail call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %a, <4 x i16> %b) #4 + ret <2 x i32> %vpadal2.i +} + +define <1 x i64> @test_vpadal_u32(<1 x i64> %a, <2 x i32> %b) #0 { +; CHECK: uadalp v{{[0-9]+}}.1d, v{{[0-9]+}}.2s + %vpadal2.i = tail call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %a, <2 x i32> %b) #4 + ret <1 x i64> %vpadal2.i +} + +define <8 x i16> @test_vpadalq_s8(<8 x i16> %a, <16 x i8> %b) #0 { +; CHECK: sadalp v{{[0-9]+}}.8h, v{{[0-9]+}}.16b + %vpadal1.i = tail call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %a, <16 x i8> %b) #4 + ret <8 x i16> %vpadal1.i +} + +define <4 x i32> @test_vpadalq_s16(<4 x i32> %a, <8 x i16> %b) #0 { +; CHECK: sadalp v{{[0-9]+}}.4s, v{{[0-9]+}}.8h + %vpadal2.i = tail call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %a, <8 x i16> %b) #4 + ret <4 x i32> %vpadal2.i +} + +define <2 x i64> @test_vpadalq_s32(<2 x i64> %a, <4 x i32> %b) #0 { +; CHECK: sadalp v{{[0-9]+}}.2d, v{{[0-9]+}}.4s + %vpadal2.i = tail call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %a, <4 x i32> %b) #4 + ret <2 x i64> %vpadal2.i +} + +define <8 x i16> @test_vpadalq_u8(<8 x i16> %a, <16 x i8> %b) #0 { +; CHECK: uadalp v{{[0-9]+}}.8h, v{{[0-9]+}}.16b + %vpadal1.i = tail call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %a, <16 x i8> %b) #4 + ret <8 x i16> %vpadal1.i +} + +define <4 x i32> @test_vpadalq_u16(<4 x i32> %a, <8 x i16> %b) #0 { +; CHECK: uadalp v{{[0-9]+}}.4s, v{{[0-9]+}}.8h + %vpadal2.i = tail call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %a, <8 x i16> %b) #4 + ret <4 x i32> %vpadal2.i +} + +define <2 x i64> @test_vpadalq_u32(<2 x i64> %a, <4 x i32> %b) #0 { +; CHECK: uadalp v{{[0-9]+}}.2d, v{{[0-9]+}}.4s + %vpadal2.i = tail call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %a, <4 x i32> %b) #4 + ret <2 x i64> %vpadal2.i +} + +define <8 x i8> @test_vqabs_s8(<8 x i8> %a) #0 { +; CHECK: sqabs v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %vqabs.i = tail call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %a) #4 + ret <8 x i8> %vqabs.i +} + +define <16 x i8> @test_vqabsq_s8(<16 x i8> %a) #0 { +; CHECK: sqabs v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %vqabs.i = tail call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %a) #4 + ret <16 x i8> %vqabs.i +} + +define <4 x i16> @test_vqabs_s16(<4 x i16> %a) #0 { +; CHECK: sqabs v{{[0-9]+}}.4h, v{{[0-9]+}}.4h + %vqabs1.i = tail call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %a) #4 + ret <4 x i16> %vqabs1.i +} + +define <8 x i16> @test_vqabsq_s16(<8 x i16> %a) #0 { +; CHECK: sqabs v{{[0-9]+}}.8h, v{{[0-9]+}}.8h + %vqabs1.i = tail call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %a) #4 + ret <8 x i16> %vqabs1.i +} + +define <2 x i32> @test_vqabs_s32(<2 x i32> %a) #0 { +; CHECK: sqabs v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vqabs1.i = tail call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %a) #4 + ret <2 x i32> %vqabs1.i +} + +define <4 x i32> @test_vqabsq_s32(<4 x i32> %a) #0 { +; CHECK: sqabs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vqabs1.i = tail call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %a) #4 + ret <4 x i32> %vqabs1.i +} + +define <2 x i64> @test_vqabsq_s64(<2 x i64> %a) #0 { +; CHECK: sqabs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vqabs1.i = tail call <2 x i64> @llvm.arm.neon.vqabs.v2i64(<2 x i64> %a) #4 + ret <2 x i64> %vqabs1.i +} + +define <8 x i8> @test_vqneg_s8(<8 x i8> %a) #0 { +; CHECK: sqneg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %vqneg.i = tail call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %a) #4 + ret <8 x i8> %vqneg.i +} + +define <16 x i8> @test_vqnegq_s8(<16 x i8> %a) #0 { +; CHECK: sqneg v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %vqneg.i = tail call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %a) #4 + ret <16 x i8> %vqneg.i +} + +define <4 x i16> @test_vqneg_s16(<4 x i16> %a) #0 { +; CHECK: sqneg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h + %vqneg1.i = tail call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %a) #4 + ret <4 x i16> %vqneg1.i +} + +define <8 x i16> @test_vqnegq_s16(<8 x i16> %a) #0 { +; CHECK: sqneg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h + %vqneg1.i = tail call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %a) #4 + ret <8 x i16> %vqneg1.i +} + +define <2 x i32> @test_vqneg_s32(<2 x i32> %a) #0 { +; CHECK: sqneg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vqneg1.i = tail call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %a) #4 + ret <2 x i32> %vqneg1.i +} + +define <4 x i32> @test_vqnegq_s32(<4 x i32> %a) #0 { +; CHECK: sqneg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vqneg1.i = tail call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %a) #4 + ret <4 x i32> %vqneg1.i +} + +define <2 x i64> @test_vqnegq_s64(<2 x i64> %a) #0 { +; CHECK: sqneg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vqneg1.i = tail call <2 x i64> @llvm.arm.neon.vqneg.v2i64(<2 x i64> %a) #4 + ret <2 x i64> %vqneg1.i +} + +define <8 x i8> @test_vneg_s8(<8 x i8> %a) #0 { +; CHECK: neg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %sub.i = sub <8 x i8> zeroinitializer, %a + ret <8 x i8> %sub.i +} + +define <16 x i8> @test_vnegq_s8(<16 x i8> %a) #0 { +; CHECK: neg v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %sub.i = sub <16 x i8> zeroinitializer, %a + ret <16 x i8> %sub.i +} + +define <4 x i16> @test_vneg_s16(<4 x i16> %a) #0 { +; CHECK: neg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h + %sub.i = sub <4 x i16> zeroinitializer, %a + ret <4 x i16> %sub.i +} + +define <8 x i16> @test_vnegq_s16(<8 x i16> %a) #0 { +; CHECK: neg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h + %sub.i = sub <8 x i16> zeroinitializer, %a + ret <8 x i16> %sub.i +} + +define <2 x i32> @test_vneg_s32(<2 x i32> %a) #0 { +; CHECK: neg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %sub.i = sub <2 x i32> zeroinitializer, %a + ret <2 x i32> %sub.i +} + +define <4 x i32> @test_vnegq_s32(<4 x i32> %a) #0 { +; CHECK: neg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %sub.i = sub <4 x i32> zeroinitializer, %a + ret <4 x i32> %sub.i +} + +define <2 x i64> @test_vnegq_s64(<2 x i64> %a) #0 { +; CHECK: neg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %sub.i = sub <2 x i64> zeroinitializer, %a + ret <2 x i64> %sub.i +} + +define <2 x float> @test_vneg_f32(<2 x float> %a) #0 { +; CHECK: fneg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %sub.i = fsub <2 x float> , %a + ret <2 x float> %sub.i +} + +define <4 x float> @test_vnegq_f32(<4 x float> %a) #0 { +; CHECK: fneg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %sub.i = fsub <4 x float> , %a + ret <4 x float> %sub.i +} + +define <2 x double> @test_vnegq_f64(<2 x double> %a) #0 { +; CHECK: fneg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %sub.i = fsub <2 x double> , %a + ret <2 x double> %sub.i +} + +define <8 x i8> @test_vabs_s8(<8 x i8> %a) #0 { +; CHECK: abs v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %vabs.i = tail call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %a) #4 + ret <8 x i8> %vabs.i +} + +define <16 x i8> @test_vabsq_s8(<16 x i8> %a) #0 { +; CHECK: abs v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %vabs.i = tail call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %a) #4 + ret <16 x i8> %vabs.i +} + +define <4 x i16> @test_vabs_s16(<4 x i16> %a) #0 { +; CHECK: abs v{{[0-9]+}}.4h, v{{[0-9]+}}.4h + %vabs1.i = tail call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %a) #4 + ret <4 x i16> %vabs1.i +} + +define <8 x i16> @test_vabsq_s16(<8 x i16> %a) #0 { +; CHECK: abs v{{[0-9]+}}.8h, v{{[0-9]+}}.8h + %vabs1.i = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %a) #4 + ret <8 x i16> %vabs1.i +} + +define <2 x i32> @test_vabs_s32(<2 x i32> %a) #0 { +; CHECK: abs v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vabs1.i = tail call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %a) #4 + ret <2 x i32> %vabs1.i +} + +define <4 x i32> @test_vabsq_s32(<4 x i32> %a) #0 { +; CHECK: abs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vabs1.i = tail call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %a) #4 + ret <4 x i32> %vabs1.i +} + +define <2 x i64> @test_vabsq_s64(<2 x i64> %a) #0 { +; CHECK: abs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vabs1.i = tail call <2 x i64> @llvm.arm.neon.vabs.v2i64(<2 x i64> %a) #4 + ret <2 x i64> %vabs1.i +} + +define <2 x float> @test_vabs_f32(<2 x float> %a) #1 { +; CHECK: fabs v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vabs1.i = tail call <2 x float> @llvm.fabs.v2f32(<2 x float> %a) #4 + ret <2 x float> %vabs1.i +} + +define <4 x float> @test_vabsq_f32(<4 x float> %a) #1 { +; CHECK: fabs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vabs1.i = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a) #4 + ret <4 x float> %vabs1.i +} + +define <2 x double> @test_vabsq_f64(<2 x double> %a) #1 { +; CHECK: fabs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vabs1.i = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %a) #4 + ret <2 x double> %vabs1.i +} + +define <8 x i8> @test_vuqadd_s8(<8 x i8> %a, <8 x i8> %b) #0 { +; CHECK: suqadd v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %vuqadd.i = tail call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> %a, <8 x i8> %b) #4 + ret <8 x i8> %vuqadd.i +} + +define <16 x i8> @test_vuqaddq_s8(<16 x i8> %a, <16 x i8> %b) #0 { +; CHECK: suqadd v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %vuqadd.i = tail call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8> %a, <16 x i8> %b) #4 + ret <16 x i8> %vuqadd.i +} + +define <4 x i16> @test_vuqadd_s16(<4 x i16> %a, <4 x i16> %b) #0 { +; CHECK: suqadd v{{[0-9]+}}.4h, v{{[0-9]+}}.4h + %vuqadd2.i = tail call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> %a, <4 x i16> %b) #4 + ret <4 x i16> %vuqadd2.i +} + +define <8 x i16> @test_vuqaddq_s16(<8 x i16> %a, <8 x i16> %b) #0 { +; CHECK: suqadd v{{[0-9]+}}.8h, v{{[0-9]+}}.8h + %vuqadd2.i = tail call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16> %a, <8 x i16> %b) #4 + ret <8 x i16> %vuqadd2.i +} + +define <2 x i32> @test_vuqadd_s32(<2 x i32> %a, <2 x i32> %b) #0 { +; CHECK: suqadd v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vuqadd2.i = tail call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32> %a, <2 x i32> %b) #4 + ret <2 x i32> %vuqadd2.i +} + +define <4 x i32> @test_vuqaddq_s32(<4 x i32> %a, <4 x i32> %b) #0 { +; CHECK: suqadd v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vuqadd2.i = tail call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32> %a, <4 x i32> %b) #4 + ret <4 x i32> %vuqadd2.i +} + +define <2 x i64> @test_vuqaddq_s64(<2 x i64> %a, <2 x i64> %b) #0 { +; CHECK: suqadd v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vuqadd2.i = tail call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64> %a, <2 x i64> %b) #4 + ret <2 x i64> %vuqadd2.i +} + +define <8 x i8> @test_vcls_s8(<8 x i8> %a) #0 { +; CHECK: cls v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %vcls.i = tail call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %a) #4 + ret <8 x i8> %vcls.i +} + +define <16 x i8> @test_vclsq_s8(<16 x i8> %a) #0 { +; CHECK: cls v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %vcls.i = tail call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %a) #4 + ret <16 x i8> %vcls.i +} + +define <4 x i16> @test_vcls_s16(<4 x i16> %a) #0 { +; CHECK: cls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h + %vcls1.i = tail call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %a) #4 + ret <4 x i16> %vcls1.i +} + +define <8 x i16> @test_vclsq_s16(<8 x i16> %a) #0 { +; CHECK: cls v{{[0-9]+}}.8h, v{{[0-9]+}}.8h + %vcls1.i = tail call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %a) #4 + ret <8 x i16> %vcls1.i +} + +define <2 x i32> @test_vcls_s32(<2 x i32> %a) #0 { +; CHECK: cls v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcls1.i = tail call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %a) #4 + ret <2 x i32> %vcls1.i +} + +define <4 x i32> @test_vclsq_s32(<4 x i32> %a) #0 { +; CHECK: cls v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcls1.i = tail call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %a) #4 + ret <4 x i32> %vcls1.i +} + +define <8 x i8> @test_vclz_s8(<8 x i8> %a) #0 { +; CHECK: clz v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) #4 + ret <8 x i8> %vclz.i +} + +define <16 x i8> @test_vclzq_s8(<16 x i8> %a) #0 { +; CHECK: clz v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) #4 + ret <16 x i8> %vclz.i +} + +define <4 x i16> @test_vclz_s16(<4 x i16> %a) #0 { +; CHECK: clz v{{[0-9]+}}.4h, v{{[0-9]+}}.4h + %vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) #4 + ret <4 x i16> %vclz1.i +} + +define <8 x i16> @test_vclzq_s16(<8 x i16> %a) #0 { +; CHECK: clz v{{[0-9]+}}.8h, v{{[0-9]+}}.8h + %vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) #4 + ret <8 x i16> %vclz1.i +} + +define <2 x i32> @test_vclz_s32(<2 x i32> %a) #0 { +; CHECK: clz v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) #4 + ret <2 x i32> %vclz1.i +} + +define <4 x i32> @test_vclzq_s32(<4 x i32> %a) #0 { +; CHECK: clz v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) #4 + ret <4 x i32> %vclz1.i +} + +define <8 x i8> @test_vcnt_s8(<8 x i8> %a) #0 { +; CHECK: cnt v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %vctpop.i = tail call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %a) #4 + ret <8 x i8> %vctpop.i +} + +define <16 x i8> @test_vcntq_s8(<16 x i8> %a) #0 { +; CHECK: cnt v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %vctpop.i = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a) #4 + ret <16 x i8> %vctpop.i +} + +define <8 x i8> @test_vmvn_s8(<8 x i8> %a) #0 { +; CHECK: not v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %neg.i = xor <8 x i8> %a, + ret <8 x i8> %neg.i +} + +define <16 x i8> @test_vmvnq_s8(<16 x i8> %a) #0 { +; CHECK: not v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %neg.i = xor <16 x i8> %a, + ret <16 x i8> %neg.i +} + +define <4 x i16> @test_vmvn_s16(<4 x i16> %a) #0 { +; CHECK: not v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %neg.i = xor <4 x i16> %a, + ret <4 x i16> %neg.i +} + +define <8 x i16> @test_vmvnq_s16(<8 x i16> %a) #0 { +; CHECK: not v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %neg.i = xor <8 x i16> %a, + ret <8 x i16> %neg.i +} + +define <2 x i32> @test_vmvn_s32(<2 x i32> %a) #0 { +; CHECK: not v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %neg.i = xor <2 x i32> %a, + ret <2 x i32> %neg.i +} + +define <4 x i32> @test_vmvnq_s32(<4 x i32> %a) #0 { +; CHECK: not v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %neg.i = xor <4 x i32> %a, + ret <4 x i32> %neg.i +} + +define <8 x i8> @test_vrbit_s8(<8 x i8> %a) #0 { +; CHECK: rbit v{{[0-9]+}}.8b, v{{[0-9]+}}.8b + %vrbit.i = tail call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %a) #4 + ret <8 x i8> %vrbit.i +} + +define <16 x i8> @test_vrbitq_s8(<16 x i8> %a) #0 { +; CHECK: rbit v{{[0-9]+}}.16b, v{{[0-9]+}}.16b + %vrbit.i = tail call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %a) #4 + ret <16 x i8> %vrbit.i +} + +define <8 x i8> @test_vmovn_s16(<8 x i16> %a) #0 { +; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h + %vmovn.i = trunc <8 x i16> %a to <8 x i8> + ret <8 x i8> %vmovn.i +} + +define <4 x i16> @test_vmovn_s32(<4 x i32> %a) #0 { +; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s + %vmovn.i = trunc <4 x i32> %a to <4 x i16> + ret <4 x i16> %vmovn.i +} + +define <2 x i32> @test_vmovn_s64(<2 x i64> %a) #0 { +; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d + %vmovn.i = trunc <2 x i64> %a to <2 x i32> + ret <2 x i32> %vmovn.i +} + +define <16 x i8> @test_vmovn_high_s16(<8 x i8> %a, <8 x i16> %b) #0 { +; CHECK: xtn2 v{{[0-9]+}}.16b, v{{[0-9]+}}.8h + %vmovn.i.i = trunc <8 x i16> %b to <8 x i8> + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %vmovn.i.i, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <8 x i16> @test_vmovn_high_s32(<4 x i16> %a, <4 x i32> %b) #0 { +; CHECK: xtn2 v{{[0-9]+}}.8h, v{{[0-9]+}}.4s + %vmovn.i.i = trunc <4 x i32> %b to <4 x i16> + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vmovn.i.i, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_vmovn_high_s64(<2 x i32> %a, <2 x i64> %b) #0 { +; CHECK: xtn2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d + %vmovn.i.i = trunc <2 x i64> %b to <2 x i32> + %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %vmovn.i.i, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_vqmovun_s16(<8 x i16> %a) #0 { +; CHECK: sqxtun v{{[0-9]+}}.8b, v{{[0-9]+}}.8h + %vqdmull1.i = tail call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %a) #4 + ret <8 x i8> %vqdmull1.i +} + +define <4 x i16> @test_vqmovun_s32(<4 x i32> %a) #0 { +; CHECK: sqxtun v{{[0-9]+}}.4h, v{{[0-9]+}}.4s + %vqdmull1.i = tail call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %a) #4 + ret <4 x i16> %vqdmull1.i +} + +define <2 x i32> @test_vqmovun_s64(<2 x i64> %a) #0 { +; CHECK: sqxtun v{{[0-9]+}}.2s, v{{[0-9]+}}.2d + %vqdmull1.i = tail call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %a) #4 + ret <2 x i32> %vqdmull1.i +} + +define <16 x i8> @test_vqmovun_high_s16(<8 x i8> %a, <8 x i16> %b) #0 { +; CHECK: sqxtun2 v{{[0-9]+}}.16b, v{{[0-9]+}}.8h + %vqdmull1.i.i = tail call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %b) #4 + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %vqdmull1.i.i, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <8 x i16> @test_vqmovun_high_s32(<4 x i16> %a, <4 x i32> %b) #0 { +; CHECK: sqxtun2 v{{[0-9]+}}.8h, v{{[0-9]+}}.4s + %vqdmull1.i.i = tail call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %b) #4 + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vqdmull1.i.i, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_vqmovun_high_s64(<2 x i32> %a, <2 x i64> %b) #0 { +; CHECK: sqxtun2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d + %vqdmull1.i.i = tail call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %b) #4 + %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %vqdmull1.i.i, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_vqmovn_s16(<8 x i16> %a) #0 { +; CHECK: sqxtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h + %vqmovn1.i = tail call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %a) #4 + ret <8 x i8> %vqmovn1.i +} + +define <4 x i16> @test_vqmovn_s32(<4 x i32> %a) #0 { +; CHECK: sqxtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s + %vqmovn1.i = tail call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %a) #4 + ret <4 x i16> %vqmovn1.i +} + +define <2 x i32> @test_vqmovn_s64(<2 x i64> %a) #0 { +; CHECK: sqxtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d + %vqmovn1.i = tail call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %a) #4 + ret <2 x i32> %vqmovn1.i +} + +define <16 x i8> @test_vqmovn_high_s16(<8 x i8> %a, <8 x i16> %b) #0 { +; CHECK: sqxtn2 v{{[0-9]+}}.16b, v{{[0-9]+}}.8h + %vqmovn1.i.i = tail call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %b) #4 + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %vqmovn1.i.i, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <8 x i16> @test_vqmovn_high_s32(<4 x i16> %a, <4 x i32> %b) #0 { +; CHECK: test_vqmovn_high_s32 + %vqmovn1.i.i = tail call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %b) #4 + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vqmovn1.i.i, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_vqmovn_high_s64(<2 x i32> %a, <2 x i64> %b) #0 { +; CHECK: test_vqmovn_high_s64 + %vqmovn1.i.i = tail call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %b) #4 + %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %vqmovn1.i.i, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_vqmovn_u16(<8 x i16> %a) #0 { +; CHECK: uqxtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h + %vqmovn1.i = tail call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %a) #4 + ret <8 x i8> %vqmovn1.i +} + +define <4 x i16> @test_vqmovn_u32(<4 x i32> %a) #0 { +; CHECK: uqxtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s + %vqmovn1.i = tail call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %a) #4 + ret <4 x i16> %vqmovn1.i +} + +define <2 x i32> @test_vqmovn_u64(<2 x i64> %a) #0 { +; CHECK: uqxtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d + %vqmovn1.i = tail call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %a) #4 + ret <2 x i32> %vqmovn1.i +} + +define <16 x i8> @test_vqmovn_high_u16(<8 x i8> %a, <8 x i16> %b) #0 { +; CHECK: uqxtn2 v{{[0-9]+}}.16b, v{{[0-9]+}}.8h + %vqmovn1.i.i = tail call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %b) #4 + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %vqmovn1.i.i, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <8 x i16> @test_vqmovn_high_u32(<4 x i16> %a, <4 x i32> %b) #0 { +; CHECK: uqxtn2 v{{[0-9]+}}.8h, v{{[0-9]+}}.4s + %vqmovn1.i.i = tail call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %b) #4 + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vqmovn1.i.i, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_vqmovn_high_u64(<2 x i32> %a, <2 x i64> %b) #0 { +; CHECK: uqxtn2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d + %vqmovn1.i.i = tail call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %b) #4 + %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %vqmovn1.i.i, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i16> @test_vshll_n_s8(<8 x i8> %a) #0 { +; CHECK: shll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #8 + %1 = sext <8 x i8> %a to <8 x i16> + %vshll_n = shl <8 x i16> %1, + ret <8 x i16> %vshll_n +} + +define <4 x i32> @test_vshll_n_s16(<4 x i16> %a) #0 { +; CHECK: shll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #16 + %1 = sext <4 x i16> %a to <4 x i32> + %vshll_n = shl <4 x i32> %1, + ret <4 x i32> %vshll_n +} + +define <2 x i64> @test_vshll_n_s32(<2 x i32> %a) #0 { +; CHECK: shll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #32 + %1 = sext <2 x i32> %a to <2 x i64> + %vshll_n = shl <2 x i64> %1, + ret <2 x i64> %vshll_n +} + +define <8 x i16> @test_vshll_n_u8(<8 x i8> %a) #0 { +; CHECK: shll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #8 + %1 = zext <8 x i8> %a to <8 x i16> + %vshll_n = shl <8 x i16> %1, + ret <8 x i16> %vshll_n +} + +define <4 x i32> @test_vshll_n_u16(<4 x i16> %a) #0 { +; CHECK: shll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #16 + %1 = zext <4 x i16> %a to <4 x i32> + %vshll_n = shl <4 x i32> %1, + ret <4 x i32> %vshll_n +} + +define <2 x i64> @test_vshll_n_u32(<2 x i32> %a) #0 { +; CHECK: shll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #32 + %1 = zext <2 x i32> %a to <2 x i64> + %vshll_n = shl <2 x i64> %1, + ret <2 x i64> %vshll_n +} + +define <8 x i16> @test_vshll_high_n_s8(<16 x i8> %a) #0 { +; CHECK: shll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #8 + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> + %1 = sext <8 x i8> %shuffle.i to <8 x i16> + %vshll_n = shl <8 x i16> %1, + ret <8 x i16> %vshll_n +} + +define <4 x i32> @test_vshll_high_n_s16(<8 x i16> %a) #0 { +; CHECK: shll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #16 + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> + %1 = sext <4 x i16> %shuffle.i to <4 x i32> + %vshll_n = shl <4 x i32> %1, + ret <4 x i32> %vshll_n +} + +define <2 x i64> @test_vshll_high_n_s32(<4 x i32> %a) #0 { +; CHECK: shll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #32 + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> + %1 = sext <2 x i32> %shuffle.i to <2 x i64> + %vshll_n = shl <2 x i64> %1, + ret <2 x i64> %vshll_n +} + +define <8 x i16> @test_vshll_high_n_u8(<16 x i8> %a) #0 { +; CHECK: shll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #8 + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> + %1 = zext <8 x i8> %shuffle.i to <8 x i16> + %vshll_n = shl <8 x i16> %1, + ret <8 x i16> %vshll_n +} + +define <4 x i32> @test_vshll_high_n_u16(<8 x i16> %a) #0 { +; CHECK: shll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #16 + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> + %1 = zext <4 x i16> %shuffle.i to <4 x i32> + %vshll_n = shl <4 x i32> %1, + ret <4 x i32> %vshll_n +} + +define <2 x i64> @test_vshll_high_n_u32(<4 x i32> %a) #0 { +; CHECK: shll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #32 + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> + %1 = zext <2 x i32> %shuffle.i to <2 x i64> + %vshll_n = shl <2 x i64> %1, + ret <2 x i64> %vshll_n +} + +define <4 x i16> @test_vcvt_f16_f32(<4 x float> %a) #0 { +; CHECK: fcvtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s + %vcvt1.i = tail call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %a) #4 + ret <4 x i16> %vcvt1.i +} + +define <8 x i16> @test_vcvt_high_f16_f32(<4 x i16> %a, <4 x float> %b) #0 { +; CHECK: fcvtn2 v{{[0-9]+}}.8h, v{{[0-9]+}}.4s + %vcvt1.i.i = tail call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %b) #4 + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vcvt1.i.i, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x float> @test_vcvt_f32_f16(<4 x i16> %a) #0 { +; CHECK: fcvtl v{{[0-9]+}}.4s, v{{[0-9]+}}.4h + %vcvt1.i = tail call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %a) #4 + ret <4 x float> %vcvt1.i +} + +define <4 x float> @test_vcvt_high_f32_f16(<8 x i16> %a) #0 { +; CHECK: fcvtl2 v{{[0-9]+}}.4s, v{{[0-9]+}}.8h + %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> + %vcvt1.i.i = tail call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %shuffle.i.i) #4 + ret <4 x float> %vcvt1.i.i +} + +define <2 x float> @test_vcvt_f32_f64(<2 x double> %a) #0 { +; CHECK: fcvtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d + %vcvt.i = fptrunc <2 x double> %a to <2 x float> + ret <2 x float> %vcvt.i +} + +define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %a, <2 x double> %b) #0 { +; CHECK: fcvtn2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d + %vcvt.i.i = fptrunc <2 x double> %b to <2 x float> + %shuffle.i = shufflevector <2 x float> %a, <2 x float> %vcvt.i.i, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <2 x float> @test_vcvtx_f32_f64(<2 x double> %a) #0 { +; CHECK: fcvtxn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d + %vcvtx_f32_f641.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %a) #4 + ret <2 x float> %vcvtx_f32_f641.i +} + +define <4 x float> @test_vcvtx_high_f32_f64(<2 x float> %a, <2 x double> %b) #0 { +; CHECK: fcvtxn2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d + %vcvtx_f32_f641.i.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %b) #4 + %shuffle.i = shufflevector <2 x float> %a, <2 x float> %vcvtx_f32_f641.i.i, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <2 x double> @test_vcvt_f64_f32(<2 x float> %a) #0 { +; CHECK: fcvtl v{{[0-9]+}}.2d, v{{[0-9]+}}.2s + %vcvt.i = fpext <2 x float> %a to <2 x double> + ret <2 x double> %vcvt.i +} + +define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %a) #0 { +; CHECK: fcvtl2 v{{[0-9]+}}.2d, v{{[0-9]+}}.4s + %shuffle.i.i = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> + %vcvt.i.i = fpext <2 x float> %shuffle.i.i to <2 x double> + ret <2 x double> %vcvt.i.i +} + +define <2 x float> @test_vrndn_f32(<2 x float> %a) #0 { +; CHECK: frintn v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrndn1.i = tail call <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float> %a) #4 + ret <2 x float> %vrndn1.i +} + +define <4 x float> @test_vrndnq_f32(<4 x float> %a) #0 { +; CHECK: frintn v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrndn1.i = tail call <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float> %a) #4 + ret <4 x float> %vrndn1.i +} + +define <2 x double> @test_vrndnq_f64(<2 x double> %a) #0 { +; CHECK: frintn v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vrndn1.i = tail call <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double> %a) #4 + ret <2 x double> %vrndn1.i +} + +define <2 x float> @test_vrnda_f32(<2 x float> %a) #0 { +; CHECK: frinta v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrnda1.i = tail call <2 x float> @llvm.round.v2f32(<2 x float> %a) #4 + ret <2 x float> %vrnda1.i +} + +define <4 x float> @test_vrndaq_f32(<4 x float> %a) #0 { +; CHECK: frinta v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrnda1.i = tail call <4 x float> @llvm.round.v4f32(<4 x float> %a) #4 + ret <4 x float> %vrnda1.i +} + +define <2 x double> @test_vrndaq_f64(<2 x double> %a) #0 { +; CHECK: frinta v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vrnda1.i = tail call <2 x double> @llvm.round.v2f64(<2 x double> %a) #4 + ret <2 x double> %vrnda1.i +} + +define <2 x float> @test_vrndp_f32(<2 x float> %a) #0 { +; CHECK: frintp v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrndp1.i = tail call <2 x float> @llvm.ceil.v2f32(<2 x float> %a) #4 + ret <2 x float> %vrndp1.i +} + +define <4 x float> @test_vrndpq_f32(<4 x float> %a) #0 { +; CHECK: frintp v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrndp1.i = tail call <4 x float> @llvm.ceil.v4f32(<4 x float> %a) #4 + ret <4 x float> %vrndp1.i +} + +define <2 x double> @test_vrndpq_f64(<2 x double> %a) #0 { +; CHECK: frintp v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vrndp1.i = tail call <2 x double> @llvm.ceil.v2f64(<2 x double> %a) #4 + ret <2 x double> %vrndp1.i +} + +define <2 x float> @test_vrndm_f32(<2 x float> %a) #0 { +; CHECK: frintm v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrndm1.i = tail call <2 x float> @llvm.floor.v2f32(<2 x float> %a) #4 + ret <2 x float> %vrndm1.i +} + +define <4 x float> @test_vrndmq_f32(<4 x float> %a) #0 { +; CHECK: frintm v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrndm1.i = tail call <4 x float> @llvm.floor.v4f32(<4 x float> %a) #4 + ret <4 x float> %vrndm1.i +} + +define <2 x double> @test_vrndmq_f64(<2 x double> %a) #0 { +; CHECK: frintm v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vrndm1.i = tail call <2 x double> @llvm.floor.v2f64(<2 x double> %a) #4 + ret <2 x double> %vrndm1.i +} + +define <2 x float> @test_vrndx_f32(<2 x float> %a) #0 { +; CHECK: frintx v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrndx1.i = tail call <2 x float> @llvm.rint.v2f32(<2 x float> %a) #4 + ret <2 x float> %vrndx1.i +} + +define <4 x float> @test_vrndxq_f32(<4 x float> %a) #0 { +; CHECK: frintx v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrndx1.i = tail call <4 x float> @llvm.rint.v4f32(<4 x float> %a) #4 + ret <4 x float> %vrndx1.i +} + +define <2 x double> @test_vrndxq_f64(<2 x double> %a) #0 { +; CHECK: frintx v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vrndx1.i = tail call <2 x double> @llvm.rint.v2f64(<2 x double> %a) #4 + ret <2 x double> %vrndx1.i +} + +define <2 x float> @test_vrnd_f32(<2 x float> %a) #0 { +; CHECK: frintz v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrnd1.i = tail call <2 x float> @llvm.trunc.v2f32(<2 x float> %a) #4 + ret <2 x float> %vrnd1.i +} + +define <4 x float> @test_vrndq_f32(<4 x float> %a) #0 { +; CHECK: frintz v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrnd1.i = tail call <4 x float> @llvm.trunc.v4f32(<4 x float> %a) #4 + ret <4 x float> %vrnd1.i +} + +define <2 x double> @test_vrndq_f64(<2 x double> %a) #0 { +; CHECK: frintz v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vrnd1.i = tail call <2 x double> @llvm.trunc.v2f64(<2 x double> %a) #4 + ret <2 x double> %vrnd1.i +} + +define <2 x float> @test_vrndi_f32(<2 x float> %a) #0 { +; CHECK: frinti v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrndi1.i = tail call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %a) #4 + ret <2 x float> %vrndi1.i +} + +define <4 x float> @test_vrndiq_f32(<4 x float> %a) #0 { +; CHECK: frinti v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrndi1.i = tail call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a) #4 + ret <4 x float> %vrndi1.i +} + +define <2 x double> @test_vrndiq_f64(<2 x double> %a) #0 { +; CHECK: frinti v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vrndi1.i = tail call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %a) #4 + ret <2 x double> %vrndi1.i +} + +define <2 x i32> @test_vcvt_s32_f32(<2 x float> %a) #0 { +; CHECK: fcvtzs v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvt.i = fptosi <2 x float> %a to <2 x i32> + ret <2 x i32> %vcvt.i +} + +define <4 x i32> @test_vcvtq_s32_f32(<4 x float> %a) #0 { +; CHECK: fcvtzs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvt.i = fptosi <4 x float> %a to <4 x i32> + ret <4 x i32> %vcvt.i +} + +define <2 x i64> @test_vcvtq_s64_f64(<2 x double> %a) #0 { +; CHECK: fcvtzs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvt.i = fptosi <2 x double> %a to <2 x i64> + ret <2 x i64> %vcvt.i +} + +define <2 x i32> @test_vcvt_u32_f32(<2 x float> %a) #0 { +; CHECK: fcvtzu v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvt.i = fptoui <2 x float> %a to <2 x i32> + ret <2 x i32> %vcvt.i +} + +define <4 x i32> @test_vcvtq_u32_f32(<4 x float> %a) #0 { +; CHECK: fcvtzu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvt.i = fptoui <4 x float> %a to <4 x i32> + ret <4 x i32> %vcvt.i +} + +define <2 x i64> @test_vcvtq_u64_f64(<2 x double> %a) #0 { +; CHECK: fcvtzu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvt.i = fptoui <2 x double> %a to <2 x i64> + ret <2 x i64> %vcvt.i +} + +define <2 x i32> @test_vcvtn_s32_f32(<2 x float> %a) #0 { +; CHECK: fcvtns v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvtns_f321.i = tail call <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float> %a) #4 + ret <2 x i32> %vcvtns_f321.i +} + +define <4 x i32> @test_vcvtnq_s32_f32(<4 x float> %a) #0 { +; CHECK: fcvtns v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvtns_f321.i = tail call <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float> %a) #4 + ret <4 x i32> %vcvtns_f321.i +} + +define <2 x i64> @test_vcvtnq_s64_f64(<2 x double> %a) #0 { +; CHECK: fcvtns v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvtns_f641.i = tail call <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double> %a) #4 + ret <2 x i64> %vcvtns_f641.i +} + +define <2 x i32> @test_vcvtn_u32_f32(<2 x float> %a) #0 { +; CHECK: fcvtnu v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvtnu_f321.i = tail call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %a) #4 + ret <2 x i32> %vcvtnu_f321.i +} + +define <4 x i32> @test_vcvtnq_u32_f32(<4 x float> %a) #0 { +; CHECK: fcvtnu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvtnu_f321.i = tail call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %a) #4 + ret <4 x i32> %vcvtnu_f321.i +} + +define <2 x i64> @test_vcvtnq_u64_f64(<2 x double> %a) #0 { +; CHECK: fcvtnu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvtnu_f641.i = tail call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %a) #4 + ret <2 x i64> %vcvtnu_f641.i +} + +define <2 x i32> @test_vcvtp_s32_f32(<2 x float> %a) #0 { +; CHECK: fcvtps v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvtps_f321.i = tail call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> %a) #4 + ret <2 x i32> %vcvtps_f321.i +} + +define <4 x i32> @test_vcvtpq_s32_f32(<4 x float> %a) #0 { +; CHECK: fcvtps v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvtps_f321.i = tail call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> %a) #4 + ret <4 x i32> %vcvtps_f321.i +} + +define <2 x i64> @test_vcvtpq_s64_f64(<2 x double> %a) #0 { +; CHECK: fcvtps v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvtps_f641.i = tail call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %a) #4 + ret <2 x i64> %vcvtps_f641.i +} + +define <2 x i32> @test_vcvtp_u32_f32(<2 x float> %a) #0 { +; CHECK: fcvtpu v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvtpu_f321.i = tail call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> %a) #4 + ret <2 x i32> %vcvtpu_f321.i +} + +define <4 x i32> @test_vcvtpq_u32_f32(<4 x float> %a) #0 { +; CHECK: fcvtpu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvtpu_f321.i = tail call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> %a) #4 + ret <4 x i32> %vcvtpu_f321.i +} + +define <2 x i64> @test_vcvtpq_u64_f64(<2 x double> %a) #0 { +; CHECK: fcvtpu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvtpu_f641.i = tail call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> %a) #4 + ret <2 x i64> %vcvtpu_f641.i +} + +define <2 x i32> @test_vcvtm_s32_f32(<2 x float> %a) #0 { +; CHECK: fcvtms v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvtms_f321.i = tail call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> %a) #4 + ret <2 x i32> %vcvtms_f321.i +} + +define <4 x i32> @test_vcvtmq_s32_f32(<4 x float> %a) #0 { +; CHECK: fcvtms v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvtms_f321.i = tail call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> %a) #4 + ret <4 x i32> %vcvtms_f321.i +} + +define <2 x i64> @test_vcvtmq_s64_f64(<2 x double> %a) #0 { +; CHECK: fcvtms v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvtms_f641.i = tail call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %a) #4 + ret <2 x i64> %vcvtms_f641.i +} + +define <2 x i32> @test_vcvtm_u32_f32(<2 x float> %a) #0 { +; CHECK: fcvtmu v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvtmu_f321.i = tail call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> %a) #4 + ret <2 x i32> %vcvtmu_f321.i +} + +define <4 x i32> @test_vcvtmq_u32_f32(<4 x float> %a) #0 { +; CHECK: fcvtmu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvtmu_f321.i = tail call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> %a) #4 + ret <4 x i32> %vcvtmu_f321.i +} + +define <2 x i64> @test_vcvtmq_u64_f64(<2 x double> %a) #0 { +; CHECK: fcvtmu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvtmu_f641.i = tail call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %a) #4 + ret <2 x i64> %vcvtmu_f641.i +} + +define <2 x i32> @test_vcvta_s32_f32(<2 x float> %a) #0 { +; CHECK: fcvtas v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvtas_f321.i = tail call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %a) #4 + ret <2 x i32> %vcvtas_f321.i +} + +define <4 x i32> @test_vcvtaq_s32_f32(<4 x float> %a) #0 { +; CHECK: fcvtas v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvtas_f321.i = tail call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> %a) #4 + ret <4 x i32> %vcvtas_f321.i +} + +define <2 x i64> @test_vcvtaq_s64_f64(<2 x double> %a) #0 { +; CHECK: fcvtas v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvtas_f641.i = tail call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %a) #4 + ret <2 x i64> %vcvtas_f641.i +} + +define <2 x i32> @test_vcvta_u32_f32(<2 x float> %a) #0 { +; CHECK: fcvtau v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvtau_f321.i = tail call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %a) #4 + ret <2 x i32> %vcvtau_f321.i +} + +define <4 x i32> @test_vcvtaq_u32_f32(<4 x float> %a) #0 { +; CHECK: fcvtau v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvtau_f321.i = tail call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %a) #4 + ret <4 x i32> %vcvtau_f321.i +} + +define <2 x i64> @test_vcvtaq_u64_f64(<2 x double> %a) #0 { +; CHECK: fcvtau v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvtau_f641.i = tail call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %a) #4 + ret <2 x i64> %vcvtau_f641.i +} + +define <2 x float> @test_vrsqrte_f32(<2 x float> %a) #0 { +; CHECK: frsqrte v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrsqrte1.i = tail call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %a) #4 + ret <2 x float> %vrsqrte1.i +} + +define <4 x float> @test_vrsqrteq_f32(<4 x float> %a) #0 { +; CHECK: frsqrte v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrsqrte1.i = tail call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %a) #4 + ret <4 x float> %vrsqrte1.i +} + +define <2 x double> @test_vrsqrteq_f64(<2 x double> %a) #0 { +; CHECK: frsqrte v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vrsqrte1.i = tail call <2 x double> @llvm.arm.neon.vrsqrte.v2f64(<2 x double> %a) #4 + ret <2 x double> %vrsqrte1.i +} + +define <2 x float> @test_vrecpe_f32(<2 x float> %a) #0 { +; CHECK: frecpe v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrecpe1.i = tail call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %a) #4 + ret <2 x float> %vrecpe1.i +} + +define <4 x float> @test_vrecpeq_f32(<4 x float> %a) #0 { +; CHECK: frecpe v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrecpe1.i = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %a) #4 + ret <4 x float> %vrecpe1.i +} + +define <2 x double> @test_vrecpeq_f64(<2 x double> %a) #0 { +; CHECK: frecpe v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vrecpe1.i = tail call <2 x double> @llvm.arm.neon.vrecpe.v2f64(<2 x double> %a) #4 + ret <2 x double> %vrecpe1.i +} + +define <2 x i32> @test_vrecpe_u32(<2 x i32> %a) #0 { +; CHECK: urecpe v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vrecpe1.i = tail call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %a) #4 + ret <2 x i32> %vrecpe1.i +} + +define <4 x i32> @test_vrecpeq_u32(<4 x i32> %a) #0 { +; CHECK: urecpe v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vrecpe1.i = tail call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %a) #4 + ret <4 x i32> %vrecpe1.i +} + +define <2 x float> @test_vsqrt_f32(<2 x float> %a) #0 { +; CHECK: fsqrt v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vsqrt1.i = tail call <2 x float> @llvm.aarch64.neon.fsqrt.v2f32(<2 x float> %a) #4 + ret <2 x float> %vsqrt1.i +} + +define <4 x float> @test_vsqrtq_f32(<4 x float> %a) #0 { +; CHECK: fsqrt v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vsqrt1.i = tail call <4 x float> @llvm.aarch64.neon.fsqrt.v4f32(<4 x float> %a) #4 + ret <4 x float> %vsqrt1.i +} + +define <2 x double> @test_vsqrtq_f64(<2 x double> %a) #0 { +; CHECK: fsqrt v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vsqrt1.i = tail call <2 x double> @llvm.aarch64.neon.fsqrt.v2f64(<2 x double> %a) #4 + ret <2 x double> %vsqrt1.i +} + +define <2 x float> @test_vcvt_f32_s32(<2 x i32> %a) #0 { +; CHECK: scvtf v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvt.i = sitofp <2 x i32> %a to <2 x float> + ret <2 x float> %vcvt.i +} + +define <2 x float> @test_vcvt_f32_u32(<2 x i32> %a) #0 { +; CHECK: ucvtf v{{[0-9]+}}.2s, v{{[0-9]+}}.2s + %vcvt.i = uitofp <2 x i32> %a to <2 x float> + ret <2 x float> %vcvt.i +} + +define <4 x float> @test_vcvtq_f32_s32(<4 x i32> %a) #0 { +; CHECK: scvtf v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvt.i = sitofp <4 x i32> %a to <4 x float> + ret <4 x float> %vcvt.i +} + +define <4 x float> @test_vcvtq_f32_u32(<4 x i32> %a) #0 { +; CHECK: ucvtf v{{[0-9]+}}.4s, v{{[0-9]+}}.4s + %vcvt.i = uitofp <4 x i32> %a to <4 x float> + ret <4 x float> %vcvt.i +} + +define <2 x double> @test_vcvtq_f64_s64(<2 x i64> %a) #0 { +; CHECK: scvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvt.i = sitofp <2 x i64> %a to <2 x double> + ret <2 x double> %vcvt.i +} + +define <2 x double> @test_vcvtq_f64_u64(<2 x i64> %a) #0 { +; CHECK: ucvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d + %vcvt.i = uitofp <2 x i64> %a to <2 x double> + ret <2 x double> %vcvt.i +} + +declare <2 x double> @llvm.aarch64.neon.fsqrt.v2f64(<2 x double>) #2 + +declare <4 x float> @llvm.aarch64.neon.fsqrt.v4f32(<4 x float>) #2 + +declare <2 x float> @llvm.aarch64.neon.fsqrt.v2f32(<2 x float>) #2 + +declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) #2 + +declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) #2 + +declare <2 x double> @llvm.arm.neon.vrecpe.v2f64(<2 x double>) #2 + +declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) #2 + +declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) #2 + +declare <2 x double> @llvm.arm.neon.vrsqrte.v2f64(<2 x double>) #2 + +declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) #2 + +declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) #2 + +declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) #2 + +declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) #2 + +declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) #2 + +declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) #2 + +declare <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float>) #2 + +declare <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float>) #2 + +declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) #2 + +declare <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float>) #2 + +declare <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float>) #2 + +declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) #2 + +declare <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float>) #2 + +declare <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float>) #2 + +declare <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double>) #2 + +declare <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float>) #2 + +declare <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float>) #2 + +declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) #2 + +declare <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float>) #2 + +declare <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float>) #2 + +declare <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double>) #2 + +declare <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float>) #2 + +declare <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float>) #2 + +declare <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double>) #2 + +declare <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float>) #2 + +declare <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float>) #2 + +declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) #3 + +declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #3 + +declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #3 + +declare <2 x double> @llvm.trunc.v2f64(<2 x double>) #3 + +declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #3 + +declare <2 x float> @llvm.trunc.v2f32(<2 x float>) #3 + +declare <2 x double> @llvm.rint.v2f64(<2 x double>) #3 + +declare <4 x float> @llvm.rint.v4f32(<4 x float>) #3 + +declare <2 x float> @llvm.rint.v2f32(<2 x float>) #3 + +declare <2 x double> @llvm.floor.v2f64(<2 x double>) #3 + +declare <4 x float> @llvm.floor.v4f32(<4 x float>) #3 + +declare <2 x float> @llvm.floor.v2f32(<2 x float>) #3 + +declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #3 + +declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #3 + +declare <2 x float> @llvm.ceil.v2f32(<2 x float>) #3 + +declare <2 x double> @llvm.round.v2f64(<2 x double>) #3 + +declare <4 x float> @llvm.round.v4f32(<4 x float>) #3 + +declare <2 x float> @llvm.round.v2f32(<2 x float>) #3 + +declare <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double>) #2 + +declare <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float>) #2 + +declare <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float>) #2 + +declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) #2 + +declare <2 x float> @llvm.aarch64.neon.fcvtn.v2f32.v2f64(<2 x double>) #2 + +declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) #2 + +declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) #2 + +declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) #2 + +declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) #2 + +declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) #2 + +declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) #2 + +declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) #2 + +declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) #2 + +declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) #2 + +declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) #2 + +declare <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8>) #2 + +declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) #2 + +declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) #2 + +declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) #2 + +declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) #2 + +declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) #2 + +declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) #2 + +declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) #2 + +declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) #2 + +declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) #2 + +declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) #2 + +declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) #2 + +declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) #2 + +declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) #2 + +declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) #2 + +declare <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64>, <2 x i64>) #2 + +declare <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32>, <4 x i32>) #2 + +declare <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32>, <2 x i32>) #2 + +declare <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16>, <8 x i16>) #2 + +declare <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16>, <4 x i16>) #2 + +declare <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8>, <16 x i8>) #2 + +declare <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8>, <8 x i8>) #2 + +declare <2 x double> @llvm.fabs.v2f64(<2 x double>) #3 + +declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #3 + +declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #3 + +declare <2 x i64> @llvm.arm.neon.vabs.v2i64(<2 x i64>) #2 + +declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) #2 + +declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) #2 + +declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) #2 + +declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) #2 + +declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) #2 + +declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) #2 + +declare <2 x i64> @llvm.arm.neon.vqneg.v2i64(<2 x i64>) #2 + +declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) #2 + +declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) #2 + +declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) #2 + +declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) #2 + +declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) #2 + +declare <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8>) #2 + +declare <2 x i64> @llvm.arm.neon.vqabs.v2i64(<2 x i64>) #2 + +declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) #2 + +declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) #2 + +declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) #2 + +declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) #2 + +declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) #2 + +declare <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8>) #2 + +declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) #2 + +declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) #2 + +declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) #2 + +declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) #2 + +declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) #2 + +declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) #2 + +declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) #2 + +declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) #2 + +declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) #2 + +declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) #2 + +declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) #2 + +declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) #2 + +declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) #2 + +declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) #2 + +declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) #2 + +declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) #2 + +declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) #2 + +declare <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8>) #2 + +declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) #2 + +declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) #2 + +declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) #2 + +declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) #2 + +declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) #2 + +declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) #2 + +declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) #2 + +declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) #2 + + diff --git a/test/MC/AArch64/neon-simd-misc.s b/test/MC/AArch64/neon-simd-misc.s new file mode 100644 index 0000000000..9e0f9c5b4d --- /dev/null +++ b/test/MC/AArch64/neon-simd-misc.s @@ -0,0 +1,646 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Element reverse +//------------------------------------------------------------------------------ + rev64 v0.16b, v31.16b + rev64 v2.8h, v4.8h + rev64 v6.4s, v8.4s + rev64 v1.8b, v9.8b + rev64 v13.4h, v21.4h + rev64 v4.2s, v0.2s + +// CHECK: rev64 v0.16b, v31.16b // encoding: [0xe0,0x0b,0x20,0x4e] +// CHECK: rev64 v2.8h, v4.8h // encoding: [0x82,0x08,0x60,0x4e] +// CHECK: rev64 v6.4s, v8.4s // encoding: [0x06,0x09,0xa0,0x4e] +// CHECK: rev64 v1.8b, v9.8b // encoding: [0x21,0x09,0x20,0x0e] +// CHECK: rev64 v13.4h, v21.4h // encoding: [0xad,0x0a,0x60,0x0e] +// CHECK: rev64 v4.2s, v0.2s // encoding: [0x04,0x08,0xa0,0x0e] + + rev32 v30.16b, v31.16b + rev32 v4.8h, v7.8h + rev32 v21.8b, v1.8b + rev32 v0.4h, v9.4h + +// CHECK: rev32 v30.16b, v31.16b // encoding: [0xfe,0x0b,0x20,0x6e] +// CHECK: rev32 v4.8h, v7.8h // encoding: [0xe4,0x08,0x60,0x6e] +// CHECK: rev32 v21.8b, v1.8b // encoding: [0x35,0x08,0x20,0x2e] +// CHECK: rev32 v0.4h, v9.4h // encoding: [0x20,0x09,0x60,0x2e] + + rev16 v30.16b, v31.16b + rev16 v21.8b, v1.8b + +// CHECK: rev16 v30.16b, v31.16b // encoding: [0xfe,0x1b,0x20,0x4e] +// CHECK: rev16 v21.8b, v1.8b // encoding: [0x35,0x18,0x20,0x0e] + +//------------------------------------------------------------------------------ +// Signed integer pairwise add long +//------------------------------------------------------------------------------ + + saddlp v3.8h, v21.16b + saddlp v8.4h, v5.8b + saddlp v9.4s, v1.8h + saddlp v0.2s, v1.4h + saddlp v12.2d, v4.4s + saddlp v17.1d, v28.2s + +// CHECK: saddlp v3.8h, v21.16b // encoding: [0xa3,0x2a,0x20,0x4e] +// CHECK: saddlp v8.4h, v5.8b // encoding: [0xa8,0x28,0x20,0x0e] +// CHECK: saddlp v9.4s, v1.8h // encoding: [0x29,0x28,0x60,0x4e] +// CHECK: saddlp v0.2s, v1.4h // encoding: [0x20,0x28,0x60,0x0e] +// CHECK: saddlp v12.2d, v4.4s // encoding: [0x8c,0x28,0xa0,0x4e] +// CHECK: saddlp v17.1d, v28.2s // encoding: [0x91,0x2b,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Unsigned integer pairwise add long +//------------------------------------------------------------------------------ + + uaddlp v3.8h, v21.16b + uaddlp v8.4h, v5.8b + uaddlp v9.4s, v1.8h + uaddlp v0.2s, v1.4h + uaddlp v12.2d, v4.4s + uaddlp v17.1d, v28.2s + +// CHECK: uaddlp v3.8h, v21.16b // encoding: [0xa3,0x2a,0x20,0x6e] +// CHECK: uaddlp v8.4h, v5.8b // encoding: [0xa8,0x28,0x20,0x2e] +// CHECK: uaddlp v9.4s, v1.8h // encoding: [0x29,0x28,0x60,0x6e] +// CHECK: uaddlp v0.2s, v1.4h // encoding: [0x20,0x28,0x60,0x2e] +// CHECK: uaddlp v12.2d, v4.4s // encoding: [0x8c,0x28,0xa0,0x6e] +// CHECK: uaddlp v17.1d, v28.2s // encoding: [0x91,0x2b,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Signed integer pairwise add and accumulate long +//------------------------------------------------------------------------------ + + sadalp v3.8h, v21.16b + sadalp v8.4h, v5.8b + sadalp v9.4s, v1.8h + sadalp v0.2s, v1.4h + sadalp v12.2d, v4.4s + sadalp v17.1d, v28.2s + +// CHECK: sadalp v3.8h, v21.16b // encoding: [0xa3,0x6a,0x20,0x4e] +// CHECK: sadalp v8.4h, v5.8b // encoding: [0xa8,0x68,0x20,0x0e] +// CHECK: sadalp v9.4s, v1.8h // encoding: [0x29,0x68,0x60,0x4e] +// CHECK: sadalp v0.2s, v1.4h // encoding: [0x20,0x68,0x60,0x0e] +// CHECK: sadalp v12.2d, v4.4s // encoding: [0x8c,0x68,0xa0,0x4e] +// CHECK: sadalp v17.1d, v28.2s // encoding: [0x91,0x6b,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Unsigned integer pairwise add and accumulate long +//------------------------------------------------------------------------------ + + uadalp v3.8h, v21.16b + uadalp v8.4h, v5.8b + uadalp v9.4s, v1.8h + uadalp v0.2s, v1.4h + uadalp v12.2d, v4.4s + uadalp v17.1d, v28.2s + +// CHECK: uadalp v3.8h, v21.16b // encoding: [0xa3,0x6a,0x20,0x6e] +// CHECK: uadalp v8.4h, v5.8b // encoding: [0xa8,0x68,0x20,0x2e] +// CHECK: uadalp v9.4s, v1.8h // encoding: [0x29,0x68,0x60,0x6e] +// CHECK: uadalp v0.2s, v1.4h // encoding: [0x20,0x68,0x60,0x2e] +// CHECK: uadalp v12.2d, v4.4s // encoding: [0x8c,0x68,0xa0,0x6e] +// CHECK: uadalp v17.1d, v28.2s // encoding: [0x91,0x6b,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Signed integer saturating accumulate of unsigned value +//------------------------------------------------------------------------------ + + suqadd v0.16b, v31.16b + suqadd v2.8h, v4.8h + suqadd v6.4s, v8.4s + suqadd v6.2d, v8.2d + suqadd v1.8b, v9.8b + suqadd v13.4h, v21.4h + suqadd v4.2s, v0.2s + +// CHECK: suqadd v0.16b, v31.16b // encoding: [0xe0,0x3b,0x20,0x4e] +// CHECK: suqadd v2.8h, v4.8h // encoding: [0x82,0x38,0x60,0x4e] +// CHECK: suqadd v6.4s, v8.4s // encoding: [0x06,0x39,0xa0,0x4e] +// CHECK: suqadd v6.2d, v8.2d // encoding: [0x06,0x39,0xe0,0x4e] +// CHECK: suqadd v1.8b, v9.8b // encoding: [0x21,0x39,0x20,0x0e] +// CHECK: suqadd v13.4h, v21.4h // encoding: [0xad,0x3a,0x60,0x0e] +// CHECK: suqadd v4.2s, v0.2s // encoding: [0x04,0x38,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Unsigned integer saturating accumulate of signed value +//------------------------------------------------------------------------------ + + usqadd v0.16b, v31.16b + usqadd v2.8h, v4.8h + usqadd v6.4s, v8.4s + usqadd v6.2d, v8.2d + usqadd v1.8b, v9.8b + usqadd v13.4h, v21.4h + usqadd v4.2s, v0.2s + +// CHECK: usqadd v0.16b, v31.16b // encoding: [0xe0,0x3b,0x20,0x6e] +// CHECK: usqadd v2.8h, v4.8h // encoding: [0x82,0x38,0x60,0x6e] +// CHECK: usqadd v6.4s, v8.4s // encoding: [0x06,0x39,0xa0,0x6e] +// CHECK: usqadd v6.2d, v8.2d // encoding: [0x06,0x39,0xe0,0x6e] +// CHECK: usqadd v1.8b, v9.8b // encoding: [0x21,0x39,0x20,0x2e] +// CHECK: usqadd v13.4h, v21.4h // encoding: [0xad,0x3a,0x60,0x2e] +// CHECK: usqadd v4.2s, v0.2s // encoding: [0x04,0x38,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Integer saturating absolute +//------------------------------------------------------------------------------ + + sqabs v0.16b, v31.16b + sqabs v2.8h, v4.8h + sqabs v6.4s, v8.4s + sqabs v6.2d, v8.2d + sqabs v1.8b, v9.8b + sqabs v13.4h, v21.4h + sqabs v4.2s, v0.2s + +// CHECK: sqabs v0.16b, v31.16b // encoding: [0xe0,0x7b,0x20,0x4e] +// CHECK: sqabs v2.8h, v4.8h // encoding: [0x82,0x78,0x60,0x4e] +// CHECK: sqabs v6.4s, v8.4s // encoding: [0x06,0x79,0xa0,0x4e] +// CHECK: sqabs v6.2d, v8.2d // encoding: [0x06,0x79,0xe0,0x4e] +// CHECK: sqabs v1.8b, v9.8b // encoding: [0x21,0x79,0x20,0x0e] +// CHECK: sqabs v13.4h, v21.4h // encoding: [0xad,0x7a,0x60,0x0e] +// CHECK: sqabs v4.2s, v0.2s // encoding: [0x04,0x78,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Signed integer saturating negate +//------------------------------------------------------------------------------ + + sqneg v0.16b, v31.16b + sqneg v2.8h, v4.8h + sqneg v6.4s, v8.4s + sqneg v6.2d, v8.2d + sqneg v1.8b, v9.8b + sqneg v13.4h, v21.4h + sqneg v4.2s, v0.2s + +// CHECK: sqneg v0.16b, v31.16b // encoding: [0xe0,0x7b,0x20,0x6e] +// CHECK: sqneg v2.8h, v4.8h // encoding: [0x82,0x78,0x60,0x6e] +// CHECK: sqneg v6.4s, v8.4s // encoding: [0x06,0x79,0xa0,0x6e] +// CHECK: sqneg v6.2d, v8.2d // encoding: [0x06,0x79,0xe0,0x6e] +// CHECK: sqneg v1.8b, v9.8b // encoding: [0x21,0x79,0x20,0x2e] +// CHECK: sqneg v13.4h, v21.4h // encoding: [0xad,0x7a,0x60,0x2e] +// CHECK: sqneg v4.2s, v0.2s // encoding: [0x04,0x78,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Integer absolute +//------------------------------------------------------------------------------ + + abs v0.16b, v31.16b + abs v2.8h, v4.8h + abs v6.4s, v8.4s + abs v6.2d, v8.2d + abs v1.8b, v9.8b + abs v13.4h, v21.4h + abs v4.2s, v0.2s + +// CHECK: abs v0.16b, v31.16b // encoding: [0xe0,0xbb,0x20,0x4e] +// CHECK: abs v2.8h, v4.8h // encoding: [0x82,0xb8,0x60,0x4e] +// CHECK: abs v6.4s, v8.4s // encoding: [0x06,0xb9,0xa0,0x4e] +// CHECK: abs v6.2d, v8.2d // encoding: [0x06,0xb9,0xe0,0x4e] +// CHECK: abs v1.8b, v9.8b // encoding: [0x21,0xb9,0x20,0x0e] +// CHECK: abs v13.4h, v21.4h // encoding: [0xad,0xba,0x60,0x0e] +// CHECK: abs v4.2s, v0.2s // encoding: [0x04,0xb8,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Integer negate +//------------------------------------------------------------------------------ + + neg v0.16b, v31.16b + neg v2.8h, v4.8h + neg v6.4s, v8.4s + neg v6.2d, v8.2d + neg v1.8b, v9.8b + neg v13.4h, v21.4h + neg v4.2s, v0.2s + +// CHECK: neg v0.16b, v31.16b // encoding: [0xe0,0xbb,0x20,0x6e] +// CHECK: neg v2.8h, v4.8h // encoding: [0x82,0xb8,0x60,0x6e] +// CHECK: neg v6.4s, v8.4s // encoding: [0x06,0xb9,0xa0,0x6e] +// CHECK: neg v6.2d, v8.2d // encoding: [0x06,0xb9,0xe0,0x6e] +// CHECK: neg v1.8b, v9.8b // encoding: [0x21,0xb9,0x20,0x2e] +// CHECK: neg v13.4h, v21.4h // encoding: [0xad,0xba,0x60,0x2e] +// CHECK: neg v4.2s, v0.2s // encoding: [0x04,0xb8,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Integer count leading sign bits +//------------------------------------------------------------------------------ + + cls v0.16b, v31.16b + cls v2.8h, v4.8h + cls v6.4s, v8.4s + cls v1.8b, v9.8b + cls v13.4h, v21.4h + cls v4.2s, v0.2s + +// CHECK: cls v0.16b, v31.16b // encoding: [0xe0,0x4b,0x20,0x4e] +// CHECK: cls v2.8h, v4.8h // encoding: [0x82,0x48,0x60,0x4e] +// CHECK: cls v6.4s, v8.4s // encoding: [0x06,0x49,0xa0,0x4e] +// CHECK: cls v1.8b, v9.8b // encoding: [0x21,0x49,0x20,0x0e] +// CHECK: cls v13.4h, v21.4h // encoding: [0xad,0x4a,0x60,0x0e] +// CHECK: cls v4.2s, v0.2s // encoding: [0x04,0x48,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Integer count leading zeros +//------------------------------------------------------------------------------ + + clz v0.16b, v31.16b + clz v2.8h, v4.8h + clz v6.4s, v8.4s + clz v1.8b, v9.8b + clz v13.4h, v21.4h + clz v4.2s, v0.2s + +// CHECK: clz v0.16b, v31.16b // encoding: [0xe0,0x4b,0x20,0x6e] +// CHECK: clz v2.8h, v4.8h // encoding: [0x82,0x48,0x60,0x6e] +// CHECK: clz v6.4s, v8.4s // encoding: [0x06,0x49,0xa0,0x6e] +// CHECK: clz v1.8b, v9.8b // encoding: [0x21,0x49,0x20,0x2e] +// CHECK: clz v13.4h, v21.4h // encoding: [0xad,0x4a,0x60,0x2e] +// CHECK: clz v4.2s, v0.2s // encoding: [0x04,0x48,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Population count +//------------------------------------------------------------------------------ + + cnt v0.16b, v31.16b + cnt v1.8b, v9.8b + +// CHECK: cnt v0.16b, v31.16b // encoding: [0xe0,0x5b,0x20,0x4e] +// CHECK: cnt v1.8b, v9.8b // encoding: [0x21,0x59,0x20,0x0e] + +//------------------------------------------------------------------------------ +// Bitwise NOT +//------------------------------------------------------------------------------ + + not v0.16b, v31.16b + not v1.8b, v9.8b + +// CHECK: not v0.16b, v31.16b // encoding: [0xe0,0x5b,0x20,0x6e] +// CHECK: not v1.8b, v9.8b // encoding: [0x21,0x59,0x20,0x2e] + +//------------------------------------------------------------------------------ +// Bitwise reverse +//------------------------------------------------------------------------------ + + rbit v0.16b, v31.16b + rbit v1.8b, v9.8b + +// CHECK: rbit v0.16b, v31.16b // encoding: [0xe0,0x5b,0x60,0x6e] +// CHECK: rbit v1.8b, v9.8b // encoding: [0x21,0x59,0x60,0x2e] + +//------------------------------------------------------------------------------ +// Floating-point absolute +//------------------------------------------------------------------------------ + + fabs v6.4s, v8.4s + fabs v6.2d, v8.2d + fabs v4.2s, v0.2s + +// CHECK: fabs v6.4s, v8.4s // encoding: [0x06,0xf9,0xa0,0x4e] +// CHECK: fabs v6.2d, v8.2d // encoding: [0x06,0xf9,0xe0,0x4e] +// CHECK: fabs v4.2s, v0.2s // encoding: [0x04,0xf8,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Floating-point negate +//------------------------------------------------------------------------------ + + fneg v6.4s, v8.4s + fneg v6.2d, v8.2d + fneg v4.2s, v0.2s + +// CHECK: fneg v6.4s, v8.4s // encoding: [0x06,0xf9,0xa0,0x6e] +// CHECK: fneg v6.2d, v8.2d // encoding: [0x06,0xf9,0xe0,0x6e] +// CHECK: fneg v4.2s, v0.2s // encoding: [0x04,0xf8,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Integer extract and narrow +//------------------------------------------------------------------------------ + + xtn2 v0.16b, v31.8h + xtn2 v2.8h, v4.4s + xtn2 v6.4s, v8.2d + xtn v1.8b, v9.8h + xtn v13.4h, v21.4s + xtn v4.2s, v0.2d + +// CHECK: xtn2 v0.16b, v31.8h // encoding: [0xe0,0x2b,0x21,0x4e] +// CHECK: xtn2 v2.8h, v4.4s // encoding: [0x82,0x28,0x61,0x4e] +// CHECK: xtn2 v6.4s, v8.2d // encoding: [0x06,0x29,0xa1,0x4e] +// CHECK: xtn v1.8b, v9.8h // encoding: [0x21,0x29,0x21,0x0e] +// CHECK: xtn v13.4h, v21.4s // encoding: [0xad,0x2a,0x61,0x0e] +// CHECK: xtn v4.2s, v0.2d // encoding: [0x04,0x28,0xa1,0x0e] + +//------------------------------------------------------------------------------ +// Signed integer saturating extract and unsigned narrow +//------------------------------------------------------------------------------ + + sqxtun2 v0.16b, v31.8h + sqxtun2 v2.8h, v4.4s + sqxtun2 v6.4s, v8.2d + sqxtun v1.8b, v9.8h + sqxtun v13.4h, v21.4s + sqxtun v4.2s, v0.2d + +// CHECK: sqxtun2 v0.16b, v31.8h // encoding: [0xe0,0x2b,0x21,0x6e] +// CHECK: sqxtun2 v2.8h, v4.4s // encoding: [0x82,0x28,0x61,0x6e] +// CHECK: sqxtun2 v6.4s, v8.2d // encoding: [0x06,0x29,0xa1,0x6e] +// CHECK: sqxtun v1.8b, v9.8h // encoding: [0x21,0x29,0x21,0x2e] +// CHECK: sqxtun v13.4h, v21.4s // encoding: [0xad,0x2a,0x61,0x2e] +// CHECK: sqxtun v4.2s, v0.2d // encoding: [0x04,0x28,0xa1,0x2e] + +//------------------------------------------------------------------------------ +// Signed integer saturating extract and narrow +//------------------------------------------------------------------------------ + + sqxtn2 v0.16b, v31.8h + sqxtn2 v2.8h, v4.4s + sqxtn2 v6.4s, v8.2d + sqxtn v1.8b, v9.8h + sqxtn v13.4h, v21.4s + sqxtn v4.2s, v0.2d + +// CHECK: sqxtn2 v0.16b, v31.8h // encoding: [0xe0,0x4b,0x21,0x4e] +// CHECK: sqxtn2 v2.8h, v4.4s // encoding: [0x82,0x48,0x61,0x4e] +// CHECK: sqxtn2 v6.4s, v8.2d // encoding: [0x06,0x49,0xa1,0x4e] +// CHECK: sqxtn v1.8b, v9.8h // encoding: [0x21,0x49,0x21,0x0e] +// CHECK: sqxtn v13.4h, v21.4s // encoding: [0xad,0x4a,0x61,0x0e] +// CHECK: sqxtn v4.2s, v0.2d // encoding: [0x04,0x48,0xa1,0x0e] + +//------------------------------------------------------------------------------ +// Unsigned integer saturating extract and narrow +//------------------------------------------------------------------------------ + + uqxtn2 v0.16b, v31.8h + uqxtn2 v2.8h, v4.4s + uqxtn2 v6.4s, v8.2d + uqxtn v1.8b, v9.8h + uqxtn v13.4h, v21.4s + uqxtn v4.2s, v0.2d + +// CHECK: uqxtn2 v0.16b, v31.8h // encoding: [0xe0,0x4b,0x21,0x6e] +// CHECK: uqxtn2 v2.8h, v4.4s // encoding: [0x82,0x48,0x61,0x6e] +// CHECK: uqxtn2 v6.4s, v8.2d // encoding: [0x06,0x49,0xa1,0x6e] +// CHECK: uqxtn v1.8b, v9.8h // encoding: [0x21,0x49,0x21,0x2e] +// CHECK: uqxtn v13.4h, v21.4s // encoding: [0xad,0x4a,0x61,0x2e] +// CHECK: uqxtn v4.2s, v0.2d // encoding: [0x04,0x48,0xa1,0x2e] + +//------------------------------------------------------------------------------ +// Integer shift left long +//------------------------------------------------------------------------------ + + shll2 v2.8h, v4.16b, #8 + shll2 v6.4s, v8.8h, #16 + shll2 v6.2d, v8.4s, #32 + shll v2.8h, v4.8b, #8 + shll v6.4s, v8.4h, #16 + shll v6.2d, v8.2s, #32 + +// CHECK: shll2 v2.8h, v4.16b, #8 // encoding: [0x82,0x38,0x21,0x6e] +// CHECK: shll2 v6.4s, v8.8h, #16 // encoding: [0x06,0x39,0x61,0x6e] +// CHECK: shll2 v6.2d, v8.4s, #32 // encoding: [0x06,0x39,0xa1,0x6e] +// CHECK: shll v2.8h, v4.8b, #8 // encoding: [0x82,0x38,0x21,0x2e] +// CHECK: shll v6.4s, v8.4h, #16 // encoding: [0x06,0x39,0x61,0x2e] +// CHECK: shll v6.2d, v8.2s, #32 // encoding: [0x06,0x39,0xa1,0x2e] + +//------------------------------------------------------------------------------ +// Floating-point convert downsize +//------------------------------------------------------------------------------ + + fcvtn2 v2.8h, v4.4s + fcvtn2 v6.4s, v8.2d + fcvtn v13.4h, v21.4s + fcvtn v4.2s, v0.2d + +// CHECK: fcvtn2 v2.8h, v4.4s // encoding: [0x82,0x68,0x21,0x4e] +// CHECK: fcvtn2 v6.4s, v8.2d // encoding: [0x06,0x69,0x61,0x4e] +// CHECK: fcvtn v13.4h, v21.4s // encoding: [0xad,0x6a,0x21,0x0e] +// CHECK: fcvtn v4.2s, v0.2d // encoding: [0x04,0x68,0x61,0x0e] + +//------------------------------------------------------------------------------ +// Floating-point convert downsize with inexact +//------------------------------------------------------------------------------ + + fcvtxn2 v6.4s, v8.2d + fcvtxn v4.2s, v0.2d + +// CHECK: fcvtxn2 v6.4s, v8.2d // encoding: [0x06,0x69,0x61,0x6e] +// CHECK: fcvtxn v4.2s, v0.2d // encoding: [0x04,0x68,0x61,0x2e] + +//------------------------------------------------------------------------------ +// Floating-point convert upsize +//------------------------------------------------------------------------------ + + fcvtl v9.4s, v1.4h + fcvtl v0.2d, v1.2s + fcvtl2 v12.4s, v4.8h + fcvtl2 v17.2d, v28.4s + +// CHECK: fcvtl v9.4s, v1.4h // encoding: [0x29,0x78,0x21,0x0e] +// CHECK: fcvtl v0.2d, v1.2s // encoding: [0x20,0x78,0x61,0x0e] +// CHECK: fcvtl2 v12.4s, v4.8h // encoding: [0x8c,0x78,0x21,0x4e] +// CHECK: fcvtl2 v17.2d, v28.4s // encoding: [0x91,0x7b,0x61,0x4e] + +//------------------------------------------------------------------------------ +// Floating-point round to integral +//------------------------------------------------------------------------------ + + frintn v6.4s, v8.4s + frintn v6.2d, v8.2d + frintn v4.2s, v0.2s + +// CHECK: frintn v6.4s, v8.4s // encoding: [0x06,0x89,0x21,0x4e] +// CHECK: frintn v6.2d, v8.2d // encoding: [0x06,0x89,0x61,0x4e] +// CHECK: frintn v4.2s, v0.2s // encoding: [0x04,0x88,0x21,0x0e] + + frinta v6.4s, v8.4s + frinta v6.2d, v8.2d + frinta v4.2s, v0.2s + +// CHECK: frinta v6.4s, v8.4s // encoding: [0x06,0x89,0x21,0x6e] +// CHECK: frinta v6.2d, v8.2d // encoding: [0x06,0x89,0x61,0x6e] +// CHECK: frinta v4.2s, v0.2s // encoding: [0x04,0x88,0x21,0x2e] + + frintp v6.4s, v8.4s + frintp v6.2d, v8.2d + frintp v4.2s, v0.2s + +// CHECK: frintp v6.4s, v8.4s // encoding: [0x06,0x89,0xa1,0x4e] +// CHECK: frintp v6.2d, v8.2d // encoding: [0x06,0x89,0xe1,0x4e] +// CHECK: frintp v4.2s, v0.2s // encoding: [0x04,0x88,0xa1,0x0e] + + frintm v6.4s, v8.4s + frintm v6.2d, v8.2d + frintm v4.2s, v0.2s + +// CHECK: frintm v6.4s, v8.4s // encoding: [0x06,0x99,0x21,0x4e] +// CHECK: frintm v6.2d, v8.2d // encoding: [0x06,0x99,0x61,0x4e] +// CHECK: frintm v4.2s, v0.2s // encoding: [0x04,0x98,0x21,0x0e] + + frintx v6.4s, v8.4s + frintx v6.2d, v8.2d + frintx v4.2s, v0.2s + +// CHECK: frintx v6.4s, v8.4s // encoding: [0x06,0x99,0x21,0x6e] +// CHECK: frintx v6.2d, v8.2d // encoding: [0x06,0x99,0x61,0x6e] +// CHECK: frintx v4.2s, v0.2s // encoding: [0x04,0x98,0x21,0x2e] + + frintz v6.4s, v8.4s + frintz v6.2d, v8.2d + frintz v4.2s, v0.2s + +// CHECK: frintz v6.4s, v8.4s // encoding: [0x06,0x99,0xa1,0x4e] +// CHECK: frintz v6.2d, v8.2d // encoding: [0x06,0x99,0xe1,0x4e] +// CHECK: frintz v4.2s, v0.2s // encoding: [0x04,0x98,0xa1,0x0e] + + frinti v6.4s, v8.4s + frinti v6.2d, v8.2d + frinti v4.2s, v0.2s + +// CHECK: frinti v6.4s, v8.4s // encoding: [0x06,0x99,0xa1,0x6e] +// CHECK: frinti v6.2d, v8.2d // encoding: [0x06,0x99,0xe1,0x6e] +// CHECK: frinti v4.2s, v0.2s // encoding: [0x04,0x98,0xa1,0x2e] + +//------------------------------------------------------------------------------ +// Floating-point convert to integer +//------------------------------------------------------------------------------ + + fcvtns v6.4s, v8.4s + fcvtns v6.2d, v8.2d + fcvtns v4.2s, v0.2s + +// CHECK: fcvtns v6.4s, v8.4s // encoding: [0x06,0xa9,0x21,0x4e] +// CHECK: fcvtns v6.2d, v8.2d // encoding: [0x06,0xa9,0x61,0x4e] +// CHECK: fcvtns v4.2s, v0.2s // encoding: [0x04,0xa8,0x21,0x0e] + + fcvtnu v6.4s, v8.4s + fcvtnu v6.2d, v8.2d + fcvtnu v4.2s, v0.2s + +// CHECK: fcvtnu v6.4s, v8.4s // encoding: [0x06,0xa9,0x21,0x6e] +// CHECK: fcvtnu v6.2d, v8.2d // encoding: [0x06,0xa9,0x61,0x6e] +// CHECK: fcvtnu v4.2s, v0.2s // encoding: [0x04,0xa8,0x21,0x2e] + + fcvtps v6.4s, v8.4s + fcvtps v6.2d, v8.2d + fcvtps v4.2s, v0.2s + +// CHECK: fcvtps v6.4s, v8.4s // encoding: [0x06,0xa9,0xa1,0x4e] +// CHECK: fcvtps v6.2d, v8.2d // encoding: [0x06,0xa9,0xe1,0x4e] +// CHECK: fcvtps v4.2s, v0.2s // encoding: [0x04,0xa8,0xa1,0x0e] + + fcvtpu v6.4s, v8.4s + fcvtpu v6.2d, v8.2d + fcvtpu v4.2s, v0.2s + +// CHECK: fcvtpu v6.4s, v8.4s // encoding: [0x06,0xa9,0xa1,0x6e] +// CHECK: fcvtpu v6.2d, v8.2d // encoding: [0x06,0xa9,0xe1,0x6e] +// CHECK: fcvtpu v4.2s, v0.2s // encoding: [0x04,0xa8,0xa1,0x2e] + + fcvtms v6.4s, v8.4s + fcvtms v6.2d, v8.2d + fcvtms v4.2s, v0.2s + +// CHECK: fcvtms v6.4s, v8.4s // encoding: [0x06,0xb9,0x21,0x4e] +// CHECK: fcvtms v6.2d, v8.2d // encoding: [0x06,0xb9,0x61,0x4e] +// CHECK: fcvtms v4.2s, v0.2s // encoding: [0x04,0xb8,0x21,0x0e] + + fcvtmu v6.4s, v8.4s + fcvtmu v6.2d, v8.2d + fcvtmu v4.2s, v0.2s + +// CHECK: fcvtmu v6.4s, v8.4s // encoding: [0x06,0xb9,0x21,0x6e] +// CHECK: fcvtmu v6.2d, v8.2d // encoding: [0x06,0xb9,0x61,0x6e] +// CHECK: fcvtmu v4.2s, v0.2s // encoding: [0x04,0xb8,0x21,0x2e] + + fcvtzs v6.4s, v8.4s + fcvtzs v6.2d, v8.2d + fcvtzs v4.2s, v0.2s + +// CHECK: fcvtzs v6.4s, v8.4s // encoding: [0x06,0xb9,0xa1,0x4e] +// CHECK: fcvtzs v6.2d, v8.2d // encoding: [0x06,0xb9,0xe1,0x4e] +// CHECK: fcvtzs v4.2s, v0.2s // encoding: [0x04,0xb8,0xa1,0x0e] + + + fcvtzu v6.4s, v8.4s + fcvtzu v6.2d, v8.2d + fcvtzu v4.2s, v0.2s + +// CHECK: fcvtzu v6.4s, v8.4s // encoding: [0x06,0xb9,0xa1,0x6e] +// CHECK: fcvtzu v6.2d, v8.2d // encoding: [0x06,0xb9,0xe1,0x6e] +// CHECK: fcvtzu v4.2s, v0.2s // encoding: [0x04,0xb8,0xa1,0x2e] + + fcvtas v6.4s, v8.4s + fcvtas v6.2d, v8.2d + fcvtas v4.2s, v0.2s + +// CHECK: fcvtas v6.4s, v8.4s // encoding: [0x06,0xc9,0x21,0x4e] +// CHECK: fcvtas v6.2d, v8.2d // encoding: [0x06,0xc9,0x61,0x4e] +// CHECK: fcvtas v4.2s, v0.2s // encoding: [0x04,0xc8,0x21,0x0e] + + fcvtau v6.4s, v8.4s + fcvtau v6.2d, v8.2d + fcvtau v4.2s, v0.2s + +// CHECK: fcvtau v6.4s, v8.4s // encoding: [0x06,0xc9,0x21,0x6e] +// CHECK: fcvtau v6.2d, v8.2d // encoding: [0x06,0xc9,0x61,0x6e] +// CHECK: fcvtau v4.2s, v0.2s // encoding: [0x04,0xc8,0x21,0x2e] + + urecpe v6.4s, v8.4s + urecpe v4.2s, v0.2s + +// CHECK: urecpe v6.4s, v8.4s // encoding: [0x06,0xc9,0xa1,0x4e] +// CHECK: urecpe v4.2s, v0.2s // encoding: [0x04,0xc8,0xa1,0x0e] + + ursqrte v6.4s, v8.4s + ursqrte v4.2s, v0.2s + +// CHECK: ursqrte v6.4s, v8.4s // encoding: [0x06,0xc9,0xa1,0x6e] +// CHECK: ursqrte v4.2s, v0.2s // encoding: [0x04,0xc8,0xa1,0x2e] + + scvtf v6.4s, v8.4s + scvtf v6.2d, v8.2d + scvtf v4.2s, v0.2s + +// CHECK: scvtf v6.4s, v8.4s // encoding: [0x06,0xd9,0x21,0x4e] +// CHECK: scvtf v6.2d, v8.2d // encoding: [0x06,0xd9,0x61,0x4e] +// CHECK: scvtf v4.2s, v0.2s // encoding: [0x04,0xd8,0x21,0x0e] + + ucvtf v6.4s, v8.4s + ucvtf v6.2d, v8.2d + ucvtf v4.2s, v0.2s + +// CHECK: ucvtf v6.4s, v8.4s // encoding: [0x06,0xd9,0x21,0x6e] +// CHECK: ucvtf v6.2d, v8.2d // encoding: [0x06,0xd9,0x61,0x6e] +// CHECK: ucvtf v4.2s, v0.2s // encoding: [0x04,0xd8,0x21,0x2e] + + frecpe v6.4s, v8.4s + frecpe v6.2d, v8.2d + frecpe v4.2s, v0.2s + +// CHECK: frecpe v6.4s, v8.4s // encoding: [0x06,0xd9,0xa1,0x4e] +// CHECK: frecpe v6.2d, v8.2d // encoding: [0x06,0xd9,0xe1,0x4e] +// CHECK: frecpe v4.2s, v0.2s // encoding: [0x04,0xd8,0xa1,0x0e] + + frsqrte v6.4s, v8.4s + frsqrte v6.2d, v8.2d + frsqrte v4.2s, v0.2s + +// CHECK: frsqrte v6.4s, v8.4s // encoding: [0x06,0xd9,0xa1,0x6e] +// CHECK: frsqrte v6.2d, v8.2d // encoding: [0x06,0xd9,0xe1,0x6e] +// CHECK: frsqrte v4.2s, v0.2s // encoding: [0x04,0xd8,0xa1,0x2e] + + fsqrt v6.4s, v8.4s + fsqrt v6.2d, v8.2d + fsqrt v4.2s, v0.2s + +// CHECK: fsqrt v6.4s, v8.4s // encoding: [0x06,0xf9,0xa1,0x6e] +// CHECK: fsqrt v6.2d, v8.2d // encoding: [0x06,0xf9,0xe1,0x6e] +// CHECK: fsqrt v4.2s, v0.2s // encoding: [0x04,0xf8,0xa1,0x2e] + + -- cgit v1.2.3