From 284c931330404e61d548fc1eedf44d5dd1b87507 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Tue, 4 Feb 2014 10:38:46 +0000 Subject: ARM: fix fast-isel assertion failure Missing braces on if meant we inserted both ARM and Thumb load for a litpool entry. This didn't end well. rdar://problem/15959157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200752 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMFastISel.cpp | 3 ++- test/CodeGen/ARM/fastisel-thumb-litpool.ll | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/ARM/fastisel-thumb-litpool.ll diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 32b6929166..68fcee7d24 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -653,13 +653,14 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRpci), DestReg) .addConstantPoolIndex(Idx)); - else + else { // The extra immediate is for addrmode2. DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp), DestReg) .addConstantPoolIndex(Idx) .addImm(0)); + } return DestReg; } diff --git a/test/CodeGen/ARM/fastisel-thumb-litpool.ll b/test/CodeGen/ARM/fastisel-thumb-litpool.ll new file mode 100644 index 0000000000..aa9e7260fb --- /dev/null +++ b/test/CodeGen/ARM/fastisel-thumb-litpool.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=thumbv7-apple-ios -O0 -o - %s | FileCheck %s + +; We used to accidentally create both an ARM and a Thumb ldr here. It led to an +; assertion failure at the time, but could go all the way through to emission, +; hence the CHECK-NOT. + +define i32 @test_thumb_ldrlit() minsize { +; CHECK: ldr r0, LCPI0_0 +; CHECK-NOT: ldr + ret i32 12345678 +} -- cgit v1.2.3