From 3d5694dca9ba2b05a4be6202509567b4a3426295 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Thu, 17 Oct 2013 12:41:05 +0000 Subject: Fix tests not to depend on specific regalloc or instruction order. They were failing with -mcpu=atom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192890 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/widen_conv-2.ll | 4 ++-- test/CodeGen/X86/x86-64-tls-1.ll | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/test/CodeGen/X86/widen_conv-2.ll b/test/CodeGen/X86/widen_conv-2.ll index 27a36df51f..906f7cdafb 100644 --- a/test/CodeGen/X86/widen_conv-2.ll +++ b/test/CodeGen/X86/widen_conv-2.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s -; CHECK: cwtl -; CHECK: cwtl +; CHECK: {{cwtl|movswl}} +; CHECK: {{cwtl|movswl}} ; sign extension v2i32 to v2i16 diff --git a/test/CodeGen/X86/x86-64-tls-1.ll b/test/CodeGen/X86/x86-64-tls-1.ll index b172e9d51b..641786f5a9 100644 --- a/test/CodeGen/X86/x86-64-tls-1.ll +++ b/test/CodeGen/X86/x86-64-tls-1.ll @@ -3,8 +3,8 @@ define i64 @z() nounwind { ; FIXME: The codegen here is primitive at best and could be much better. ; The add and the moves can be folded together. -; CHECK: movq $tm_nest_level@TPOFF, %rcx -; CHECK: movq %fs:0, %rax +; CHECK-DAG: movq $tm_nest_level@TPOFF, %rcx +; CHECK-DAG: movq %fs:0, %rax ; CHECK: addl %ecx, %eax ret i64 and (i64 ptrtoint (i32* @tm_nest_level to i64), i64 100) } -- cgit v1.2.3