From 5c8b8e61df9744ec1efbf6760abbcb62058541a8 Mon Sep 17 00:00:00 2001 From: Kevin Qin Date: Mon, 13 Jan 2014 01:56:29 +0000 Subject: [AArch64 NEON] Add more scenarios to use perm instructions when lowering shuffle_vector This patch covered 2 more scenarios: 1. Two operands of shuffle_vector are the same, like %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> 2. One of operands is undef, like %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> After this patch, perm instructions will have chance to be emitted instead of lots of INS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199069 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64ISelLowering.cpp | 47 +- test/CodeGen/AArch64/neon-perm.ll | 1441 ++++++++++++++++++++++++++++ 2 files changed, 1478 insertions(+), 10 deletions(-) diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 0d9c516660..ce9ce3aeb5 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4242,7 +4242,7 @@ static bool isREVMask(ArrayRef M, EVT VT, unsigned BlockSize) { // isPermuteMask - Check whether the vector shuffle matches to UZP, ZIP and // TRN instruction. -static unsigned isPermuteMask(ArrayRef M, EVT VT) { +static unsigned isPermuteMask(ArrayRef M, EVT VT, bool isV2undef) { unsigned NumElts = VT.getVectorNumElements(); if (NumElts < 4) return 0; @@ -4251,7 +4251,10 @@ static unsigned isPermuteMask(ArrayRef M, EVT VT) { // Check UZP1 for (unsigned i = 0; i < NumElts; ++i) { - if ((unsigned)M[i] != i * 2) { + unsigned answer = i * 2; + if (isV2undef && answer >= NumElts) + answer -= NumElts; + if (M[i] != -1 && (unsigned)M[i] != answer) { ismatch = false; break; } @@ -4262,7 +4265,10 @@ static unsigned isPermuteMask(ArrayRef M, EVT VT) { // Check UZP2 ismatch = true; for (unsigned i = 0; i < NumElts; ++i) { - if ((unsigned)M[i] != i * 2 + 1) { + unsigned answer = i * 2 + 1; + if (isV2undef && answer >= NumElts) + answer -= NumElts; + if (M[i] != -1 && (unsigned)M[i] != answer) { ismatch = false; break; } @@ -4273,7 +4279,10 @@ static unsigned isPermuteMask(ArrayRef M, EVT VT) { // Check ZIP1 ismatch = true; for (unsigned i = 0; i < NumElts; ++i) { - if ((unsigned)M[i] != i / 2 + NumElts * (i % 2)) { + unsigned answer = i / 2 + NumElts * (i % 2); + if (isV2undef && answer >= NumElts) + answer -= NumElts; + if (M[i] != -1 && (unsigned)M[i] != answer) { ismatch = false; break; } @@ -4284,7 +4293,10 @@ static unsigned isPermuteMask(ArrayRef M, EVT VT) { // Check ZIP2 ismatch = true; for (unsigned i = 0; i < NumElts; ++i) { - if ((unsigned)M[i] != (NumElts + i) / 2 + NumElts * (i % 2)) { + unsigned answer = (NumElts + i) / 2 + NumElts * (i % 2); + if (isV2undef && answer >= NumElts) + answer -= NumElts; + if (M[i] != -1 && (unsigned)M[i] != answer) { ismatch = false; break; } @@ -4295,7 +4307,10 @@ static unsigned isPermuteMask(ArrayRef M, EVT VT) { // Check TRN1 ismatch = true; for (unsigned i = 0; i < NumElts; ++i) { - if ((unsigned)M[i] != i + (NumElts - 1) * (i % 2)) { + unsigned answer = i + (NumElts - 1) * (i % 2); + if (isV2undef && answer >= NumElts) + answer -= NumElts; + if (M[i] != -1 && (unsigned)M[i] != answer) { ismatch = false; break; } @@ -4306,7 +4321,10 @@ static unsigned isPermuteMask(ArrayRef M, EVT VT) { // Check TRN2 ismatch = true; for (unsigned i = 0; i < NumElts; ++i) { - if ((unsigned)M[i] != 1 + i + (NumElts - 1) * (i % 2)) { + unsigned answer = 1 + i + (NumElts - 1) * (i % 2); + if (isV2undef && answer >= NumElts) + answer -= NumElts; + if (M[i] != -1 && (unsigned)M[i] != answer) { ismatch = false; break; } @@ -4343,9 +4361,18 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, if (isREVMask(ShuffleMask, VT, 16)) return DAG.getNode(AArch64ISD::NEON_REV16, dl, VT, V1); - unsigned ISDNo = isPermuteMask(ShuffleMask, VT); - if (ISDNo) - return DAG.getNode(ISDNo, dl, VT, V1, V2); + unsigned ISDNo; + if (V2.getOpcode() == ISD::UNDEF) + ISDNo = isPermuteMask(ShuffleMask, VT, true); + else + ISDNo = isPermuteMask(ShuffleMask, VT, false); + + if (ISDNo) { + if (V2.getOpcode() == ISD::UNDEF) + return DAG.getNode(ISDNo, dl, VT, V1, V1); + else + return DAG.getNode(ISDNo, dl, VT, V1, V2); + } // If the element of shuffle mask are all the same constant, we can // transform it into either NEON_VDUP or NEON_VDUPLANE diff --git a/test/CodeGen/AArch64/neon-perm.ll b/test/CodeGen/AArch64/neon-perm.ll index fa4d54dc74..a0b17e161a 100644 --- a/test/CodeGen/AArch64/neon-perm.ll +++ b/test/CodeGen/AArch64/neon-perm.ll @@ -1030,6 +1030,1447 @@ entry: ret <8 x i16> %shuffle.i } +define <8 x i8> @test_same_vuzp1_s8(<8 x i8> %a) { +; CHECK: test_same_vuzp1_s8: +; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vuzp1q_s8(<16 x i8> %a) { +; CHECK: test_same_vuzp1q_s8: +; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vuzp1_s16(<4 x i16> %a) { +; CHECK: test_same_vuzp1_s16: +; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vuzp1q_s16(<8 x i16> %a) { +; CHECK: test_same_vuzp1q_s16: +; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vuzp1q_s32(<4 x i32> %a) { +; CHECK: test_same_vuzp1q_s32: +; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_same_vuzp1_u8(<8 x i8> %a) { +; CHECK: test_same_vuzp1_u8: +; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vuzp1q_u8(<16 x i8> %a) { +; CHECK: test_same_vuzp1q_u8: +; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vuzp1_u16(<4 x i16> %a) { +; CHECK: test_same_vuzp1_u16: +; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vuzp1q_u16(<8 x i16> %a) { +; CHECK: test_same_vuzp1q_u16: +; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vuzp1q_u32(<4 x i32> %a) { +; CHECK: test_same_vuzp1q_u32: +; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_same_vuzp1q_f32(<4 x float> %a) { +; CHECK: test_same_vuzp1q_f32: +; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_same_vuzp1_p8(<8 x i8> %a) { +; CHECK: test_same_vuzp1_p8: +; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vuzp1q_p8(<16 x i8> %a) { +; CHECK: test_same_vuzp1q_p8: +; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vuzp1_p16(<4 x i16> %a) { +; CHECK: test_same_vuzp1_p16: +; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vuzp1q_p16(<8 x i16> %a) { +; CHECK: test_same_vuzp1q_p16: +; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_same_vuzp2_s8(<8 x i8> %a) { +; CHECK: test_same_vuzp2_s8: +; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vuzp2q_s8(<16 x i8> %a) { +; CHECK: test_same_vuzp2q_s8: +; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vuzp2_s16(<4 x i16> %a) { +; CHECK: test_same_vuzp2_s16: +; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vuzp2q_s16(<8 x i16> %a) { +; CHECK: test_same_vuzp2q_s16: +; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vuzp2q_s32(<4 x i32> %a) { +; CHECK: test_same_vuzp2q_s32: +; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_same_vuzp2_u8(<8 x i8> %a) { +; CHECK: test_same_vuzp2_u8: +; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vuzp2q_u8(<16 x i8> %a) { +; CHECK: test_same_vuzp2q_u8: +; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vuzp2_u16(<4 x i16> %a) { +; CHECK: test_same_vuzp2_u16: +; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vuzp2q_u16(<8 x i16> %a) { +; CHECK: test_same_vuzp2q_u16: +; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vuzp2q_u32(<4 x i32> %a) { +; CHECK: test_same_vuzp2q_u32: +; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_same_vuzp2q_f32(<4 x float> %a) { +; CHECK: test_same_vuzp2q_f32: +; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_same_vuzp2_p8(<8 x i8> %a) { +; CHECK: test_same_vuzp2_p8: +; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vuzp2q_p8(<16 x i8> %a) { +; CHECK: test_same_vuzp2q_p8: +; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vuzp2_p16(<4 x i16> %a) { +; CHECK: test_same_vuzp2_p16: +; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vuzp2q_p16(<8 x i16> %a) { +; CHECK: test_same_vuzp2q_p16: +; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_same_vzip1_s8(<8 x i8> %a) { +; CHECK: test_same_vzip1_s8: +; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vzip1q_s8(<16 x i8> %a) { +; CHECK: test_same_vzip1q_s8: +; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vzip1_s16(<4 x i16> %a) { +; CHECK: test_same_vzip1_s16: +; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vzip1q_s16(<8 x i16> %a) { +; CHECK: test_same_vzip1q_s16: +; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vzip1q_s32(<4 x i32> %a) { +; CHECK: test_same_vzip1q_s32: +; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_same_vzip1_u8(<8 x i8> %a) { +; CHECK: test_same_vzip1_u8: +; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vzip1q_u8(<16 x i8> %a) { +; CHECK: test_same_vzip1q_u8: +; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vzip1_u16(<4 x i16> %a) { +; CHECK: test_same_vzip1_u16: +; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vzip1q_u16(<8 x i16> %a) { +; CHECK: test_same_vzip1q_u16: +; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vzip1q_u32(<4 x i32> %a) { +; CHECK: test_same_vzip1q_u32: +; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_same_vzip1q_f32(<4 x float> %a) { +; CHECK: test_same_vzip1q_f32: +; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_same_vzip1_p8(<8 x i8> %a) { +; CHECK: test_same_vzip1_p8: +; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vzip1q_p8(<16 x i8> %a) { +; CHECK: test_same_vzip1q_p8: +; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vzip1_p16(<4 x i16> %a) { +; CHECK: test_same_vzip1_p16: +; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vzip1q_p16(<8 x i16> %a) { +; CHECK: test_same_vzip1q_p16: +; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_same_vzip2_s8(<8 x i8> %a) { +; CHECK: test_same_vzip2_s8: +; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vzip2q_s8(<16 x i8> %a) { +; CHECK: test_same_vzip2q_s8: +; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vzip2_s16(<4 x i16> %a) { +; CHECK: test_same_vzip2_s16: +; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vzip2q_s16(<8 x i16> %a) { +; CHECK: test_same_vzip2q_s16: +; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vzip2q_s32(<4 x i32> %a) { +; CHECK: test_same_vzip2q_s32: +; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_same_vzip2_u8(<8 x i8> %a) { +; CHECK: test_same_vzip2_u8: +; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vzip2q_u8(<16 x i8> %a) { +; CHECK: test_same_vzip2q_u8: +; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vzip2_u16(<4 x i16> %a) { +; CHECK: test_same_vzip2_u16: +; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vzip2q_u16(<8 x i16> %a) { +; CHECK: test_same_vzip2q_u16: +; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vzip2q_u32(<4 x i32> %a) { +; CHECK: test_same_vzip2q_u32: +; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_same_vzip2q_f32(<4 x float> %a) { +; CHECK: test_same_vzip2q_f32: +; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_same_vzip2_p8(<8 x i8> %a) { +; CHECK: test_same_vzip2_p8: +; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vzip2q_p8(<16 x i8> %a) { +; CHECK: test_same_vzip2q_p8: +; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vzip2_p16(<4 x i16> %a) { +; CHECK: test_same_vzip2_p16: +; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vzip2q_p16(<8 x i16> %a) { +; CHECK: test_same_vzip2q_p16: +; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_same_vtrn1_s8(<8 x i8> %a) { +; CHECK: test_same_vtrn1_s8: +; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vtrn1q_s8(<16 x i8> %a) { +; CHECK: test_same_vtrn1q_s8: +; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vtrn1_s16(<4 x i16> %a) { +; CHECK: test_same_vtrn1_s16: +; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vtrn1q_s16(<8 x i16> %a) { +; CHECK: test_same_vtrn1q_s16: +; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vtrn1q_s32(<4 x i32> %a) { +; CHECK: test_same_vtrn1q_s32: +; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_same_vtrn1_u8(<8 x i8> %a) { +; CHECK: test_same_vtrn1_u8: +; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vtrn1q_u8(<16 x i8> %a) { +; CHECK: test_same_vtrn1q_u8: +; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vtrn1_u16(<4 x i16> %a) { +; CHECK: test_same_vtrn1_u16: +; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vtrn1q_u16(<8 x i16> %a) { +; CHECK: test_same_vtrn1q_u16: +; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vtrn1q_u32(<4 x i32> %a) { +; CHECK: test_same_vtrn1q_u32: +; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_same_vtrn1q_f32(<4 x float> %a) { +; CHECK: test_same_vtrn1q_f32: +; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_same_vtrn1_p8(<8 x i8> %a) { +; CHECK: test_same_vtrn1_p8: +; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vtrn1q_p8(<16 x i8> %a) { +; CHECK: test_same_vtrn1q_p8: +; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vtrn1_p16(<4 x i16> %a) { +; CHECK: test_same_vtrn1_p16: +; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vtrn1q_p16(<8 x i16> %a) { +; CHECK: test_same_vtrn1q_p16: +; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_same_vtrn2_s8(<8 x i8> %a) { +; CHECK: test_same_vtrn2_s8: +; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vtrn2q_s8(<16 x i8> %a) { +; CHECK: test_same_vtrn2q_s8: +; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vtrn2_s16(<4 x i16> %a) { +; CHECK: test_same_vtrn2_s16: +; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vtrn2q_s16(<8 x i16> %a) { +; CHECK: test_same_vtrn2q_s16: +; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vtrn2q_s32(<4 x i32> %a) { +; CHECK: test_same_vtrn2q_s32: +; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_same_vtrn2_u8(<8 x i8> %a) { +; CHECK: test_same_vtrn2_u8: +; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vtrn2q_u8(<16 x i8> %a) { +; CHECK: test_same_vtrn2q_u8: +; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vtrn2_u16(<4 x i16> %a) { +; CHECK: test_same_vtrn2_u16: +; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vtrn2q_u16(<8 x i16> %a) { +; CHECK: test_same_vtrn2q_u16: +; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_same_vtrn2q_u32(<4 x i32> %a) { +; CHECK: test_same_vtrn2q_u32: +; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_same_vtrn2q_f32(<4 x float> %a) { +; CHECK: test_same_vtrn2q_f32: +; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_same_vtrn2_p8(<8 x i8> %a) { +; CHECK: test_same_vtrn2_p8: +; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_same_vtrn2q_p8(<16 x i8> %a) { +; CHECK: test_same_vtrn2q_p8: +; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_same_vtrn2_p16(<4 x i16> %a) { +; CHECK: test_same_vtrn2_p16: +; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_same_vtrn2q_p16(<8 x i16> %a) { +; CHECK: test_same_vtrn2q_p16: +; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> + ret <8 x i16> %shuffle.i +} + + +define <8 x i8> @test_undef_vuzp1_s8(<8 x i8> %a) { +; CHECK: test_undef_vuzp1_s8: +; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vuzp1q_s8(<16 x i8> %a) { +; CHECK: test_undef_vuzp1q_s8: +; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vuzp1_s16(<4 x i16> %a) { +; CHECK: test_undef_vuzp1_s16: +; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vuzp1q_s16(<8 x i16> %a) { +; CHECK: test_undef_vuzp1q_s16: +; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vuzp1q_s32(<4 x i32> %a) { +; CHECK: test_undef_vuzp1q_s32: +; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_undef_vuzp1_u8(<8 x i8> %a) { +; CHECK: test_undef_vuzp1_u8: +; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vuzp1q_u8(<16 x i8> %a) { +; CHECK: test_undef_vuzp1q_u8: +; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vuzp1_u16(<4 x i16> %a) { +; CHECK: test_undef_vuzp1_u16: +; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vuzp1q_u16(<8 x i16> %a) { +; CHECK: test_undef_vuzp1q_u16: +; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vuzp1q_u32(<4 x i32> %a) { +; CHECK: test_undef_vuzp1q_u32: +; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_undef_vuzp1q_f32(<4 x float> %a) { +; CHECK: test_undef_vuzp1q_f32: +; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_undef_vuzp1_p8(<8 x i8> %a) { +; CHECK: test_undef_vuzp1_p8: +; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vuzp1q_p8(<16 x i8> %a) { +; CHECK: test_undef_vuzp1q_p8: +; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vuzp1_p16(<4 x i16> %a) { +; CHECK: test_undef_vuzp1_p16: +; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vuzp1q_p16(<8 x i16> %a) { +; CHECK: test_undef_vuzp1q_p16: +; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_undef_vuzp2_s8(<8 x i8> %a) { +; CHECK: test_undef_vuzp2_s8: +; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vuzp2q_s8(<16 x i8> %a) { +; CHECK: test_undef_vuzp2q_s8: +; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vuzp2_s16(<4 x i16> %a) { +; CHECK: test_undef_vuzp2_s16: +; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vuzp2q_s16(<8 x i16> %a) { +; CHECK: test_undef_vuzp2q_s16: +; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vuzp2q_s32(<4 x i32> %a) { +; CHECK: test_undef_vuzp2q_s32: +; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_undef_vuzp2_u8(<8 x i8> %a) { +; CHECK: test_undef_vuzp2_u8: +; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vuzp2q_u8(<16 x i8> %a) { +; CHECK: test_undef_vuzp2q_u8: +; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vuzp2_u16(<4 x i16> %a) { +; CHECK: test_undef_vuzp2_u16: +; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vuzp2q_u16(<8 x i16> %a) { +; CHECK: test_undef_vuzp2q_u16: +; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vuzp2q_u32(<4 x i32> %a) { +; CHECK: test_undef_vuzp2q_u32: +; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_undef_vuzp2q_f32(<4 x float> %a) { +; CHECK: test_undef_vuzp2q_f32: +; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_undef_vuzp2_p8(<8 x i8> %a) { +; CHECK: test_undef_vuzp2_p8: +; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vuzp2q_p8(<16 x i8> %a) { +; CHECK: test_undef_vuzp2q_p8: +; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vuzp2_p16(<4 x i16> %a) { +; CHECK: test_undef_vuzp2_p16: +; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vuzp2q_p16(<8 x i16> %a) { +; CHECK: test_undef_vuzp2q_p16: +; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_undef_vzip1_s8(<8 x i8> %a) { +; CHECK: test_undef_vzip1_s8: +; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vzip1q_s8(<16 x i8> %a) { +; CHECK: test_undef_vzip1q_s8: +; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vzip1_s16(<4 x i16> %a) { +; CHECK: test_undef_vzip1_s16: +; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vzip1q_s16(<8 x i16> %a) { +; CHECK: test_undef_vzip1q_s16: +; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vzip1q_s32(<4 x i32> %a) { +; CHECK: test_undef_vzip1q_s32: +; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_undef_vzip1_u8(<8 x i8> %a) { +; CHECK: test_undef_vzip1_u8: +; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vzip1q_u8(<16 x i8> %a) { +; CHECK: test_undef_vzip1q_u8: +; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vzip1_u16(<4 x i16> %a) { +; CHECK: test_undef_vzip1_u16: +; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vzip1q_u16(<8 x i16> %a) { +; CHECK: test_undef_vzip1q_u16: +; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vzip1q_u32(<4 x i32> %a) { +; CHECK: test_undef_vzip1q_u32: +; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_undef_vzip1q_f32(<4 x float> %a) { +; CHECK: test_undef_vzip1q_f32: +; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_undef_vzip1_p8(<8 x i8> %a) { +; CHECK: test_undef_vzip1_p8: +; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vzip1q_p8(<16 x i8> %a) { +; CHECK: test_undef_vzip1q_p8: +; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vzip1_p16(<4 x i16> %a) { +; CHECK: test_undef_vzip1_p16: +; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vzip1q_p16(<8 x i16> %a) { +; CHECK: test_undef_vzip1q_p16: +; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_undef_vzip2_s8(<8 x i8> %a) { +; CHECK: test_undef_vzip2_s8: +; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vzip2q_s8(<16 x i8> %a) { +; CHECK: test_undef_vzip2q_s8: +; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vzip2_s16(<4 x i16> %a) { +; CHECK: test_undef_vzip2_s16: +; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vzip2q_s16(<8 x i16> %a) { +; CHECK: test_undef_vzip2q_s16: +; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vzip2q_s32(<4 x i32> %a) { +; CHECK: test_undef_vzip2q_s32: +; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_undef_vzip2_u8(<8 x i8> %a) { +; CHECK: test_undef_vzip2_u8: +; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vzip2q_u8(<16 x i8> %a) { +; CHECK: test_undef_vzip2q_u8: +; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vzip2_u16(<4 x i16> %a) { +; CHECK: test_undef_vzip2_u16: +; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vzip2q_u16(<8 x i16> %a) { +; CHECK: test_undef_vzip2q_u16: +; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vzip2q_u32(<4 x i32> %a) { +; CHECK: test_undef_vzip2q_u32: +; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_undef_vzip2q_f32(<4 x float> %a) { +; CHECK: test_undef_vzip2q_f32: +; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_undef_vzip2_p8(<8 x i8> %a) { +; CHECK: test_undef_vzip2_p8: +; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vzip2q_p8(<16 x i8> %a) { +; CHECK: test_undef_vzip2q_p8: +; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vzip2_p16(<4 x i16> %a) { +; CHECK: test_undef_vzip2_p16: +; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vzip2q_p16(<8 x i16> %a) { +; CHECK: test_undef_vzip2q_p16: +; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_undef_vtrn1_s8(<8 x i8> %a) { +; CHECK: test_undef_vtrn1_s8: +; CHECK: ret +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vtrn1q_s8(<16 x i8> %a) { +; CHECK: test_undef_vtrn1q_s8: +; CHECK: ret +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vtrn1_s16(<4 x i16> %a) { +; CHECK: test_undef_vtrn1_s16: +; CHECK: ret +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vtrn1q_s16(<8 x i16> %a) { +; CHECK: test_undef_vtrn1q_s16: +; CHECK: ret +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vtrn1q_s32(<4 x i32> %a) { +; CHECK: test_undef_vtrn1q_s32: +; CHECK: ret +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_undef_vtrn1_u8(<8 x i8> %a) { +; CHECK: test_undef_vtrn1_u8: +; CHECK: ret +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vtrn1q_u8(<16 x i8> %a) { +; CHECK: test_undef_vtrn1q_u8: +; CHECK: ret +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vtrn1_u16(<4 x i16> %a) { +; CHECK: test_undef_vtrn1_u16: +; CHECK: ret +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vtrn1q_u16(<8 x i16> %a) { +; CHECK: test_undef_vtrn1q_u16: +; CHECK: ret +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vtrn1q_u32(<4 x i32> %a) { +; CHECK: test_undef_vtrn1q_u32: +; CHECK: ret +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_undef_vtrn1q_f32(<4 x float> %a) { +; CHECK: test_undef_vtrn1q_f32: +; CHECK: ret +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_undef_vtrn1_p8(<8 x i8> %a) { +; CHECK: test_undef_vtrn1_p8: +; CHECK: ret +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vtrn1q_p8(<16 x i8> %a) { +; CHECK: test_undef_vtrn1q_p8: +; CHECK: ret +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vtrn1_p16(<4 x i16> %a) { +; CHECK: test_undef_vtrn1_p16: +; CHECK: ret +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vtrn1q_p16(<8 x i16> %a) { +; CHECK: test_undef_vtrn1q_p16: +; CHECK: ret +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <8 x i8> @test_undef_vtrn2_s8(<8 x i8> %a) { +; CHECK: test_undef_vtrn2_s8: +; CHECK: rev16 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vtrn2q_s8(<16 x i8> %a) { +; CHECK: test_undef_vtrn2q_s8: +; CHECK: rev16 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vtrn2_s16(<4 x i16> %a) { +; CHECK: test_undef_vtrn2_s16: +; CHECK: rev32 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vtrn2q_s16(<8 x i16> %a) { +; CHECK: test_undef_vtrn2q_s16: +; CHECK: rev32 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vtrn2q_s32(<4 x i32> %a) { +; CHECK: test_undef_vtrn2q_s32: +; CHECK: rev64 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <8 x i8> @test_undef_vtrn2_u8(<8 x i8> %a) { +; CHECK: test_undef_vtrn2_u8: +; CHECK: rev16 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vtrn2q_u8(<16 x i8> %a) { +; CHECK: test_undef_vtrn2q_u8: +; CHECK: rev16 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vtrn2_u16(<4 x i16> %a) { +; CHECK: test_undef_vtrn2_u16: +; CHECK: rev32 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vtrn2q_u16(<8 x i16> %a) { +; CHECK: test_undef_vtrn2q_u16: +; CHECK: rev32 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + +define <4 x i32> @test_undef_vtrn2q_u32(<4 x i32> %a) { +; CHECK: test_undef_vtrn2q_u32: +; CHECK: rev64 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> + ret <4 x i32> %shuffle.i +} + +define <4 x float> @test_undef_vtrn2q_f32(<4 x float> %a) { +; CHECK: test_undef_vtrn2q_f32: +; CHECK: rev64 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> + ret <4 x float> %shuffle.i +} + +define <8 x i8> @test_undef_vtrn2_p8(<8 x i8> %a) { +; CHECK: test_undef_vtrn2_p8: +; CHECK: rev16 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +entry: + %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> + ret <8 x i8> %shuffle.i +} + +define <16 x i8> @test_undef_vtrn2q_p8(<16 x i8> %a) { +; CHECK: test_undef_vtrn2q_p8: +; CHECK: rev16 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> + ret <16 x i8> %shuffle.i +} + +define <4 x i16> @test_undef_vtrn2_p16(<4 x i16> %a) { +; CHECK: test_undef_vtrn2_p16: +; CHECK: rev32 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +entry: + %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> + ret <4 x i16> %shuffle.i +} + +define <8 x i16> @test_undef_vtrn2q_p16(<8 x i16> %a) { +; CHECK: test_undef_vtrn2q_p16: +; CHECK: rev32 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +entry: + %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> + ret <8 x i16> %shuffle.i +} + define %struct.int8x8x2_t @test_vuzp_s8(<8 x i8> %a, <8 x i8> %b) { ; CHECK: test_vuzp_s8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -- cgit v1.2.3