From 66e19c3e9db6e2727be21074a52f5c9fa187050f Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Wed, 16 May 2012 22:19:56 +0000 Subject: This patch adds the register class for MIPS16 as well as the ability for llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156958 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips.td | 4 ++++ lib/Target/Mips/MipsInstrInfo.cpp | 20 ++++++++++---------- lib/Target/Mips/MipsRegisterInfo.td | 7 +++++++ lib/Target/Mips/MipsSubtarget.cpp | 2 +- lib/Target/Mips/MipsSubtarget.h | 4 ++++ 5 files changed, 26 insertions(+), 11 deletions(-) diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index cbebe84a18..8548ae0b8b 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -72,6 +72,9 @@ def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", "Mips64r2", "Mips64r2 ISA Support", [FeatureMips64, FeatureMips32r2]>; +def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", + "Mips16 mode">; + //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// @@ -83,6 +86,7 @@ def : Proc<"mips32", [FeatureMips32]>; def : Proc<"mips32r2", [FeatureMips32r2]>; def : Proc<"mips64", [FeatureMips64]>; def : Proc<"mips64r2", [FeatureMips64r2]>; +def : Proc<"mips16", [FeatureMips16]>; def MipsAsmWriter : AsmWriter { string AsmWriterClassName = "InstPrinter"; diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 7578b17492..f5e2d3024e 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -189,15 +189,15 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opc = 0; - if (RC == &Mips::CPURegsRegClass) + if (Mips::CPURegsRegClass.hasSubClassEq(RC)) Opc = IsN64 ? Mips::SW_P8 : Mips::SW; - else if (RC == &Mips::CPU64RegsRegClass) + else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC)) Opc = IsN64 ? Mips::SD_P8 : Mips::SD; - else if (RC == &Mips::FGR32RegClass) + else if (Mips::FGR32RegClass.hasSubClassEq(RC)) Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1; - else if (RC == &Mips::AFGR64RegClass) + else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) Opc = Mips::SDC1; - else if (RC == &Mips::FGR64RegClass) + else if (Mips::FGR64RegClass.hasSubClassEq(RC)) Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164; assert(Opc && "Register class not handled!"); @@ -216,15 +216,15 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); unsigned Opc = 0; - if (RC == &Mips::CPURegsRegClass) + if (Mips::CPURegsRegClass.hasSubClassEq(RC)) Opc = IsN64 ? Mips::LW_P8 : Mips::LW; - else if (RC == &Mips::CPU64RegsRegClass) + else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC)) Opc = IsN64 ? Mips::LD_P8 : Mips::LD; - else if (RC == &Mips::FGR32RegClass) + else if (Mips::FGR32RegClass.hasSubClassEq(RC)) Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1; - else if (RC == &Mips::AFGR64RegClass) + else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) Opc = Mips::LDC1; - else if (RC == &Mips::FGR64RegClass) + else if (Mips::FGR64RegClass.hasSubClassEq(RC)) Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164; assert(Opc && "Register class not handled!"); diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index f7cc1f65ba..8a13bd13ea 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -265,6 +265,13 @@ def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add // Reserved ZERO_64, AT_64, K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; +def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add + // Return Values and Arguments + V0, V1, A0, A1, A2, A3, + // Callee save + S0, S1)>; + + // 64bit fp: // * FGR64 - 32 64-bit registers // * AFGR64 - 16 32-bit even registers (32-bit FP Mode) diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 44522688d4..f072802db6 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -30,7 +30,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, MipsArchVersion(Mips32), MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true), HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), - HasMinMax(false), HasSwap(false), HasBitCount(false) + HasMinMax(false), HasSwap(false), HasBitCount(false), InMips16Mode(false) { std::string CPUName = CPU; if (CPUName.empty()) diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 7faf77baa6..4c8bdde904 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -86,6 +86,9 @@ protected: // HasBitCount - Count leading '1' and '0' bits. bool HasBitCount; + // InMips16 -- can process Mips16 instructions + bool InMips16Mode; + InstrItineraryData InstrItins; public: @@ -124,6 +127,7 @@ public: bool isSingleFloat() const { return IsSingleFloat; } bool isNotSingleFloat() const { return !IsSingleFloat; } bool hasVFPU() const { return HasVFPU; } + bool inMips16Mode() const { return InMips16Mode; } bool isLinux() const { return IsLinux; } /// Features related to the presence of specific instructions. -- cgit v1.2.3