From 6bf0c6c53577485360247a527dd16aaa3297b93c Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Fri, 6 Sep 2013 17:32:44 +0000 Subject: mi-sched: improve regpressure tracing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190180 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MachineScheduler.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index 274fb0ef94..618586425f 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -566,7 +566,8 @@ updateScheduledPressure(const std::vector &NewMaxPressure) { unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); if (NewMaxPressure[i] > Limit ) { dbgs() << " " << TRI->getRegPressureSetName(i) << ": " - << NewMaxPressure[i] << " > " << Limit << "\n"; + << NewMaxPressure[i] << " > " << Limit << "(+ " + << BotRPTracker.getLiveThru()[i] << " livethru)\n"; } }); } @@ -2454,6 +2455,10 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand, } } } + DEBUG(if (TryCand.RPDelta.Excess.isValid()) + dbgs() << " SU(" << TryCand.SU->NodeNum << ") " + << TRI->getRegPressureSetName(TryCand.RPDelta.Excess.getPSet()) + << ":" << TryCand.RPDelta.Excess.getUnitInc() << "\n"); // Initialize the candidate if needed. if (!Cand.isValid()) { @@ -2614,7 +2619,7 @@ void ConvergingScheduler::traceCandidate(const SchedCandidate &Cand) { } #endif -/// Pick the best candidate from the top queue. +/// Pick the best candidate from the queue. /// /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during /// DAG building. To adjust for the current scheduling location we need to -- cgit v1.2.3