From 6e032942cf58d1c41f88609a1cec74eb74940ecd Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Mon, 30 May 2011 20:20:15 +0000 Subject: Use the dwarf->llvm mapping to print register names in the cfi directives. Fixes PR9826. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetAsmInfo.h | 4 +++ include/llvm/Target/TargetRegisterInfo.h | 2 ++ lib/MC/MCAsmStreamer.cpp | 30 +++++++++++++++++---- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 4 +++ lib/Target/ARM/ARMBaseRegisterInfo.h | 1 + lib/Target/Alpha/AlphaRegisterInfo.cpp | 5 ++++ lib/Target/Alpha/AlphaRegisterInfo.h | 1 + lib/Target/Blackfin/BlackfinRegisterInfo.cpp | 6 +++++ lib/Target/Blackfin/BlackfinRegisterInfo.h | 1 + lib/Target/CellSPU/SPURegisterInfo.cpp | 4 +++ lib/Target/CellSPU/SPURegisterInfo.h | 1 + lib/Target/MBlaze/MBlazeRegisterInfo.cpp | 4 +++ lib/Target/MBlaze/MBlazeRegisterInfo.h | 1 + lib/Target/MSP430/MSP430RegisterInfo.cpp | 5 ++++ lib/Target/MSP430/MSP430RegisterInfo.h | 1 + lib/Target/Mips/MipsRegisterInfo.cpp | 4 +++ lib/Target/Mips/MipsRegisterInfo.h | 1 + lib/Target/PTX/PTXRegisterInfo.h | 3 +++ lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp | 3 +++ lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h | 1 + lib/Target/PowerPC/PPCFrameLowering.cpp | 8 ++++++ lib/Target/PowerPC/PPCRegisterInfo.cpp | 8 ++++++ lib/Target/PowerPC/PPCRegisterInfo.h | 1 + lib/Target/Sparc/SparcRegisterInfo.cpp | 4 +++ lib/Target/Sparc/SparcRegisterInfo.h | 1 + lib/Target/SystemZ/SystemZRegisterInfo.cpp | 6 +++++ lib/Target/SystemZ/SystemZRegisterInfo.h | 1 + lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp | 4 +++ lib/Target/X86/InstPrinter/X86ATTInstPrinter.h | 1 + lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp | 4 +++ lib/Target/X86/InstPrinter/X86IntelInstPrinter.h | 1 + lib/Target/X86/X86RegisterInfo.cpp | 31 +++++++++++++++------- lib/Target/X86/X86RegisterInfo.h | 1 + lib/Target/XCore/XCoreRegisterInfo.cpp | 4 +++ lib/Target/XCore/XCoreRegisterInfo.h | 1 + test/CodeGen/X86/2008-08-31-EH_RETURN32.ll | 2 +- test/CodeGen/X86/2008-08-31-EH_RETURN64.ll | 2 +- test/CodeGen/X86/empty-functions.ll | 4 +-- test/CodeGen/X86/pr9743.ll | 4 +-- utils/TableGen/RegisterInfoEmitter.cpp | 29 ++++++++++++++++++++ 40 files changed, 178 insertions(+), 21 deletions(-) diff --git a/include/llvm/Target/TargetAsmInfo.h b/include/llvm/Target/TargetAsmInfo.h index c30409d9f9..743a2d47ce 100644 --- a/include/llvm/Target/TargetAsmInfo.h +++ b/include/llvm/Target/TargetAsmInfo.h @@ -95,6 +95,10 @@ public: return TRI->getDwarfRegNum(RegNum, isEH); } + int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const { + return TRI->getLLVMRegNum(DwarfRegNum, isEH); + } + int getSEHRegNum(unsigned RegNum) const { return TRI->getSEHRegNum(RegNum); } diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 2b13483058..075c3d1412 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -802,6 +802,8 @@ public: /// debugging info. virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; + virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0; + /// getFrameRegister - This method should return the register used as a base /// for values allocated in the current stack frame. virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; diff --git a/lib/MC/MCAsmStreamer.cpp b/lib/MC/MCAsmStreamer.cpp index ada3a70bf6..ae9936ce6f 100644 --- a/lib/MC/MCAsmStreamer.cpp +++ b/lib/MC/MCAsmStreamer.cpp @@ -54,6 +54,8 @@ class MCAsmStreamer : public MCStreamer { bool needsSet(const MCExpr *Value); + void EmitRegisterName(int64_t Register); + public: MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os, bool isVerboseAsm, bool useLoc, bool useCFI, @@ -819,13 +821,25 @@ void MCAsmStreamer::EmitCFIEndProc() { EmitEOL(); } +void MCAsmStreamer::EmitRegisterName(int64_t Register) { + if (InstPrinter) { + const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo(); + unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true); + OS << '%' << InstPrinter->getRegName(LLVMRegister); + } else { + OS << Register; + } +} + void MCAsmStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) { MCStreamer::EmitCFIDefCfa(Register, Offset); if (!UseCFI) return; - OS << "\t.cfi_def_cfa " << Register << ", " << Offset; + OS << "\t.cfi_def_cfa "; + EmitRegisterName(Register); + OS << ", " << Offset; EmitEOL(); } @@ -845,7 +859,8 @@ void MCAsmStreamer::EmitCFIDefCfaRegister(int64_t Register) { if (!UseCFI) return; - OS << "\t.cfi_def_cfa_register " << Register; + OS << "\t.cfi_def_cfa_register "; + EmitRegisterName(Register); EmitEOL(); } @@ -855,7 +870,9 @@ void MCAsmStreamer::EmitCFIOffset(int64_t Register, int64_t Offset) { if (!UseCFI) return; - OS << "\t.cfi_offset " << Register << ", " << Offset; + OS << "\t.cfi_offset "; + EmitRegisterName(Register); + OS << ", " << Offset; EmitEOL(); } @@ -906,7 +923,8 @@ void MCAsmStreamer::EmitCFISameValue(int64_t Register) { if (!UseCFI) return; - OS << "\t.cfi_same_value " << Register; + OS << "\t.cfi_same_value "; + EmitRegisterName(Register); EmitEOL(); } @@ -916,7 +934,9 @@ void MCAsmStreamer::EmitCFIRelOffset(int64_t Register, int64_t Offset) { if (!UseCFI) return; - OS << "\t.cfi_rel_offset " << Register << ", " << Offset; + OS << "\t.cfi_rel_offset "; + EmitRegisterName(Register); + OS << ", " << Offset; EmitEOL(); } diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index e6c5c1cb60..4ab37f6cc7 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -684,6 +684,10 @@ int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const { switch (Reg) { diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index 9edf72df21..c60d75a689 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -172,6 +172,7 @@ public: unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; bool isLowRegister(unsigned Reg) const; diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 53a464d3e4..d6c3809960 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -199,6 +199,11 @@ int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { return -1; } +int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const { + llvm_unreachable("What is the dwarf register number"); + return -1; +} + #include "AlphaGenRegisterInfo.inc" std::string AlphaRegisterInfo::getPrettyName(unsigned reg) diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h index b0d4dd03b3..ffe6cf19e2 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.h +++ b/lib/Target/Alpha/AlphaRegisterInfo.h @@ -48,6 +48,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo { unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; static std::string getPrettyName(unsigned reg); }; diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp index b4a9b84f9e..6ca460ef80 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp @@ -351,5 +351,11 @@ int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { return -1; } +int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, + bool isEH) const { + llvm_unreachable("What is the dwarf register number"); + return -1; +} + #include "BlackfinGenRegisterInfo.inc" diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.h b/lib/Target/Blackfin/BlackfinRegisterInfo.h index 642b8adaf9..dc4a69921b 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.h +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.h @@ -60,6 +60,7 @@ namespace llvm { unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; // Utility functions void adjustRegister(MachineBasicBlock &MBB, diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index 0bdd50ac79..623ae76326 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -328,6 +328,10 @@ SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { + return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0); +} + int SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const { diff --git a/lib/Target/CellSPU/SPURegisterInfo.h b/lib/Target/CellSPU/SPURegisterInfo.h index 1708c59837..6ecf0f28dd 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.h +++ b/lib/Target/CellSPU/SPURegisterInfo.h @@ -83,6 +83,7 @@ namespace llvm { //! Get DWARF debugging register number int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; //! Convert D-form load/store to X-form load/store /*! diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp index ed8511df5e..517279fda5 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp @@ -356,5 +356,9 @@ int MBlazeRegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { return MBlazeGenRegisterInfo::getDwarfRegNumFull(RegNo,0); } +int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + #include "MBlazeGenRegisterInfo.inc" diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.h b/lib/Target/MBlaze/MBlazeRegisterInfo.h index 69ec5aa489..380783991c 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.h +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.h @@ -75,6 +75,7 @@ struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo { unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp index 1da6d8da1f..834c9af263 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -242,4 +242,9 @@ int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { return 0; } +int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { + llvm_unreachable("Not implemented yet!"); + return 0; +} + #include "MSP430GenRegisterInfo.inc" diff --git a/lib/Target/MSP430/MSP430RegisterInfo.h b/lib/Target/MSP430/MSP430RegisterInfo.h index e97608323a..e82055876f 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.h +++ b/lib/Target/MSP430/MSP430RegisterInfo.h @@ -61,6 +61,7 @@ public: //! Get DWARF debugging register number int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index c8598ec8ef..f3f7272730 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -278,4 +278,8 @@ getDwarfRegNum(unsigned RegNum, bool isEH) const { return MipsGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + #include "MipsGenRegisterInfo.inc" diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index 767359fd6e..76b0035f16 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -63,6 +63,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo { unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/PTX/PTXRegisterInfo.h b/lib/Target/PTX/PTXRegisterInfo.h index 67e130f153..dc56352381 100644 --- a/lib/Target/PTX/PTXRegisterInfo.h +++ b/lib/Target/PTX/PTXRegisterInfo.h @@ -57,6 +57,9 @@ struct PTXRegisterInfo : public PTXGenRegisterInfo { virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const { return PTXGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } + virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const { + return PTXGenRegisterInfo::getLLVMRegNumFull(RegNum, 0); + } }; // struct PTXRegisterInfo } // namespace llvm diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp index c8db0c4047..dd9f2744e2 100644 --- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp +++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp @@ -26,6 +26,9 @@ StringRef PPCInstPrinter::getOpcodeName(unsigned Opcode) const { return getInstructionName(Opcode); } +StringRef PPCInstPrinter::getRegName(unsigned RegNo) const { + return getRegisterName(RegNo); +} void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { // Check for slwi/srwi mnemonics. diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h index 9cf9db9c26..6a9841199d 100644 --- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h +++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h @@ -33,6 +33,7 @@ public: return SyntaxVariant == 1; } + StringRef getRegName(unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &O); virtual StringRef getOpcodeName(unsigned Opcode) const; diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp index 9d8ef5feef..375e000fe4 100644 --- a/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -487,6 +487,14 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); unsigned Reg = CSI[I].getReg(); if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; + + // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just + // subregisters of CR2. We just need to emit a move of CR2. + if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ) + continue; + if (Reg == PPC::CR2UN) + Reg = PPC::CR2; + MachineLocation CSDst(MachineLocation::VirtualFP, Offset); MachineLocation CSSrc(Reg); Moves.push_back(MachineMove(Label, CSDst, CSSrc)); diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 81f544fc38..3374e9b0b6 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -702,4 +702,12 @@ int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour); } +int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { + // FIXME: Most probably dwarf numbers differs for Linux and Darwin + unsigned Flavour = Subtarget.isPPC64() ? + DWARFFlavour::PPC64 : DWARFFlavour::PPC32; + + return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour); +} + #include "PPCGenRegisterInfo.inc" diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index aa29ffef06..48c25625ea 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -68,6 +68,7 @@ public: unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index b010d04a27..fdd66ddc7d 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -130,5 +130,9 @@ int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + #include "SparcGenRegisterInfo.inc" diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index d930b5398f..56c8068228 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -52,6 +52,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo { unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/lib/Target/SystemZ/SystemZRegisterInfo.cpp index 18b82f3a6c..ed62cfff08 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -139,4 +139,10 @@ int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { return -1; } +int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + assert(0 && "What is the dwarf register number"); + return -1; +} + + #include "SystemZGenRegisterInfo.inc" diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.h b/lib/Target/SystemZ/SystemZRegisterInfo.h index 6379fd3510..cd8f20fee6 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.h +++ b/lib/Target/SystemZ/SystemZRegisterInfo.h @@ -54,6 +54,7 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo { unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp index dd6e353384..6ff4442919 100644 --- a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp @@ -41,6 +41,10 @@ X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) &TM.getSubtarget())); } +StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const { + return getRegisterName(RegNo); +} + void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { // Try to print any aliases first. if (!printAliasInstr(MI, OS)) diff --git a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h index 8d69391c96..0a17c1b368 100644 --- a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h +++ b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h @@ -26,6 +26,7 @@ class X86ATTInstPrinter : public MCInstPrinter { public: X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI); + StringRef getRegName(unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &OS); virtual StringRef getOpcodeName(unsigned Opcode) const; diff --git a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp index 47253ebd20..bdf5af20db 100644 --- a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp @@ -29,6 +29,10 @@ using namespace llvm; #define GET_INSTRUCTION_NAME #include "X86GenAsmWriter1.inc" +StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const { + return getRegisterName(RegNo); +} + void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { printInstruction(MI, OS); diff --git a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h index ca99dc09b8..c51a210dcc 100644 --- a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h +++ b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h @@ -27,6 +27,7 @@ public: X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} + StringRef getRegName(unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &OS); virtual StringRef getOpcodeName(unsigned Opcode) const; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index ebd0d055c6..68cc2cf3bf 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -73,29 +73,40 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, } } -/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF -/// specific numbering, used in debug info and exception tables. -int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { - const X86Subtarget *Subtarget = &TM.getSubtarget(); - unsigned Flavour = DWARFFlavour::X86_64; - +static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) { if (!Subtarget->is64Bit()) { if (Subtarget->isTargetDarwin()) { if (isEH) - Flavour = DWARFFlavour::X86_32_DarwinEH; + return DWARFFlavour::X86_32_DarwinEH; else - Flavour = DWARFFlavour::X86_32_Generic; + return DWARFFlavour::X86_32_Generic; } else if (Subtarget->isTargetCygMing()) { // Unsupported by now, just quick fallback - Flavour = DWARFFlavour::X86_32_Generic; + return DWARFFlavour::X86_32_Generic; } else { - Flavour = DWARFFlavour::X86_32_Generic; + return DWARFFlavour::X86_32_Generic; } } + return DWARFFlavour::X86_64; +} + +/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF +/// specific numbering, used in debug info and exception tables. +int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { + const X86Subtarget *Subtarget = &TM.getSubtarget(); + unsigned Flavour = getFlavour(Subtarget, isEH); return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour); } +/// getLLVMRegNum - This function maps DWARF register numbers to LLVM register. +int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + const X86Subtarget *Subtarget = &TM.getSubtarget(); + unsigned Flavour = getFlavour(Subtarget, isEH); + + return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour); +} + int X86RegisterInfo::getSEHRegNum(unsigned i) const { int reg = getX86RegNum(i); diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 268691a5a4..dd3d3dcdcc 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -80,6 +80,7 @@ public: /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum /// (created by TableGen) for target dependencies. int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; // FIXME: This should be tablegen'd like getDwarfRegNum is int getSEHRegNum(unsigned i) const; diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 00b8b75c9b..46c9e57c1a 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -315,6 +315,10 @@ int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const { const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); diff --git a/lib/Target/XCore/XCoreRegisterInfo.h b/lib/Target/XCore/XCoreRegisterInfo.h index 770483b686..7a9bc9fb87 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.h +++ b/lib/Target/XCore/XCoreRegisterInfo.h @@ -75,6 +75,7 @@ public: //! Get DWARF debugging register number int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll index b92c789a30..1d27fc53ea 100644 --- a/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll +++ b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll @@ -1,5 +1,5 @@ ; Check that eh_return & unwind_init were properly lowered -; RUN: llc < %s | grep %ebp | count 7 +; RUN: llc < %s | grep %ebp | count 9 ; RUN: llc < %s | grep %ecx | count 5 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll index 00ab73569c..d423bfc389 100644 --- a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll +++ b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll @@ -1,5 +1,5 @@ ; Check that eh_return & unwind_init were properly lowered -; RUN: llc < %s | grep %rbp | count 5 +; RUN: llc < %s | grep %rbp | count 7 ; RUN: llc < %s | grep %rcx | count 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/test/CodeGen/X86/empty-functions.ll b/test/CodeGen/X86/empty-functions.ll index 3434133753..874c53ac3b 100644 --- a/test/CodeGen/X86/empty-functions.ll +++ b/test/CodeGen/X86/empty-functions.ll @@ -20,10 +20,10 @@ entry: ; CHECK-FP-NEXT: : ; CHECK-FP-NEXT: .cfi_def_cfa_offset 16 ; CHECK-FP-NEXT: : -; CHECK-FP-NEXT: .cfi_offset 6, -16 +; CHECK-FP-NEXT: .cfi_offset %rbp, -16 ; CHECK-FP-NEXT: movq %rsp, %rbp ; CHECK-FP-NEXT: : -; CHECK-FP-NEXT: .cfi_def_cfa_register 6 +; CHECK-FP-NEXT: .cfi_def_cfa_register %rbp ; CHECK-FP-NEXT: nop ; CHECK-FP-NEXT: : ; CHECK-FP-NEXT: .cfi_endproc diff --git a/test/CodeGen/X86/pr9743.ll b/test/CodeGen/X86/pr9743.ll index 8feccd9ef1..6597c23533 100644 --- a/test/CodeGen/X86/pr9743.ll +++ b/test/CodeGen/X86/pr9743.ll @@ -9,9 +9,9 @@ define void @f() { ; CHECK-NEXT: : ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: : -; CHECK-NEXT: .cfi_offset 6, -16 +; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: : -; CHECK-NEXT: .cfi_def_cfa_register 6 +; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: ret diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 5d92693352..156c145540 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -80,6 +80,8 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" << " virtual int getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const;\n" + << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " + << "unsigned Flavour) const;\n" << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" << " virtual bool needsStackRealignment(const MachineFunction &) const\n" << " { return false; }\n" @@ -989,6 +991,33 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) I->second.push_back(-1); + // Emit reverse information about the dwarf register numbers. + OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, " + << "unsigned Flavour) const {\n" + << " switch (Flavour) {\n" + << " default:\n" + << " assert(0 && \"Unknown DWARF flavour\");\n" + << " return -1;\n"; + + for (unsigned i = 0, e = maxLength; i != e; ++i) { + OS << " case " << i << ":\n" + << " switch (DwarfRegNum) {\n" + << " default:\n" + << " assert(0 && \"Invalid DwarfRegNum\");\n" + << " return -1;\n"; + + for (DwarfRegNumsMapTy::iterator + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { + int DwarfRegNo = I->second[i]; + if (DwarfRegNo >= 0) + OS << " case " << DwarfRegNo << ":\n" + << " return " << getQualifiedName(I->first) << ";\n"; + } + OS << " };\n"; + } + + OS << " };\n}\n\n"; + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { Record *Reg = Regs[i].TheDef; const RecordVal *V = Reg->getValue("DwarfAlias"); -- cgit v1.2.3