From 72d4223ff57f6d03d7802e100cc38634c14c70dc Mon Sep 17 00:00:00 2001 From: Matheus Almeida Date: Wed, 29 Jan 2014 15:12:02 +0000 Subject: [mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200400 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsMSAInstrFormats.td | 11 +++++++++++ lib/Target/Mips/MipsMSAInstrInfo.td | 6 +++++- test/CodeGen/Mips/msa/2r_vector_scalar.ll | 13 ++++++++++++- test/MC/Mips/msa/test_2r_msa64.s | 11 +++++++++++ 4 files changed, 39 insertions(+), 2 deletions(-) create mode 100644 test/MC/Mips/msa/test_2r_msa64.s diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index d463d60354..937898f9d5 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -96,6 +96,17 @@ class MSA_2R_FILL_FMT major, bits<2> df, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } +class MSA_2R_FILL_D_FMT major, bits<2> df, bits<6> minor>: MSA64Inst { + bits<5> rs; + bits<5> wd; + + let Inst{25-18} = major; + let Inst{17-16} = df; + let Inst{15-11} = rs; + let Inst{10-6} = wd; + let Inst{5-0} = minor; +} + class MSA_2R_FMT major, bits<2> df, bits<6> minor>: MSAInst { bits<5> ws; bits<5> wd; diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 1da8095f57..1e18af5fc4 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -236,7 +236,7 @@ def vsplati32 : PatFrag<(ops node:$e0), (v4i32 (build_vector node:$e0, node:$e0, node:$e0, node:$e0))>; def vsplati64 : PatFrag<(ops node:$e0), - (v2i64 (build_vector:$v0 node:$e0, node:$e0))>; + (v2i64 (build_vector node:$e0, node:$e0))>; def vsplatf32 : PatFrag<(ops node:$e0), (v4f32 (build_vector node:$e0, node:$e0, node:$e0, node:$e0))>; @@ -730,6 +730,7 @@ class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; +class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; @@ -2093,6 +2094,8 @@ class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, MSA128HOpnd, GPR32Opnd>; class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, MSA128WOpnd, GPR32Opnd>; +class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, + MSA128DOpnd, GPR64Opnd>; class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE; @@ -3025,6 +3028,7 @@ def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; def FILL_B : FILL_B_ENC, FILL_B_DESC; def FILL_H : FILL_H_ENC, FILL_H_DESC; def FILL_W : FILL_W_ENC, FILL_W_DESC; +def FILL_D : FILL_D_ENC, FILL_D_DESC; def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; diff --git a/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/test/CodeGen/Mips/msa/2r_vector_scalar.ll index c304ede366..64e459e4d9 100644 --- a/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -5,6 +5,10 @@ ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 @llvm_mips_fill_b_ARG1 = global i32 23, align 16 @llvm_mips_fill_b_RES = global <16 x i8> , align 16 @@ -21,6 +25,7 @@ declare <16 x i8> @llvm.mips.fill.b(i32) nounwind ; MIPS-ANY: llvm_mips_fill_b_test: ; MIPS32-DAG: lw [[R1:\$[0-9]+]], +; MIPS64-DAG: ld [[R1:\$[0-9]+]], ; MIPS-ANY-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]] ; MIPS-ANY-DAG: st.b [[R2]], ; MIPS-ANY: .size llvm_mips_fill_b_test @@ -40,6 +45,7 @@ declare <8 x i16> @llvm.mips.fill.h(i32) nounwind ; MIPS-ANY: llvm_mips_fill_h_test: ; MIPS32-DAG: lw [[R1:\$[0-9]+]], +; MIPS64-DAG: ld [[R1:\$[0-9]+]], ; MIPS-ANY-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]] ; MIPS-ANY-DAG: st.h [[R2]], ; MIPS-ANY: .size llvm_mips_fill_h_test @@ -59,6 +65,7 @@ declare <4 x i32> @llvm.mips.fill.w(i32) nounwind ; MIPS-ANY: llvm_mips_fill_w_test: ; MIPS32-DAG: lw [[R1:\$[0-9]+]], +; MIPS64-DAG: ld [[R1:\$[0-9]+]], ; MIPS-ANY-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]] ; MIPS-ANY-DAG: st.w [[R2]], ; MIPS-ANY: .size llvm_mips_fill_w_test @@ -79,11 +86,15 @@ declare <2 x i64> @llvm.mips.fill.d(i64) nounwind ; MIPS-ANY: llvm_mips_fill_d_test: ; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0( ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4( +; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_fill_d_ARG1) ; MIPS32-DAG: ldi.b [[R3:\$w[0-9]+]], 0 ; MIPS32-DAG: insert.w [[R3]][0], [[R1]] ; MIPS32-DAG: insert.w [[R3]][1], [[R2]] ; MIPS32-DAG: insert.w [[R3]][2], [[R1]] ; MIPS32-DAG: insert.w [[R3]][3], [[R2]] +; MIPS64-DAG: fill.d [[WD:\$w[0-9]+]], [[R1]] ; MIPS32-DAG: st.w [[R3]], +; MIPS64-DAG: ld [[RD:\$[0-9]+]], %got_disp(llvm_mips_fill_d_RES) +; MIPS64-DAG: st.d [[WD]], 0([[RD]]) ; MIPS-ANY: .size llvm_mips_fill_d_test -; +; \ No newline at end of file diff --git a/test/MC/Mips/msa/test_2r_msa64.s b/test/MC/Mips/msa/test_2r_msa64.s new file mode 100644 index 0000000000..743fb88087 --- /dev/null +++ b/test/MC/Mips/msa/test_2r_msa64.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s +# +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ +# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ +# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP +# +# CHECK: fill.d $w27, $9 # encoding: [0x7b,0x03,0x4e,0xde] + +# CHECKOBJDUMP: fill.d $w27, $9 + + fill.d $w27, $9 -- cgit v1.2.3