From 7d3e2b78c74ad92bda0836de3e056ee8ec41e446 Mon Sep 17 00:00:00 2001
From: Eli Friedman <eli.friedman@gmail.com>
Date: Wed, 28 Sep 2011 21:00:25 +0000
Subject: PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the
 target CPU does not support them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelLowering.cpp   |  7 +++++++
 test/CodeGen/X86/vec_compare-sse4.ll | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 test/CodeGen/X86/vec_compare-sse4.ll

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index cab9161f5a..fc2d5ce64e 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -8555,6 +8555,13 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
   if (Swap)
     std::swap(Op0, Op1);
 
+  // Check that the operation in question is available (most are plain SSE2,
+  // but PCMPGTQ and PCMPEQQ have different requirements).
+  if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42() && !Subtarget->hasAVX())
+    return SDValue();
+  if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41() && !Subtarget->hasAVX())
+    return SDValue();
+
   // Since SSE has no unsigned integer comparisons, we need to flip  the sign
   // bits of the inputs before performing those operations.
   if (FlipSigns) {
diff --git a/test/CodeGen/X86/vec_compare-sse4.ll b/test/CodeGen/X86/vec_compare-sse4.ll
new file mode 100644
index 0000000000..b4a4a4cfa7
--- /dev/null
+++ b/test/CodeGen/X86/vec_compare-sse4.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=x86 -mattr=-sse3,+sse2 | FileCheck %s -check-prefix=SSE2
+; RUN: llc < %s -march=x86 -mattr=-sse42,+sse41 | FileCheck %s -check-prefix=SSE41
+; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42
+
+define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {
+; SSE42: test1:
+; SSE42: pcmpgtq
+; SSE42: ret
+; SSE41: test1:
+; SSE41-NOT: pcmpgtq
+; SSE41: ret
+; SSE2: test1:
+; SSE2-NOT: pcmpgtq
+; SSE2: ret
+
+	%C = icmp sgt <2 x i64> %A, %B
+  %D = sext <2 x i1> %C to <2 x i64>
+	ret <2 x i64> %D
+}
+
+define <2 x i64> @test2(<2 x i64> %A, <2 x i64> %B) nounwind {
+; SSE42: test2:
+; SSE42: pcmpeqq
+; SSE42: ret
+; SSE41: test2:
+; SSE41: pcmpeqq
+; SSE41: ret
+; SSE2: test2:
+; SSE2-NOT: pcmpeqq
+; SSE2: ret
+
+	%C = icmp eq <2 x i64> %A, %B
+  %D = sext <2 x i1> %C to <2 x i64>
+	ret <2 x i64> %D
+}
-- 
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