From 87476b607cfcfa3db89a7c3d2e403e9246c9927d Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Wed, 30 Apr 2014 11:19:28 +0000 Subject: ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/ARM64InstrFormats.td | 3 + lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp | 6 + lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h | 1 + test/CodeGen/ARM64/aarch64-neon-copy.ll | 4 +- test/CodeGen/ARM64/fast-isel.ll | 2 +- test/CodeGen/ARM64/fcopysign.ll | 4 +- test/CodeGen/ARM64/trap.ll | 2 +- test/CodeGen/ARM64/vector-ext.ll | 2 +- test/CodeGen/ARM64/vector-imm.ll | 18 +-- test/CodeGen/ARM64/vshuffle.ll | 2 +- test/MC/ARM64/advsimd.s | 148 +++++++++++----------- test/MC/ARM64/aliases.s | 6 +- test/MC/Disassembler/ARM64/advsimd.txt | 111 ++++++++-------- test/MC/Disassembler/ARM64/branch.txt | 16 +-- 14 files changed, 167 insertions(+), 158 deletions(-) diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td index 86ddb0722a..f1d6f3d6bb 100644 --- a/lib/Target/ARM64/ARM64InstrFormats.td +++ b/lib/Target/ARM64/ARM64InstrFormats.td @@ -222,6 +222,7 @@ def imm0_65535 : Operand, ImmLeaf { let ParserMatchClass = Imm0_65535Operand; + let PrintMethod = "printHexImm"; } def Imm1_8Operand : AsmOperandClass { @@ -452,6 +453,7 @@ def imm0_255 : Operand, ImmLeaf { let ParserMatchClass = Imm0_255Operand; + let PrintMethod = "printHexImm"; } // imm0_127 predicate - True if the immediate is in the range [0,127] @@ -460,6 +462,7 @@ def imm0_127 : Operand, ImmLeaf { let ParserMatchClass = Imm0_127Operand; + let PrintMethod = "printHexImm"; } // NOTE: These imm0_N operands have to be of type i64 because i64 is the size diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp index 875c758b1a..55aca160d1 100644 --- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp +++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp @@ -1008,6 +1008,12 @@ void ARM64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, } } +void ARM64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNo); + O << format("#%#llx", Op.getImm()); +} + void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h index 66bf6b00bc..990b37b6b4 100644 --- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h +++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h @@ -44,6 +44,7 @@ protected: bool printSysAlias(const MCInst *MI, raw_ostream &O); // Operand printers void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O); void printPostIncOperand1(const MCInst *MI, unsigned OpNo, raw_ostream &O); diff --git a/test/CodeGen/ARM64/aarch64-neon-copy.ll b/test/CodeGen/ARM64/aarch64-neon-copy.ll index ce851525da..3b4cc6cc4f 100644 --- a/test/CodeGen/ARM64/aarch64-neon-copy.ll +++ b/test/CodeGen/ARM64/aarch64-neon-copy.ll @@ -1369,7 +1369,7 @@ define <4 x i16> @concat_vector_v4i16_const() { define <4 x i16> @concat_vector_v4i16_const_one() { ; CHECK-LABEL: concat_vector_v4i16_const_one: -; CHECK: movi {{v[0-9]+}}.4h, #1 +; CHECK: movi {{v[0-9]+}}.4h, #0x1 %r = shufflevector <1 x i16> , <1 x i16> undef, <4 x i32> zeroinitializer ret <4 x i16> %r } @@ -1397,7 +1397,7 @@ define <8 x i16> @concat_vector_v8i16_const() { define <8 x i16> @concat_vector_v8i16_const_one() { ; CHECK-LABEL: concat_vector_v8i16_const_one: -; CHECK: movi {{v[0-9]+}}.8h, #1 +; CHECK: movi {{v[0-9]+}}.8h, #0x1 %r = shufflevector <1 x i16> , <1 x i16> undef, <8 x i32> zeroinitializer ret <8 x i16> %r } diff --git a/test/CodeGen/ARM64/fast-isel.ll b/test/CodeGen/ARM64/fast-isel.ll index ba718d3a95..0194b3a6c2 100644 --- a/test/CodeGen/ARM64/fast-isel.ll +++ b/test/CodeGen/ARM64/fast-isel.ll @@ -87,7 +87,7 @@ entry: define void @t6() nounwind { ; CHECK: t6 -; CHECK: brk #1 +; CHECK: brk #0x1 tail call void @llvm.trap() ret void } diff --git a/test/CodeGen/ARM64/fcopysign.ll b/test/CodeGen/ARM64/fcopysign.ll index 094ce7aa5b..66241df944 100644 --- a/test/CodeGen/ARM64/fcopysign.ll +++ b/test/CodeGen/ARM64/fcopysign.ll @@ -5,7 +5,7 @@ define float @test1(float %x, float %y) nounwind { entry: ; CHECK-LABEL: test1: -; CHECK: movi.4s v2, #128, lsl #24 +; CHECK: movi.4s v2, #0x80, lsl #24 ; CHECK: bit.16b v0, v1, v2 %0 = tail call float @copysignf(float %x, float %y) nounwind readnone ret float %0 @@ -37,7 +37,7 @@ define float @test4() nounwind { entry: ; CHECK-LABEL: test4: ; CHECK: fcvt s0, d0 -; CHECK: movi.4s v[[CONST:[0-9]+]], #128, lsl #24 +; CHECK: movi.4s v[[CONST:[0-9]+]], #0x80, lsl #24 ; CHECK: bit.16b v{{[0-9]+}}, v0, v[[CONST]] %0 = tail call double (...)* @bar() nounwind %1 = fptrunc double %0 to float diff --git a/test/CodeGen/ARM64/trap.ll b/test/CodeGen/ARM64/trap.ll index c9e0beabfc..5e99c32c57 100644 --- a/test/CodeGen/ARM64/trap.ll +++ b/test/CodeGen/ARM64/trap.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm64 | FileCheck %s define void @foo() nounwind { ; CHECK: foo -; CHECK: brk #1 +; CHECK: brk #0x1 tail call void @llvm.trap() ret void } diff --git a/test/CodeGen/ARM64/vector-ext.ll b/test/CodeGen/ARM64/vector-ext.ll index 88889fdef3..9cc0555d8c 100644 --- a/test/CodeGen/ARM64/vector-ext.ll +++ b/test/CodeGen/ARM64/vector-ext.ll @@ -2,7 +2,7 @@ ;CHECK: @func30 ;CHECK: ushll.4s v0, v0, #0 -;CHECK: movi.4s v1, #1 +;CHECK: movi.4s v1, #0x1 ;CHECK: and.16b v0, v0, v1 ;CHECK: str q0, [x0] ;CHECK: ret diff --git a/test/CodeGen/ARM64/vector-imm.ll b/test/CodeGen/ARM64/vector-imm.ll index f1fc3ccf84..2a9450f4e2 100644 --- a/test/CodeGen/ARM64/vector-imm.ll +++ b/test/CodeGen/ARM64/vector-imm.ll @@ -50,35 +50,35 @@ define <2 x double> @foo(<2 x double> %bar) nounwind { define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t1: -; CHECK: movi.4s v0, #75 +; CHECK: movi.4s v0, #0x4b ret <4 x i32> } define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t2: -; CHECK: movi.4s v0, #75, lsl #8 +; CHECK: movi.4s v0, #0x4b, lsl #8 ret <4 x i32> } define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t3: -; CHECK: movi.4s v0, #75, lsl #16 +; CHECK: movi.4s v0, #0x4b, lsl #16 ret <4 x i32> } define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t4: -; CHECK: movi.4s v0, #75, lsl #24 +; CHECK: movi.4s v0, #0x4b, lsl #24 ret <4 x i32> } define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_8h_imm_t5: -; CHECK: movi.8h v0, #75 +; CHECK: movi.8h v0, #0x4b ret <8 x i16> } @@ -86,28 +86,28 @@ entry: define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_8h_imm_t6: -; CHECK: movi.8h v0, #75, lsl #8 +; CHECK: movi.8h v0, #0x4b, lsl #8 ret <8 x i16> } define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t7: -; CHECK: movi.4s v0, #75, msl #8 +; CHECK: movi.4s v0, #0x4b, msl #8 ret <4 x i32> } define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t8: -; CHECK: movi.4s v0, #75, msl #16 +; CHECK: movi.4s v0, #0x4b, msl #16 ret <4 x i32> } define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_16b_imm_t9: -; CHECK: movi.16b v0, #75 +; CHECK: movi.16b v0, #0x4b ret <16 x i8> } diff --git a/test/CodeGen/ARM64/vshuffle.ll b/test/CodeGen/ARM64/vshuffle.ll index fb1227daad..62fd96102d 100644 --- a/test/CodeGen/ARM64/vshuffle.ll +++ b/test/CodeGen/ARM64/vshuffle.ll @@ -15,7 +15,7 @@ ; CHECK: .byte 0 ; 0x0 ; CHECK: test1 ; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI0_0 -; CHECK: movi.8h v[[REG1:[0-9]+]], #1, lsl #8 +; CHECK: movi.8h v[[REG1:[0-9]+]], #0x1, lsl #8 ; CHECK: tbl.8b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]] define <8 x i1> @test1() { entry: diff --git a/test/MC/ARM64/advsimd.s b/test/MC/ARM64/advsimd.s index bd1924e4cd..9990864329 100644 --- a/test/MC/ARM64/advsimd.s +++ b/test/MC/ARM64/advsimd.s @@ -780,19 +780,19 @@ foo: bic.2s v0, #1, lsl #16 bic.2s v0, #1, lsl #24 -; CHECK: bic.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x2f] -; CHECK: bic.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x2f] -; CHECK: bic.2s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x2f] -; CHECK: bic.2s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x2f] -; CHECK: bic.2s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x2f] +; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f] +; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f] +; CHECK: bic.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x2f] +; CHECK: bic.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x2f] +; CHECK: bic.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x2f] bic.4h v0, #1 bic.4h v0, #1, lsl #0 bic.4h v0, #1, lsl #8 -; CHECK: bic.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x2f] -; CHECK: bic.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x2f] -; CHECK: bic.4h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x2f] +; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f] +; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f] +; CHECK: bic.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x2f] bic.4s v0, #1 bic.4s v0, #1, lsl #0 @@ -800,19 +800,19 @@ foo: bic.4s v0, #1, lsl #16 bic.4s v0, #1, lsl #24 -; CHECK: bic.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x6f] -; CHECK: bic.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x6f] -; CHECK: bic.4s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x6f] -; CHECK: bic.4s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x6f] -; CHECK: bic.4s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x6f] +; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f] +; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f] +; CHECK: bic.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x6f] +; CHECK: bic.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x6f] +; CHECK: bic.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x6f] bic.8h v0, #1 bic.8h v0, #1, lsl #0 bic.8h v0, #1, lsl #8 -; CHECK: bic.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x6f] -; CHECK: bic.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x6f] -; CHECK: bic.8h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x6f] +; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f] +; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f] +; CHECK: bic.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x6f] fmov.2d v0, #1.250000e-01 @@ -830,19 +830,19 @@ foo: orr.2s v0, #1, lsl #16 orr.2s v0, #1, lsl #24 -; CHECK: orr.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x0f] -; CHECK: orr.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x0f] -; CHECK: orr.2s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x0f] -; CHECK: orr.2s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x0f] -; CHECK: orr.2s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x0f] +; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f] +; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f] +; CHECK: orr.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x0f] +; CHECK: orr.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x0f] +; CHECK: orr.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x0f] orr.4h v0, #1 orr.4h v0, #1, lsl #0 orr.4h v0, #1, lsl #8 -; CHECK: orr.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x0f] -; CHECK: orr.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x0f] -; CHECK: orr.4h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x0f] +; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f] +; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f] +; CHECK: orr.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x0f] orr.4s v0, #1 orr.4s v0, #1, lsl #0 @@ -850,19 +850,19 @@ foo: orr.4s v0, #1, lsl #16 orr.4s v0, #1, lsl #24 -; CHECK: orr.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x4f] -; CHECK: orr.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x4f] -; CHECK: orr.4s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x4f] -; CHECK: orr.4s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x4f] -; CHECK: orr.4s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x4f] +; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f] +; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f] +; CHECK: orr.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x4f] +; CHECK: orr.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x4f] +; CHECK: orr.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x4f] orr.8h v0, #1 orr.8h v0, #1, lsl #0 orr.8h v0, #1, lsl #8 -; CHECK: orr.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x4f] -; CHECK: orr.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x4f] -; CHECK: orr.8h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x4f] +; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f] +; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f] +; CHECK: orr.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x4f] movi d0, #0x000000000000ff movi.2d v0, #0x000000000000ff @@ -876,11 +876,11 @@ foo: movi.2s v0, #1, lsl #16 movi.2s v0, #1, lsl #24 -; CHECK: movi.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x0f] -; CHECK: movi.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x0f] -; CHECK: movi.2s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x0f] -; CHECK: movi.2s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x0f] -; CHECK: movi.2s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x0f] +; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f] +; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x0f] movi.4s v0, #1 movi.4s v0, #1, lsl #0 @@ -888,43 +888,43 @@ foo: movi.4s v0, #1, lsl #16 movi.4s v0, #1, lsl #24 -; CHECK: movi.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x4f] -; CHECK: movi.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x4f] -; CHECK: movi.4s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x4f] -; CHECK: movi.4s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x4f] -; CHECK: movi.4s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x4f] +; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f] +; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x4f] movi.4h v0, #1 movi.4h v0, #1, lsl #0 movi.4h v0, #1, lsl #8 -; CHECK: movi.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x0f] -; CHECK: movi.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x0f] -; CHECK: movi.4h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x0f] +; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f] +; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f] +; CHECK: movi.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x0f] movi.8h v0, #1 movi.8h v0, #1, lsl #0 movi.8h v0, #1, lsl #8 -; CHECK: movi.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x4f] -; CHECK: movi.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x4f] -; CHECK: movi.8h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x4f] +; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f] +; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f] +; CHECK: movi.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x4f] movi.2s v0, #1, msl #8 movi.2s v0, #1, msl #16 movi.4s v0, #1, msl #8 movi.4s v0, #1, msl #16 -; CHECK: movi.2s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x0f] -; CHECK: movi.2s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x0f] -; CHECK: movi.4s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x4f] -; CHECK: movi.4s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x4f] +; CHECK: movi.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x0f] +; CHECK: movi.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x4f] movi.8b v0, #1 movi.16b v0, #1 -; CHECK: movi.8b v0, #1 ; encoding: [0x20,0xe4,0x00,0x0f] -; CHECK: movi.16b v0, #1 ; encoding: [0x20,0xe4,0x00,0x4f] +; CHECK: movi.8b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x0f] +; CHECK: movi.16b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x4f] mvni.2s v0, #1 mvni.2s v0, #1, lsl #0 @@ -932,11 +932,11 @@ foo: mvni.2s v0, #1, lsl #16 mvni.2s v0, #1, lsl #24 -; CHECK: mvni.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x2f] -; CHECK: mvni.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x2f] -; CHECK: mvni.2s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x2f] -; CHECK: mvni.2s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x2f] -; CHECK: mvni.2s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x2f] mvni.4s v0, #1 mvni.4s v0, #1, lsl #0 @@ -944,37 +944,37 @@ foo: mvni.4s v0, #1, lsl #16 mvni.4s v0, #1, lsl #24 -; CHECK: mvni.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x6f] -; CHECK: mvni.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x6f] -; CHECK: mvni.4s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x6f] -; CHECK: mvni.4s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x6f] -; CHECK: mvni.4s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x6f] mvni.4h v0, #1 mvni.4h v0, #1, lsl #0 mvni.4h v0, #1, lsl #8 -; CHECK: mvni.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x2f] -; CHECK: mvni.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x2f] -; CHECK: mvni.4h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x2f] +; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f] +; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f] +; CHECK: mvni.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x2f] mvni.8h v0, #1 mvni.8h v0, #1, lsl #0 mvni.8h v0, #1, lsl #8 -; CHECK: mvni.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x6f] -; CHECK: mvni.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x6f] -; CHECK: mvni.8h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x6f] +; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f] +; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f] +; CHECK: mvni.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x6f] mvni.2s v0, #1, msl #8 mvni.2s v0, #1, msl #16 mvni.4s v0, #1, msl #8 mvni.4s v0, #1, msl #16 -; CHECK: mvni.2s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x2f] -; CHECK: mvni.2s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x2f] -; CHECK: mvni.4s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x6f] -; CHECK: mvni.4s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x6f] +; CHECK: mvni.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x2f] +; CHECK: mvni.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x6f] ;===-------------------------------------------------------------------------=== ; AdvSIMD scalar x index diff --git a/test/MC/ARM64/aliases.s b/test/MC/ARM64/aliases.s index df746b3c8a..5c2f15cccc 100644 --- a/test/MC/ARM64/aliases.s +++ b/test/MC/ARM64/aliases.s @@ -746,8 +746,8 @@ foo: movi v2.2D, #0x000000000000ff ; CHECK: movi.16b v4, #0 ; encoding: [0x04,0xe4,0x00,0x4f] -; CHECK: movi.16b v4, #1 ; encoding: [0x24,0xe4,0x00,0x4f] -; CHECK: movi.8b v4, #2 ; encoding: [0x44,0xe4,0x00,0x0f] -; CHECK: movi.8b v4, #3 ; encoding: [0x64,0xe4,0x00,0x0f] +; CHECK: movi.16b v4, #0x1 ; encoding: [0x24,0xe4,0x00,0x4f] +; CHECK: movi.8b v4, #0x2 ; encoding: [0x44,0xe4,0x00,0x0f] +; CHECK: movi.8b v4, #0x3 ; encoding: [0x64,0xe4,0x00,0x0f] ; CHECK: movi.2d v1, #0x000000000000ff ; encoding: [0x21,0xe4,0x00,0x6f] ; CHECK: movi.2d v2, #0x000000000000ff ; encoding: [0x22,0xe4,0x00,0x6f] diff --git a/test/MC/Disassembler/ARM64/advsimd.txt b/test/MC/Disassembler/ARM64/advsimd.txt index f9bfc8859c..36aae17a5e 100644 --- a/test/MC/Disassembler/ARM64/advsimd.txt +++ b/test/MC/Disassembler/ARM64/advsimd.txt @@ -535,18 +535,18 @@ 0x20 0x54 0x00 0x2f 0x20 0x74 0x00 0x2f -# CHECK: bic.2s v0, #1 -# CHECK: bic.2s v0, #1, lsl #8 -# CHECK: bic.2s v0, #1, lsl #16 -# CHECK: bic.2s v0, #1, lsl #24 +# CHECK: bic.2s v0, #0x1 +# CHECK: bic.2s v0, #0x1, lsl #8 +# CHECK: bic.2s v0, #0x1, lsl #16 +# CHECK: bic.2s v0, #0x1, lsl #24 0x20 0x94 0x00 0x2f 0x20 0x94 0x00 0x2f 0x20 0xb4 0x00 0x2f -# CHECK: bic.4h v0, #1 -# CHECK: bic.4h v0, #1 -# FIXME: bic.4h v0, #1, lsl #8 +# CHECK: bic.4h v0, #0x1 +# CHECK: bic.4h v0, #0x1 +# FIXME: bic.4h v0, #0x1, lsl #8 # 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0" 0x20 0x14 0x00 0x6f @@ -554,16 +554,16 @@ 0x20 0x54 0x00 0x6f 0x20 0x74 0x00 0x6f -# CHECK: bic.4s v0, #1 -# CHECK: bic.4s v0, #1, lsl #8 -# CHECK: bic.4s v0, #1, lsl #16 -# CHECK: bic.4s v0, #1, lsl #24 +# CHECK: bic.4s v0, #0x1 +# CHECK: bic.4s v0, #0x1, lsl #8 +# CHECK: bic.4s v0, #0x1, lsl #16 +# CHECK: bic.4s v0, #0x1, lsl #24 0x20 0x94 0x00 0x6f 0x20 0xb4 0x00 0x6f -# CHECK: bic.8h v0, #1 -# FIXME: bic.8h v0, #1, lsl #8 +# CHECK: bic.8h v0, #0x1 +# FIXME: bic.8h v0, #0x1, lsl #8 # "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0" 0x00 0xf4 0x02 0x6f @@ -581,16 +581,16 @@ 0x20 0x54 0x00 0x0f 0x20 0x74 0x00 0x0f -# CHECK: orr.2s v0, #1 -# CHECK: orr.2s v0, #1, lsl #8 -# CHECK: orr.2s v0, #1, lsl #16 -# CHECK: orr.2s v0, #1, lsl #24 +# CHECK: orr.2s v0, #0x1 +# CHECK: orr.2s v0, #0x1, lsl #8 +# CHECK: orr.2s v0, #0x1, lsl #16 +# CHECK: orr.2s v0, #0x1, lsl #24 0x20 0x94 0x00 0x0f 0x20 0xb4 0x00 0x0f -# CHECK: orr.4h v0, #1 -# FIXME: orr.4h v0, #1, lsl #8 +# CHECK: orr.4h v0, #0x1 +# FIXME: orr.4h v0, #0x1, lsl #8 # 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0" 0x20 0x14 0x00 0x4f @@ -598,17 +598,16 @@ 0x20 0x54 0x00 0x4f 0x20 0x74 0x00 0x4f -# CHECK: orr.4s v0, #1 -# CHECK: orr.4s v0, #1, lsl #8 -# CHECK: orr.4s v0, #1, lsl #16 -# CHECK: orr.4s v0, #1, lsl #24 +# CHECK: orr.4s v0, #0x1 +# CHECK: orr.4s v0, #0x1, lsl #8 +# CHECK: orr.4s v0, #0x1, lsl #16 +# CHECK: orr.4s v0, #0x1, lsl #24 0x20 0x94 0x00 0x4f 0x20 0xb4 0x00 0x4f -# CHECK: orr.8h v0, #1 -# FIXME: orr.8h v0, #1, lsl #8 -# "orr.8h" should be selected over "fcvtns.4s v0, v1, #0" +# CHECK: orr.8h v0, #0x1 +# CHECK: orr.8h v0, #0x1, lsl #8 0x21 0x70 0x40 0x0c 0x42 0xa0 0x40 0x4c @@ -1445,82 +1444,82 @@ # CHECK: movi d0, #0x000000000000ff # CHECK: movi.2d v0, #0x000000000000ff -# CHECK: movi.8b v0, #1 -# CHECK: movi.16b v0, #1 +# CHECK: movi.8b v0, #0x1 +# CHECK: movi.16b v0, #0x1 0x20 0x04 0x00 0x0f 0x20 0x24 0x00 0x0f 0x20 0x44 0x00 0x0f 0x20 0x64 0x00 0x0f -# CHECK: movi.2s v0, #1 -# CHECK: movi.2s v0, #1, lsl #8 -# CHECK: movi.2s v0, #1, lsl #16 -# CHECK: movi.2s v0, #1, lsl #24 +# CHECK: movi.2s v0, #0x1 +# CHECK: movi.2s v0, #0x1, lsl #8 +# CHECK: movi.2s v0, #0x1, lsl #16 +# CHECK: movi.2s v0, #0x1, lsl #24 0x20 0x04 0x00 0x4f 0x20 0x24 0x00 0x4f 0x20 0x44 0x00 0x4f 0x20 0x64 0x00 0x4f -# CHECK: movi.4s v0, #1 -# CHECK: movi.4s v0, #1, lsl #8 -# CHECK: movi.4s v0, #1, lsl #16 -# CHECK: movi.4s v0, #1, lsl #24 +# CHECK: movi.4s v0, #0x1 +# CHECK: movi.4s v0, #0x1, lsl #8 +# CHECK: movi.4s v0, #0x1, lsl #16 +# CHECK: movi.4s v0, #0x1, lsl #24 0x20 0x84 0x00 0x0f 0x20 0xa4 0x00 0x0f -# CHECK: movi.4h v0, #1 -# CHECK: movi.4h v0, #1, lsl #8 +# CHECK: movi.4h v0, #0x1 +# CHECK: movi.4h v0, #0x1, lsl #8 0x20 0x84 0x00 0x4f 0x20 0xa4 0x00 0x4f -# CHECK: movi.8h v0, #1 -# CHECK: movi.8h v0, #1, lsl #8 +# CHECK: movi.8h v0, #0x1 +# CHECK: movi.8h v0, #0x1, lsl #8 0x20 0x04 0x00 0x2f 0x20 0x24 0x00 0x2f 0x20 0x44 0x00 0x2f 0x20 0x64 0x00 0x2f -# CHECK: mvni.2s v0, #1 -# CHECK: mvni.2s v0, #1, lsl #8 -# CHECK: mvni.2s v0, #1, lsl #16 -# CHECK: mvni.2s v0, #1, lsl #24 +# CHECK: mvni.2s v0, #0x1 +# CHECK: mvni.2s v0, #0x1, lsl #8 +# CHECK: mvni.2s v0, #0x1, lsl #16 +# CHECK: mvni.2s v0, #0x1, lsl #24 0x20 0x04 0x00 0x6f 0x20 0x24 0x00 0x6f 0x20 0x44 0x00 0x6f 0x20 0x64 0x00 0x6f -# CHECK: mvni.4s v0, #1 -# CHECK: mvni.4s v0, #1, lsl #8 -# CHECK: mvni.4s v0, #1, lsl #16 -# CHECK: mvni.4s v0, #1, lsl #24 +# CHECK: mvni.4s v0, #0x1 +# CHECK: mvni.4s v0, #0x1, lsl #8 +# CHECK: mvni.4s v0, #0x1, lsl #16 +# CHECK: mvni.4s v0, #0x1, lsl #24 0x20 0x84 0x00 0x2f 0x20 0xa4 0x00 0x2f -# CHECK: mvni.4h v0, #1 -# CHECK: mvni.4h v0, #1, lsl #8 +# CHECK: mvni.4h v0, #0x1 +# CHECK: mvni.4h v0, #0x1, lsl #8 0x20 0x84 0x00 0x6f 0x20 0xa4 0x00 0x6f -# CHECK: mvni.8h v0, #1 -# CHECK: mvni.8h v0, #1, lsl #8 +# CHECK: mvni.8h v0, #0x1 +# CHECK: mvni.8h v0, #0x1, lsl #8 0x20 0xc4 0x00 0x2f 0x20 0xd4 0x00 0x2f 0x20 0xc4 0x00 0x6f 0x20 0xd4 0x00 0x6f -# CHECK: mvni.2s v0, #1, msl #8 -# CHECK: mvni.2s v0, #1, msl #16 -# CHECK: mvni.4s v0, #1, msl #8 -# CHECK: mvni.4s v0, #1, msl #16 +# CHECK: mvni.2s v0, #0x1, msl #8 +# CHECK: mvni.2s v0, #0x1, msl #16 +# CHECK: mvni.4s v0, #0x1, msl #8 +# CHECK: mvni.4s v0, #0x1, msl #16 0x00 0x88 0x21 0x2e 0x00 0x98 0x21 0x2e diff --git a/test/MC/Disassembler/ARM64/branch.txt b/test/MC/Disassembler/ARM64/branch.txt index c5b254b736..6af1ad886a 100644 --- a/test/MC/Disassembler/ARM64/branch.txt +++ b/test/MC/Disassembler/ARM64/branch.txt @@ -24,21 +24,21 @@ #----------------------------------------------------------------------------- 0x20 0x00 0x20 0xd4 -# CHECK: brk #1 +# CHECK: brk #0x1 0x41 0x00 0xa0 0xd4 -# CHECK: dcps1 #2 +# CHECK: dcps1 #0x2 0x62 0x00 0xa0 0xd4 -# CHECK: dcps2 #3 +# CHECK: dcps2 #0x3 0x83 0x00 0xa0 0xd4 -# CHECK: dcps3 #4 +# CHECK: dcps3 #0x4 0xa0 0x00 0x40 0xd4 -# CHECK: hlt #5 +# CHECK: hlt #0x5 0xc2 0x00 0x00 0xd4 -# CHECK: hvc #6 +# CHECK: hvc #0x6 0xe3 0x00 0x00 0xd4 -# CHECK: smc #7 +# CHECK: smc #0x7 0x01 0x01 0x00 0xd4 -# CHECK: svc #8 +# CHECK: svc #0x8 #----------------------------------------------------------------------------- # PC-relative branches (both positive and negative displacement) -- cgit v1.2.3