From a01820a50824bf592d0a2900cf17ae3adfd5575a Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanaka@mips.com>
Date: Mon, 17 Oct 2011 18:01:00 +0000
Subject: Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142205 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/Mips64InstrInfo.td    | 12 ++++++++----
 lib/Target/Mips/MipsInstrInfo.td      |  4 +---
 lib/Target/Mips/MipsTargetMachine.cpp |  4 ++--
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 49b0223643..7d55cce9fa 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -28,6 +28,9 @@ def Subtract32 : SDNodeXForm<imm, [{
   return getI32Imm((unsigned)N->getZExtValue() - 32);
 }]>;
 
+// shamt field must fit in 5 bits.
+def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>;
+
 // imm32_63 predicate - True if imm is in range [32, 63].
 def imm32_63 : ImmLeaf<i64,
                        [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
@@ -113,9 +116,9 @@ def XOR64    : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
 def NOR64    : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
 
 /// Shift Instructions
-def DSLL     : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;
-def DSRL     : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5>;
-def DSRA     : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5>;
+def DSLL     : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5_64>;
+def DSRL     : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5_64>;
+def DSRA     : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5_64>;
 def DSLL32   : LogicR_shift_rotate_imm64<0x3c, 0x00, "dsll32", shl, imm32_63>;
 def DSRL32   : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>;
 def DSRA32   : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>;
@@ -125,7 +128,8 @@ def DSRAV    : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
 
 // Rotate Instructions
 let Predicates = [HasMips64r2] in {
-  def DROTR    : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>;
+  def DROTR    : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr,
+                                           immZExt5_64>;
   def DROTR32  : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr,
                                            imm32_63>;
   def DROTRV   : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 06b7de7e8e..507010698c 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -191,9 +191,7 @@ def immZExt16  : PatLeaf<(imm), [{
 }], LO16>;
 
 // shamt field must fit in 5 bits.
-def immZExt5 : PatLeaf<(imm), [{
-  return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
-}]>;
+def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
 
 // Mips Address Mode! SDNode frameindex could possibily be a match
 // since load and store instructions from stack used it.
diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp
index 6480da3e6d..a318f81352 100644
--- a/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/lib/Target/Mips/MipsTargetMachine.cpp
@@ -41,10 +41,10 @@ MipsTargetMachine(const Target &T, StringRef TT,
   Subtarget(TT, CPU, FS, isLittle),
   DataLayout(isLittle ?
              (Subtarget.isABI_N64() ?
-              "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
+              "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
               "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
              (Subtarget.isABI_N64() ?
-              "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
+              "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
               "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
   InstrInfo(*this),
   FrameLowering(Subtarget),
-- 
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