From b0f8afd43c54b9b5cb39eb1740eb1fedc4e6471c Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Thu, 12 Dec 2013 00:15:47 +0000 Subject: Fix an over-constrained assertion in MachineFunction::addLiveIn. The assertion was checking that the virtual register VReg used to represent the physical register PReg uses the same register class as the one passed to MachineFunction::addLiveIn. This is over-constraining because it is sufficient to check that the register class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and that VRegRC contains PReg. Indeed, if VReg gets constrained because of some operation constraints between two calls of MachineFunction::addLiveIn, the original assertion cannot match. This fixes . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197097 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MachineFunction.cpp | 11 ++++++++++- test/CodeGen/AArch64/assertion-rc-mismatch.ll | 24 ++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/AArch64/assertion-rc-mismatch.ll diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp index 0703df09a6..96a5ccb969 100644 --- a/lib/CodeGen/MachineFunction.cpp +++ b/lib/CodeGen/MachineFunction.cpp @@ -425,7 +425,16 @@ unsigned MachineFunction::addLiveIn(unsigned PReg, MachineRegisterInfo &MRI = getRegInfo(); unsigned VReg = MRI.getLiveInVirtReg(PReg); if (VReg) { - assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!"); + const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg); + (void)VRegRC; + // A physical register can be added several times. + // Between two calls, the register class of the related virtual register + // may have been constrained to match some operation constraints. + // In that case, check that the current register class includes the + // physical register and is a sub class of the specified RC. + assert((VRegRC == RC || (VRegRC->contains(PReg) && + RC->hasSubClassEq(VRegRC))) && + "Register class mismatch!"); return VReg; } VReg = MRI.createVirtualRegister(RC); diff --git a/test/CodeGen/AArch64/assertion-rc-mismatch.ll b/test/CodeGen/AArch64/assertion-rc-mismatch.ll new file mode 100644 index 0000000000..02b0c0e786 --- /dev/null +++ b/test/CodeGen/AArch64/assertion-rc-mismatch.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; Test case related to . + +; CHECK-LABEL: small +define i64 @small(i64 %encodedBase) { +cmp: + %lnot.i.i = icmp eq i64 %encodedBase, 0 + br i1 %lnot.i.i, label %if, label %else +if: + %tmp1 = call i8* @llvm.returnaddress(i32 0) + br label %end +else: + %tmp3 = call i8* @llvm.returnaddress(i32 0) + %ptr = getelementptr inbounds i8* %tmp3, i64 -16 + %ld = load i8* %ptr, align 4 + %tmp2 = inttoptr i8 %ld to i8* + br label %end +end: + %tmp = phi i8* [ %tmp1, %if ], [ %tmp2, %else ] + %coerce.val.pi56 = ptrtoint i8* %tmp to i64 + ret i64 %coerce.val.pi56 +} + +declare i8* @llvm.returnaddress(i32) -- cgit v1.2.3