From 57e02b3358e8caeddb093fab88fee6f73cd5d597 Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Sun, 12 May 2013 22:55:57 +0000 Subject: SLPVectorizer: Clear the map that maps between scalars to vectors after each round of vectorization. Testcase in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181673 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/Vectorize/VecUtils.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/Transforms/Vectorize/VecUtils.cpp b/lib/Transforms/Vectorize/VecUtils.cpp index 55adf8a816..6f36c938fa 100644 --- a/lib/Transforms/Vectorize/VecUtils.cpp +++ b/lib/Transforms/Vectorize/VecUtils.cpp @@ -633,6 +633,7 @@ Value *BoUpSLP::vectorizeTree(ArrayRef VL, int VF) { numberInstructions(); MustScalarize.clear(); MustExtract.clear(); + VectorizedValues.clear(); return V; } -- cgit v1.2.3 From 507b9242ed3cbac13a1c4c58fe28188e1a0d6fa6 Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Sun, 12 May 2013 22:58:45 +0000 Subject: SLPVectorizer: Fix a bug in the code that generates extracts for values with multiple users. The external user does not have to be in lane #0. We have to save the lane for each scalar so that we know which vector lane to extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181674 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/Vectorize/VecUtils.cpp | 34 ++++++++++++++++++++++------ test/Transforms/SLPVectorizer/X86/diamond.ll | 32 ++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 9 deletions(-) diff --git a/lib/Transforms/Vectorize/VecUtils.cpp b/lib/Transforms/Vectorize/VecUtils.cpp index 6f36c938fa..1362b784f0 100644 --- a/lib/Transforms/Vectorize/VecUtils.cpp +++ b/lib/Transforms/Vectorize/VecUtils.cpp @@ -282,6 +282,7 @@ int BoUpSLP::getTreeCost(ArrayRef VL) { DEBUG(dbgs()<<"SLP: Adding to MustExtract " "because of a safe out of tree usage.\n"); MustExtract.insert(*it); + continue; } if (Lane == -1) Lane = LaneMap[*I]; if (Lane != LaneMap[*I]) { @@ -610,6 +611,9 @@ Value *BoUpSLP::Scalarize(ArrayRef VL, VectorType *Ty) { GatherInstructions.push_back(Vec); } + for (unsigned i = 0; i < Ty->getNumElements(); ++i) + VectorizedValues[VL[i]] = Vec; + return Vec; } @@ -617,6 +621,7 @@ Value *BoUpSLP::vectorizeTree(ArrayRef VL, int VF) { Value *V = vectorizeTree_rec(VL, VF); Instruction *LastInstr = GetLastInstr(VL, VL.size()); + int LastInstrIdx = InstrIdx[LastInstr]; IRBuilder<> Builder(LastInstr); for (ValueSet::iterator it = MustExtract.begin(), e = MustExtract.end(); it != e; ++it) { @@ -625,7 +630,15 @@ Value *BoUpSLP::vectorizeTree(ArrayRef VL, int VF) { assert(LaneMap.count(I) && "Unable to find the lane for the external use"); Value *Idx = Builder.getInt32(LaneMap[I]); Value *Extract = Builder.CreateExtractElement(Vec, Idx); - I->replaceAllUsesWith(Extract); + bool Replaced = false; + for (Value::use_iterator U = I->use_begin(), UE = U->use_end(); U != UE; + ++U) { + Instruction *UI = cast(*U); + if (UI->getParent() != I->getParent() || InstrIdx[UI] > LastInstrIdx) + UI->replaceUsesOfWith(I ,Extract); + Replaced = true; + } + assert(Replaced && "Must replace at least one outside user"); } // We moved some instructions around. We have to number them again @@ -691,7 +704,10 @@ Value *BoUpSLP::vectorizeTree_rec(ArrayRef VL, int VF) { IRBuilder<> Builder(GetLastInstr(VL, VF)); CastInst *CI = dyn_cast(VL0); Value *V = Builder.CreateCast(CI->getOpcode(), InVec, VecTy); - VectorizedValues[VL0] = V; + + for (int i = 0; i < VF; ++i) + VectorizedValues[VL[i]] = V; + return V; } case Instruction::Add: @@ -723,7 +739,10 @@ Value *BoUpSLP::vectorizeTree_rec(ArrayRef VL, int VF) { IRBuilder<> Builder(GetLastInstr(VL, VF)); BinaryOperator *BinOp = cast(VL0); Value *V = Builder.CreateBinOp(BinOp->getOpcode(), RHS,LHS); - VectorizedValues[VL0] = V; + + for (int i = 0; i < VF; ++i) + VectorizedValues[VL[i]] = V; + return V; } case Instruction::Load: { @@ -740,7 +759,10 @@ Value *BoUpSLP::vectorizeTree_rec(ArrayRef VL, int VF) { VecTy->getPointerTo()); LI = Builder.CreateLoad(VecPtr); LI->setAlignment(Alignment); - VectorizedValues[VL0] = LI; + + for (int i = 0; i < VF; ++i) + VectorizedValues[VL[i]] = LI; + return LI; } case Instruction::Store: { @@ -763,9 +785,7 @@ Value *BoUpSLP::vectorizeTree_rec(ArrayRef VL, int VF) { return 0; } default: - Value *S = Scalarize(VL, VecTy); - VectorizedValues[VL0] = S; - return S; + return Scalarize(VL, VecTy); } } diff --git a/test/Transforms/SLPVectorizer/X86/diamond.ll b/test/Transforms/SLPVectorizer/X86/diamond.ll index 49c8712d20..8959b0d9ee 100644 --- a/test/Transforms/SLPVectorizer/X86/diamond.ll +++ b/test/Transforms/SLPVectorizer/X86/diamond.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s +; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" @@ -74,6 +74,34 @@ entry: %add20 = mul i32 %3, %mul238 %arrayidx21 = getelementptr inbounds i32* %B, i64 3 store i32 %add20, i32* %arrayidx21, align 4 - ret i32 %0 ;<--------- This value has multiple users and can't be vectorized. + ret i32 %0 ;<--------- This value has multiple users } +; In this example we have an external user that is not the first element in the vector. +; CHECK: @extr_user1 +; CHECK: store <4 x i32> +; CHECK-NEXT: extractelement <4 x i32> +; CHECK: ret +define i32 @extr_user1(i32* noalias nocapture %B, i32* noalias nocapture %A, i32 %n, i32 %m) { +entry: + %0 = load i32* %A, align 4 + %mul238 = add i32 %m, %n + %add = mul i32 %0, %mul238 + store i32 %add, i32* %B, align 4 + %arrayidx4 = getelementptr inbounds i32* %A, i64 1 + %1 = load i32* %arrayidx4, align 4 + %add8 = mul i32 %1, %mul238 + %arrayidx9 = getelementptr inbounds i32* %B, i64 1 + store i32 %add8, i32* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds i32* %A, i64 2 + %2 = load i32* %arrayidx10, align 4 + %add14 = mul i32 %2, %mul238 + %arrayidx15 = getelementptr inbounds i32* %B, i64 2 + store i32 %add14, i32* %arrayidx15, align 4 + %arrayidx16 = getelementptr inbounds i32* %A, i64 3 + %3 = load i32* %arrayidx16, align 4 + %add20 = mul i32 %3, %mul238 + %arrayidx21 = getelementptr inbounds i32* %B, i64 3 + store i32 %add20, i32* %arrayidx21, align 4 + ret i32 %1 ;<--------- This value has multiple users +} -- cgit v1.2.3 From aa4f36407f51d827af834d05821c7466db32f147 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Mon, 13 May 2013 00:18:24 +0000 Subject: XFAIL this test for mingw too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181678 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/ExecutionEngine/MCJIT/eh.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/ExecutionEngine/MCJIT/eh.ll b/test/ExecutionEngine/MCJIT/eh.ll index cd67dd70c5..c2135736ad 100644 --- a/test/ExecutionEngine/MCJIT/eh.ll +++ b/test/ExecutionEngine/MCJIT/eh.ll @@ -1,5 +1,5 @@ ; RUN: %lli_mcjit %s -; XFAIL: arm, cygwin, win32 +; XFAIL: arm, cygwin, win32, mingw declare i8* @__cxa_allocate_exception(i64) declare void @__cxa_throw(i8*, i8*, i8*) declare i32 @__gxx_personality_v0(...) -- cgit v1.2.3 From 4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Mon, 13 May 2013 01:16:13 +0000 Subject: Remove the MachineMove class. It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/AsmPrinter.h | 7 ++-- include/llvm/CodeGen/MachineModuleInfo.h | 16 ++++----- include/llvm/MC/MCAsmInfo.h | 11 +++--- include/llvm/MC/MachineLocation.h | 29 ---------------- include/llvm/Support/TargetRegistry.h | 10 +++--- include/llvm/Target/TargetMachine.h | 1 + lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 9 +++-- lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 39 +++++++++------------- lib/CodeGen/AsmPrinter/DwarfException.h | 1 - lib/CodeGen/LLVMTargetMachine.cpp | 19 ++++++----- lib/CodeGen/MachineModuleInfo.cpp | 35 ++++++++++++++++++- lib/MC/MCDisassembler/Disassembler.cpp | 10 +++--- lib/MC/MCDwarf.cpp | 39 ++-------------------- lib/Target/AArch64/AArch64TargetMachine.cpp | 1 + .../AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp | 9 ++--- lib/Target/ARM/ARMTargetMachine.cpp | 2 ++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 2 +- lib/Target/Hexagon/HexagonTargetMachine.cpp | 1 + .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 9 ++--- lib/Target/MBlaze/MBlazeTargetMachine.cpp | 1 + .../MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp | 2 +- lib/Target/MSP430/MSP430TargetMachine.cpp | 4 ++- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 8 ++--- lib/Target/Mips/MipsTargetMachine.cpp | 1 + lib/Target/NVPTX/NVPTXTargetMachine.cpp | 4 ++- .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 9 ++--- lib/Target/PowerPC/PPCTargetMachine.cpp | 1 + lib/Target/R600/AMDGPUTargetMachine.cpp | 1 + lib/Target/Sparc/SparcTargetMachine.cpp | 1 + .../SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp | 10 +++--- lib/Target/SystemZ/SystemZTargetMachine.cpp | 1 + lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp | 16 +++++---- lib/Target/X86/X86TargetMachine.cpp | 2 ++ .../XCore/MCTargetDesc/XCoreMCTargetDesc.cpp | 8 ++--- lib/Target/XCore/XCoreTargetMachine.cpp | 1 + tools/llvm-mc/llvm-mc.cpp | 6 ++-- tools/llvm-objdump/MachODump.cpp | 5 +-- tools/llvm-objdump/llvm-objdump.cpp | 15 +++++---- 38 files changed, 169 insertions(+), 177 deletions(-) diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h index c2fd6ce367..5973255047 100644 --- a/include/llvm/CodeGen/AsmPrinter.h +++ b/include/llvm/CodeGen/AsmPrinter.h @@ -38,8 +38,8 @@ namespace llvm { class MachineConstantPoolValue; class MachineJumpTableInfo; class MachineModuleInfo; - class MachineMove; class MCAsmInfo; + class MCCFIInstruction; class MCContext; class MCSection; class MCStreamer; @@ -417,9 +417,8 @@ namespace llvm { // Dwarf Lowering Routines //===------------------------------------------------------------------===// - /// EmitCFIFrameMove - Emit frame instruction to describe the layout of the - /// frame. - void EmitCFIFrameMove(const MachineMove &Move) const; + /// \brief Emit frame instruction to describe the layout of the frame. + void emitCFIInstruction(const MCCFIInstruction &Inst) const; //===------------------------------------------------------------------===// // Inline Asm Support diff --git a/include/llvm/CodeGen/MachineModuleInfo.h b/include/llvm/CodeGen/MachineModuleInfo.h index b719757822..95eb1e40dc 100644 --- a/include/llvm/CodeGen/MachineModuleInfo.h +++ b/include/llvm/CodeGen/MachineModuleInfo.h @@ -106,9 +106,9 @@ class MachineModuleInfo : public ImmutablePass { /// want. MachineModuleInfoImpl *ObjFileMMI; - /// FrameMoves - List of moves done by a function's prolog. Used to construct - /// frame maps by debug and exception handling consumers. - std::vector FrameMoves; + /// List of moves done by a function's prolog. Used to construct frame maps + /// by debug and exception handling consumers. + std::vector FrameInstructions; /// CompactUnwindEncoding - If the target supports it, this is the compact /// unwind encoding. It replaces a function's CIE and FDE. @@ -231,15 +231,15 @@ public: UsesVAFloatArgument = b; } - /// getFrameMoves - Returns a reference to a list of moves done in the current + /// \brief Returns a reference to a list of cfi instructions in the current /// function's prologue. Used to construct frame maps for debug and exception /// handling comsumers. - const std::vector &getFrameMoves() { return FrameMoves; } + const std::vector &getFrameInstructions() { + return FrameInstructions; + } void addFrameMove(MCSymbol *Label, const MachineLocation &Dst, - const MachineLocation &Src) { - FrameMoves.push_back(MachineMove(Label, Dst, Src)); - } + const MachineLocation &Src); /// getCompactUnwindEncoding - Returns the compact unwind encoding for a /// function if the target supports the encoding. This encoding replaces a diff --git a/include/llvm/MC/MCAsmInfo.h b/include/llvm/MC/MCAsmInfo.h index d020de3004..72d325f79c 100644 --- a/include/llvm/MC/MCAsmInfo.h +++ b/include/llvm/MC/MCAsmInfo.h @@ -17,6 +17,7 @@ #define LLVM_MC_MCASMINFO_H #include "llvm/MC/MCDirectives.h" +#include "llvm/MC/MCDwarf.h" #include "llvm/MC/MachineLocation.h" #include #include @@ -332,7 +333,7 @@ namespace llvm { //===--- Prologue State ----------------------------------------------===// - std::vector InitialFrameState; + std::vector InitialFrameState; public: explicit MCAsmInfo(); @@ -567,11 +568,11 @@ namespace llvm { return DwarfRegNumForCFI; } - void addInitialFrameState(MCSymbol *label, const MachineLocation &D, - const MachineLocation &S) { - InitialFrameState.push_back(MachineMove(label, D, S)); + void addInitialFrameState(const MCCFIInstruction &Inst) { + InitialFrameState.push_back(Inst); } - const std::vector &getInitialFrameState() const { + + const std::vector &getInitialFrameState() const { return InitialFrameState; } }; diff --git a/include/llvm/MC/MachineLocation.h b/include/llvm/MC/MachineLocation.h index 83c8b72ee4..c4a96606b1 100644 --- a/include/llvm/MC/MachineLocation.h +++ b/include/llvm/MC/MachineLocation.h @@ -10,11 +10,6 @@ // frame. Locations will be one of two forms; a register or an address formed // from a base address plus an offset. Register indirection can be specified by // explicitly passing an offset to the constructor. -// -// The MachineMove class is used to represent abstract move operations in the -// prolog/epilog of a compiled function. A collection of these objects can be -// used by a debug consumer to track the location of values when unwinding stack -// frames. //===----------------------------------------------------------------------===// @@ -74,30 +69,6 @@ public: void dump(); #endif }; - -/// MachineMove - This class represents the save or restore of a callee saved -/// register that exception or debug info needs to know about. -class MachineMove { -private: - /// Label - Symbol for post-instruction address when result of move takes - /// effect. - MCSymbol *Label; - - // Move to & from location. - MachineLocation Destination, Source; -public: - MachineMove() : Label(0) {} - - MachineMove(MCSymbol *label, const MachineLocation &D, - const MachineLocation &S) - : Label(label), Destination(D), Source(S) {} - - // Accessors - MCSymbol *getLabel() const { return Label; } - const MachineLocation &getDestination() const { return Destination; } - const MachineLocation &getSource() const { return Source; } -}; - } // End llvm namespace #endif diff --git a/include/llvm/Support/TargetRegistry.h b/include/llvm/Support/TargetRegistry.h index 5bfb8ad41d..e1f6706618 100644 --- a/include/llvm/Support/TargetRegistry.h +++ b/include/llvm/Support/TargetRegistry.h @@ -70,7 +70,8 @@ namespace llvm { typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT); - typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(StringRef TT); + typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI, + StringRef TT); typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, Reloc::Model RM, CodeModel::Model CM, @@ -265,10 +266,11 @@ namespace llvm { /// feature set; it should always be provided. Generally this should be /// either the target triple from the module, or the target triple of the /// host if that does not exist. - MCAsmInfo *createMCAsmInfo(StringRef Triple) const { + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, + StringRef Triple) const { if (!MCAsmInfoCtorFn) return 0; - return MCAsmInfoCtorFn(Triple); + return MCAsmInfoCtorFn(MRI, Triple); } /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. @@ -803,7 +805,7 @@ namespace llvm { TargetRegistry::RegisterMCAsmInfo(T, &Allocator); } private: - static MCAsmInfo *Allocator(StringRef TT) { + static MCAsmInfo *Allocator(const MCRegisterInfo &MRI, StringRef TT) { return new MCAsmInfoImpl(TT); } diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 37a79fe852..c5e4b278d9 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -292,6 +292,7 @@ protected: // Can only create subclasses. Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + void initAsmInfo(); public: /// \brief Register analysis passes for this target with a pass manager. /// diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index eb744d243b..7ad4f57f75 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -636,14 +636,13 @@ void AsmPrinter::emitPrologLabel(const MachineInstr &MI) { OutStreamer.EmitCompactUnwindEncoding(MMI->getCompactUnwindEncoding()); MachineModuleInfo &MMI = MF->getMMI(); - const std::vector &Moves = MMI.getFrameMoves(); + std::vector Instructions = MMI.getFrameInstructions(); bool FoundOne = false; (void)FoundOne; - for (std::vector::const_iterator I = Moves.begin(), - E = Moves.end(); - I != E; ++I) { + for (std::vector::iterator I = Instructions.begin(), + E = Instructions.end(); I != E; ++I) { if (I->getLabel() == Label) { - EmitCFIFrameMove(*I); + emitCFIInstruction(*I); FoundOne = true; } } diff --git a/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp b/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp index 31e42d47cf..e6d67e8822 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp @@ -169,28 +169,21 @@ void AsmPrinter::EmitSectionOffset(const MCSymbol *Label, // Dwarf Lowering Routines //===----------------------------------------------------------------------===// -/// EmitCFIFrameMove - Emit a frame instruction. -void AsmPrinter::EmitCFIFrameMove(const MachineMove &Move) const { - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - - const MachineLocation &Dst = Move.getDestination(); - const MachineLocation &Src = Move.getSource(); - - // If advancing cfa. - if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { - if (Src.getReg() == MachineLocation::VirtualFP) { - OutStreamer.EmitCFIDefCfaOffset(-Src.getOffset()); - } else { - // Reg + Offset - OutStreamer.EmitCFIDefCfa(RI->getDwarfRegNum(Src.getReg(), true), - Src.getOffset()); - } - } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { - assert(Dst.isReg() && "Machine move not supported yet."); - OutStreamer.EmitCFIDefCfaRegister(RI->getDwarfRegNum(Dst.getReg(), true)); - } else { - assert(!Dst.isReg() && "Machine move not supported yet."); - OutStreamer.EmitCFIOffset(RI->getDwarfRegNum(Src.getReg(), true), - Dst.getOffset()); +void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const { + switch (Inst.getOperation()) { + default: + llvm_unreachable("Unexpected instruction"); + case MCCFIInstruction::OpDefCfaOffset: + OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset()); + break; + case MCCFIInstruction::OpDefCfa: + OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset()); + break; + case MCCFIInstruction::OpDefCfaRegister: + OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister()); + break; + case MCCFIInstruction::OpOffset: + OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset()); + break; } } diff --git a/lib/CodeGen/AsmPrinter/DwarfException.h b/lib/CodeGen/AsmPrinter/DwarfException.h index 74b1b13367..49a85d81b4 100644 --- a/lib/CodeGen/AsmPrinter/DwarfException.h +++ b/lib/CodeGen/AsmPrinter/DwarfException.h @@ -23,7 +23,6 @@ namespace llvm { template class SmallVectorImpl; struct LandingPadInfo; class MachineModuleInfo; -class MachineMove; class MachineInstr; class MachineFunction; class MCAsmInfo; diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index 1a09837834..7ce5cc6f67 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -62,14 +62,8 @@ static bool getVerboseAsm() { llvm_unreachable("Invalid verbose asm state"); } -LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, - StringRef CPU, StringRef FS, - TargetOptions Options, - Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL) - : TargetMachine(T, Triple, CPU, FS, Options) { - CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL); - AsmInfo = T.createMCAsmInfo(Triple); +void LLVMTargetMachine::initAsmInfo() { + AsmInfo = TheTarget.createMCAsmInfo(*getRegisterInfo(), TargetTriple); // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0, // and if the old one gets included then MCAsmInfo will be NULL and // we'll crash later. @@ -79,6 +73,15 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, "and that InitializeAllTargetMCs() is being invoked!"); } +LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, + StringRef CPU, StringRef FS, + TargetOptions Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : TargetMachine(T, Triple, CPU, FS, Options) { + CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL); +} + void LLVMTargetMachine::addAnalysisPasses(PassManagerBase &PM) { PM.add(createBasicTargetTransformInfoPass(getTargetLowering())); } diff --git a/lib/CodeGen/MachineModuleInfo.cpp b/lib/CodeGen/MachineModuleInfo.cpp index 8af9d053b1..74cf9f50df 100644 --- a/lib/CodeGen/MachineModuleInfo.cpp +++ b/lib/CodeGen/MachineModuleInfo.cpp @@ -268,6 +268,39 @@ MachineModuleInfo::MachineModuleInfo() MachineModuleInfo::~MachineModuleInfo() { } +static MCCFIInstruction convertMoveToCFI(const MCRegisterInfo &MRI, + MCSymbol *Label, + const MachineLocation &Dst, + const MachineLocation &Src) { + // If advancing cfa. + if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { + if (Src.getReg() == MachineLocation::VirtualFP) + return MCCFIInstruction::createDefCfaOffset(Label, Src.getOffset()); + // Reg + Offset + return MCCFIInstruction::createDefCfa( + Label, MRI.getDwarfRegNum(Src.getReg(), true), -Src.getOffset()); + } + + if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { + assert(Dst.isReg() && "Machine move not supported yet."); + return MCCFIInstruction::createDefCfaRegister( + Label, MRI.getDwarfRegNum(Dst.getReg(), true)); + } + + assert(!Dst.isReg() && "Machine move not supported yet."); + return MCCFIInstruction::createOffset( + Label, MRI.getDwarfRegNum(Src.getReg(), true), Dst.getOffset()); +} + + +void MachineModuleInfo::addFrameMove(MCSymbol *Label, + const MachineLocation &Dst, + const MachineLocation &Src) { + MCCFIInstruction I = + convertMoveToCFI(Context.getRegisterInfo(), Label, Dst, Src); + FrameInstructions.push_back(I); +} + bool MachineModuleInfo::doInitialization(Module &M) { ObjFileMMI = 0; @@ -303,7 +336,7 @@ bool MachineModuleInfo::doFinalization(Module &M) { /// void MachineModuleInfo::EndFunction() { // Clean up frame info. - FrameMoves.clear(); + FrameInstructions.clear(); // Clean up exception info. LandingPads.clear(); diff --git a/lib/MC/MCDisassembler/Disassembler.cpp b/lib/MC/MCDisassembler/Disassembler.cpp index 4766b37476..d3c019246c 100644 --- a/lib/MC/MCDisassembler/Disassembler.cpp +++ b/lib/MC/MCDisassembler/Disassembler.cpp @@ -42,8 +42,12 @@ LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU, const Target *TheTarget = TargetRegistry::lookupTarget(Triple, Error); assert(TheTarget && "Unable to create target!"); + const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple); + if (!MRI) + return 0; + // Get the assembler info needed to setup the MCContext. - const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(Triple); + const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple); if (!MAI) return 0; @@ -51,10 +55,6 @@ LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU, if (!MII) return 0; - const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple); - if (!MRI) - return 0; - // Package up features to be passed to target/subtarget std::string FeaturesStr; diff --git a/lib/MC/MCDwarf.cpp b/lib/MC/MCDwarf.cpp index 7640a63ee3..efe0c46db8 100644 --- a/lib/MC/MCDwarf.cpp +++ b/lib/MC/MCDwarf.cpp @@ -873,17 +873,6 @@ static void EmitPersonality(MCStreamer &streamer, const MCSymbol &symbol, streamer.EmitValue(v, size); } -static const MachineLocation TranslateMachineLocation( - const MCRegisterInfo &MRI, - const MachineLocation &Loc) { - unsigned Reg = Loc.getReg() == MachineLocation::VirtualFP ? - MachineLocation::VirtualFP : - unsigned(MRI.getDwarfRegNum(Loc.getReg(), true)); - const MachineLocation &NewLoc = Loc.isReg() ? - MachineLocation(Reg) : MachineLocation(Reg, Loc.getOffset()); - return NewLoc; -} - namespace { class FrameEmitterImpl { int CFAOffset; @@ -1316,32 +1305,8 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(MCStreamer &streamer, // Initial Instructions const MCAsmInfo &MAI = context.getAsmInfo(); - const std::vector &Moves = MAI.getInitialFrameState(); - std::vector Instructions; - - for (int i = 0, n = Moves.size(); i != n; ++i) { - MCSymbol *Label = Moves[i].getLabel(); - const MachineLocation &Dst = - TranslateMachineLocation(MRI, Moves[i].getDestination()); - const MachineLocation &Src = - TranslateMachineLocation(MRI, Moves[i].getSource()); - - if (Dst.isReg()) { - assert(Dst.getReg() == MachineLocation::VirtualFP); - assert(!Src.isReg()); - MCCFIInstruction Inst = - MCCFIInstruction::createDefCfa(Label, Src.getReg(), -Src.getOffset()); - Instructions.push_back(Inst); - } else { - assert(Src.isReg()); - unsigned Reg = Src.getReg(); - int Offset = Dst.getOffset(); - MCCFIInstruction Inst = - MCCFIInstruction::createOffset(Label, Reg, Offset); - Instructions.push_back(Inst); - } - } - + const std::vector &Instructions = + MAI.getInitialFrameState(); EmitCFIInstructions(streamer, Instructions, NULL); // Padding diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index df599d599d..f1695e2ce2 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -38,6 +38,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT, TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget) { + initAsmInfo(); } namespace { diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp index 3435217bb2..eeec608820 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -57,13 +57,14 @@ static MCRegisterInfo *createAArch64MCRegisterInfo(StringRef Triple) { return X; } -static MCAsmInfo *createAArch64MCAsmInfo(StringRef TT) { +static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, + StringRef TT) { Triple TheTriple(TT); MCAsmInfo *MAI = new AArch64ELFMCAsmInfo(); - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(AArch64::XSP, 0); - MAI->addInitialFrameState(0, Dst, Src); + unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0); + MAI->addInitialFrameState(Inst); return MAI; } diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 42c7d2c437..17c52c94a0 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -85,6 +85,7 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget) { + initAsmInfo(); if (!Subtarget.hasARMOps()) report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " "support ARM mode execution!"); @@ -117,6 +118,7 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, FrameLowering(Subtarget.hasThumb2() ? new ARMFrameLowering(Subtarget) : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) { + initAsmInfo(); } namespace { diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 57239f8011..b858fff546 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -159,7 +159,7 @@ static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) { return X; } -static MCAsmInfo *createARMMCAsmInfo(StringRef TT) { +static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { Triple TheTriple(TT); if (TheTriple.isOSDarwin()) diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index dc44b34cff..2d5529b5c9 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -79,6 +79,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, FrameLowering(Subtarget), InstrItins(&Subtarget.getInstrItineraryData()) { setMCUseCFI(false); + initAsmInfo(); } // addPassesForOptimizations - Allow the backend (target) to add Target diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 273bc22b8e..2f93a5299c 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -54,13 +54,14 @@ static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT, return X; } -static MCAsmInfo *createHexagonMCAsmInfo(StringRef TT) { +static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, + StringRef TT) { MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); // VirtualFP = (R30 + #0). - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(Hexagon::R30, 0); - MAI->addInitialFrameState(0, Dst, Src); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( + 0, Hexagon::R30, 0); + MAI->addInitialFrameState(Inst); return MAI; } diff --git a/lib/Target/MBlaze/MBlazeTargetMachine.cpp b/lib/Target/MBlaze/MBlazeTargetMachine.cpp index bcdd32fed9..c75895575d 100644 --- a/lib/Target/MBlaze/MBlazeTargetMachine.cpp +++ b/lib/Target/MBlaze/MBlazeTargetMachine.cpp @@ -43,6 +43,7 @@ MBlazeTargetMachine(const Target &T, StringRef TT, FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { + initAsmInfo(); } namespace { diff --git a/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp b/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp index ec76dba491..5bc0668f35 100644 --- a/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp +++ b/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp @@ -53,7 +53,7 @@ static MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU, return X; } -static MCAsmInfo *createMCAsmInfo(StringRef TT) { +static MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { Triple TheTriple(TT); switch (TheTriple.getOS()) { default: diff --git a/lib/Target/MSP430/MSP430TargetMachine.cpp b/lib/Target/MSP430/MSP430TargetMachine.cpp index 164e351df9..6710a09707 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -36,7 +36,9 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, // FIXME: Check DataLayout string. DL("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), - FrameLowering(Subtarget) { } + FrameLowering(Subtarget) { + initAsmInfo(); +} namespace { /// MSP430 Code Generator Pass Configuration Options. diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index 26694ffdac..837fabee76 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -93,12 +93,12 @@ static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, return X; } -static MCAsmInfo *createMipsMCAsmInfo(StringRef TT) { +static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { MCAsmInfo *MAI = new MipsMCAsmInfo(TT); - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(Mips::SP, 0); - MAI->addInitialFrameState(0, Dst, Src); + unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, SP, 0); + MAI->addInitialFrameState(Inst); return MAI; } diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index a876f1c7f0..89407351a0 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -72,6 +72,7 @@ MipsTargetMachine(const Target &T, StringRef TT, FrameLowering(MipsFrameLowering::create(*this, Subtarget)), TLInfo(MipsTargetLowering::create(*this)), TSInfo(*this), JITInfo() { + initAsmInfo(); } diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 67ca6b58e5..5f35edf219 100644 --- a/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -72,7 +72,9 @@ NVPTXTargetMachine::NVPTXTargetMachine( Subtarget(TT, CPU, FS, is64bit), DL(Subtarget.getDataLayout()), InstrInfo(*this), TLInfo(*this), TSInfo(*this), FrameLowering( - *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {} + *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ { + initAsmInfo(); +} void NVPTXTargetMachine32::anchor() {} diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index a01fa44a9a..2da30f9038 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -58,7 +58,7 @@ static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, return X; } -static MCAsmInfo *createPPCMCAsmInfo(StringRef TT) { +static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { Triple TheTriple(TT); bool isPPC64 = TheTriple.getArch() == Triple::ppc64; @@ -69,9 +69,10 @@ static MCAsmInfo *createPPCMCAsmInfo(StringRef TT) { MAI = new PPCLinuxMCAsmInfo(isPPC64); // Initial state of the frame pointer is R1. - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(isPPC64? PPC::X1 : PPC::R1, 0); - MAI->addInitialFrameState(0, Dst, Src); + unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1; + MCCFIInstruction Inst = + MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(Reg, true), 0); + MAI->addInitialFrameState(Inst); return MAI; } diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 14dc794195..0b099edff4 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -48,6 +48,7 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, // The binutils for the BG/P are too old for CFI. if (Subtarget.isBGP()) setMCUseCFI(false); + initAsmInfo(); } void PPC32TargetMachine::anchor() { } diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index 31fbf32d0c..7175ec941a 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -70,6 +70,7 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, InstrInfo = new SIInstrInfo(*this); TLInfo = new SITargetLowering(*this); } + initAsmInfo(); } AMDGPUTargetMachine::~AMDGPUTargetMachine() { diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index 60bceb708f..3e7a24aecf 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -37,6 +37,7 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, InstrInfo(Subtarget), TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget) { + initAsmInfo(); } namespace { diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index 6844f92ec9..6fe80610dc 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -27,11 +27,13 @@ using namespace llvm; -static MCAsmInfo *createSystemZMCAsmInfo(StringRef TT) { +static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, + StringRef TT) { MCAsmInfo *MAI = new SystemZMCAsmInfo(TT); - MachineLocation FPDst(MachineLocation::VirtualFP); - MachineLocation FPSrc(SystemZ::R15D, -SystemZMC::CFAOffsetFromInitialSP); - MAI->addInitialFrameState(0, FPDst, FPSrc); + MCCFIInstruction Inst = + MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(SystemZ::R15D, true), + SystemZMC::CFAOffsetFromInitialSP); + MAI->addInitialFrameState(Inst); return MAI; } diff --git a/lib/Target/SystemZ/SystemZTargetMachine.cpp b/lib/Target/SystemZ/SystemZTargetMachine.cpp index 8c4c456ef5..17450ee53e 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -33,6 +33,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT, "-f32:32-f64:64-f128:64-a0:8:16-n32:64"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), FrameLowering(*this, Subtarget) { + initAsmInfo(); } namespace { diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index 226ebca8cb..d5aab8e0a2 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -263,7 +263,7 @@ static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) { return X; } -static MCAsmInfo *createX86MCAsmInfo(StringRef TT) { +static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { Triple TheTriple(TT); bool is64Bit = TheTriple.getArch() == Triple::x86_64; @@ -290,14 +290,16 @@ static MCAsmInfo *createX86MCAsmInfo(StringRef TT) { int stackGrowth = is64Bit ? -8 : -4; // Initial state of the frame pointer is esp+stackGrowth. - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth); - MAI->addInitialFrameState(0, Dst, Src); + unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( + 0, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); + MAI->addInitialFrameState(Inst); // Add return address to move list - MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth); - MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP); - MAI->addInitialFrameState(0, CSDst, CSSrc); + unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; + MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( + 0, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); + MAI->addInitialFrameState(Inst2); return MAI; } diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 00fa47f80b..0422a61fb8 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -49,6 +49,7 @@ X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, TLInfo(*this), TSInfo(*this), JITInfo(*this) { + initAsmInfo(); } void X86_64TargetMachine::anchor() { } @@ -69,6 +70,7 @@ X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, TLInfo(*this), TSInfo(*this), JITInfo(*this) { + initAsmInfo(); } /// X86TargetMachine ctor - Create an X86 target. diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index e38da34a81..10bb6dfa92 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -51,13 +51,13 @@ static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, return X; } -static MCAsmInfo *createXCoreMCAsmInfo(StringRef TT) { +static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, + StringRef TT) { MCAsmInfo *MAI = new XCoreMCAsmInfo(TT); // Initial state of the frame pointer is SP. - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(XCore::SP, 0); - MAI->addInitialFrameState(0, Dst, Src); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, XCore::SP, 0); + MAI->addInitialFrameState(Inst); return MAI; } diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index 07e5fff141..3ef1520c71 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -33,6 +33,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this) { + initAsmInfo(); } namespace { diff --git a/tools/llvm-mc/llvm-mc.cpp b/tools/llvm-mc/llvm-mc.cpp index 4b01c33504..289a445089 100644 --- a/tools/llvm-mc/llvm-mc.cpp +++ b/tools/llvm-mc/llvm-mc.cpp @@ -379,12 +379,12 @@ int main(int argc, char **argv) { // it later. SrcMgr.setIncludeDirs(IncludeDirs); - llvm::OwningPtr MAI(TheTarget->createMCAsmInfo(TripleName)); - assert(MAI && "Unable to create target asm info!"); - llvm::OwningPtr MRI(TheTarget->createMCRegInfo(TripleName)); assert(MRI && "Unable to create target register info!"); + llvm::OwningPtr MAI(TheTarget->createMCAsmInfo(*MRI, TripleName)); + assert(MAI && "Unable to create target asm info!"); + // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and // MCObjectFileInfo needs a MCContext reference in order to initialize itself. OwningPtr MOFI(new MCObjectFileInfo()); diff --git a/tools/llvm-objdump/MachODump.cpp b/tools/llvm-objdump/MachODump.cpp index 6797e2dc5b..c7e5cc1ede 100644 --- a/tools/llvm-objdump/MachODump.cpp +++ b/tools/llvm-objdump/MachODump.cpp @@ -251,11 +251,12 @@ static void DisassembleInputMachO2(StringRef Filename, InstrAnalysis(TheTarget->createMCInstrAnalysis(InstrInfo.get())); // Set up disassembler. - OwningPtr AsmInfo(TheTarget->createMCAsmInfo(TripleName)); + OwningPtr MRI(TheTarget->createMCRegInfo(TripleName)); + OwningPtr AsmInfo( + TheTarget->createMCAsmInfo(*MRI, TripleName)); OwningPtr STI(TheTarget->createMCSubtargetInfo(TripleName, "", "")); OwningPtr DisAsm(TheTarget->createMCDisassembler(*STI)); - OwningPtr MRI(TheTarget->createMCRegInfo(TripleName)); int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); OwningPtr IP(TheTarget->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *InstrInfo, diff --git a/tools/llvm-objdump/llvm-objdump.cpp b/tools/llvm-objdump/llvm-objdump.cpp index 247b90f030..053123fd3e 100644 --- a/tools/llvm-objdump/llvm-objdump.cpp +++ b/tools/llvm-objdump/llvm-objdump.cpp @@ -272,8 +272,15 @@ static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) { if (Symbols.empty()) Symbols.push_back(std::make_pair(0, name)); + OwningPtr MRI(TheTarget->createMCRegInfo(TripleName)); + if (!MRI) { + errs() << "error: no register info for target " << TripleName << "\n"; + return; + } + // Set up disassembler. - OwningPtr AsmInfo(TheTarget->createMCAsmInfo(TripleName)); + OwningPtr AsmInfo( + TheTarget->createMCAsmInfo(*MRI, TripleName)); if (!AsmInfo) { errs() << "error: no assembly info for target " << TripleName << "\n"; @@ -295,12 +302,6 @@ static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) { return; } - OwningPtr MRI(TheTarget->createMCRegInfo(TripleName)); - if (!MRI) { - errs() << "error: no register info for target " << TripleName << "\n"; - return; - } - OwningPtr MII(TheTarget->createMCInstrInfo()); if (!MII) { errs() << "error: no instruction info for target " << TripleName << "\n"; -- cgit v1.2.3 From 3778c04b2e3bc879cb7f175ba4d42f23fb9cef76 Mon Sep 17 00:00:00 2001 From: Hao Liu Date: Mon, 13 May 2013 02:07:05 +0000 Subject: Fix PR15950 A bug in DAG Combiner about undef mask git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181682 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 35 +++++++++++++++------- .../ARM/2013-05-13-DAGCombiner-undef-mask.ll | 10 +++++++ 2 files changed, 35 insertions(+), 10 deletions(-) create mode 100644 test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c54dffbb13..076684993a 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9254,19 +9254,34 @@ static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) { for (unsigned I = 0; I != NumConcats; ++I) { // Make sure we're dealing with a copy. unsigned Begin = I * NumElemsPerConcat; - if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0) - return SDValue(); + bool AllUndef = true, NoUndef = true; + for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) { + if (SVN->getMaskElt(J) >= 0) + AllUndef = false; + else + NoUndef = false; + } - for (unsigned J = 1; J != NumElemsPerConcat; ++J) { - if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J)) + if (NoUndef) { + unsigned Begin = I * NumElemsPerConcat; + if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0) return SDValue(); - } - unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat; - if (FirstElt < N0.getNumOperands()) - Ops.push_back(N0.getOperand(FirstElt)); - else - Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands())); + for (unsigned J = 1; J != NumElemsPerConcat; ++J) + if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J)) + return SDValue(); + + unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat; + if (FirstElt < N0.getNumOperands()) + Ops.push_back(N0.getOperand(FirstElt)); + else + Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands())); + + } else if (AllUndef) { + Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType())); + } else { // Mixed with general masks and undefs, can't do optimization. + return SDValue(); + } } return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, Ops.data(), diff --git a/test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll b/test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll new file mode 100644 index 0000000000..8f6709ec5e --- /dev/null +++ b/test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s +target triple = "armv7-none-linux-gnueabi" + +define <3 x i64> @shuffle(i1 %dec1, i1 %dec0, <3 x i64> %b) { +entry: + %.sink = select i1 %dec1, <3 x i64> %b, <3 x i64> zeroinitializer + %.sink15 = select i1 %dec0, <3 x i64> %b, <3 x i64> zeroinitializer + %vecinit7 = shufflevector <3 x i64> %.sink, <3 x i64> %.sink15, <3 x i32> + ret <3 x i64> %vecinit7 +} -- cgit v1.2.3 From 985eb9004c280f4921e4bb450d6b3ee2ce75f634 Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Mon, 13 May 2013 05:13:13 +0000 Subject: SLPVectorizer: Swap LHS and RHS. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181684 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/Vectorize/VecUtils.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/Transforms/Vectorize/VecUtils.cpp b/lib/Transforms/Vectorize/VecUtils.cpp index 1362b784f0..80d61616aa 100644 --- a/lib/Transforms/Vectorize/VecUtils.cpp +++ b/lib/Transforms/Vectorize/VecUtils.cpp @@ -730,15 +730,15 @@ Value *BoUpSLP::vectorizeTree_rec(ArrayRef VL, int VF) { case Instruction::Xor: { ValueList LHSVL, RHSVL; for (int i = 0; i < VF; ++i) { - RHSVL.push_back(cast(VL[i])->getOperand(0)); - LHSVL.push_back(cast(VL[i])->getOperand(1)); + LHSVL.push_back(cast(VL[i])->getOperand(0)); + RHSVL.push_back(cast(VL[i])->getOperand(1)); } - Value *RHS = vectorizeTree_rec(RHSVL, VF); Value *LHS = vectorizeTree_rec(LHSVL, VF); + Value *RHS = vectorizeTree_rec(RHSVL, VF); IRBuilder<> Builder(GetLastInstr(VL, VF)); BinaryOperator *BinOp = cast(VL0); - Value *V = Builder.CreateBinOp(BinOp->getOpcode(), RHS,LHS); + Value *V = Builder.CreateBinOp(BinOp->getOpcode(), LHS,RHS); for (int i = 0; i < VF; ++i) VectorizedValues[VL[i]] = V; -- cgit v1.2.3 From b99052ce4a75a3eac638afcd5171903514aa28e9 Mon Sep 17 00:00:00 2001 From: Duncan Sands Date: Mon, 13 May 2013 07:50:47 +0000 Subject: Suppress GCC compiler warnings in release builds about variables that are only read in asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181689 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonNewValueJump.cpp | 1 + lib/Target/X86/AsmParser/X86AsmParser.cpp | 1 + lib/Transforms/Vectorize/VecUtils.cpp | 1 + 3 files changed, 3 insertions(+) diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp index 05e696865f..f7c4513213 100644 --- a/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -631,6 +631,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { .addMBB(jmpTarget); assert(NewMI && "New Value Jump Instruction Not created!"); + (void)NewMI; if (cmpInstr->getOperand(0).isReg() && cmpInstr->getOperand(0).isKill()) cmpInstr->getOperand(0).setIsKill(false); diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 019a670083..263eb5ed9c 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -1196,6 +1196,7 @@ RewriteIntelBracExpression(SmallVectorImpl *AsmRewrites, } } assert (Found && "Unable to rewrite ImmDisp."); + (void)Found; } else { // We have a symbolic and an immediate displacement, but no displacement // before the bracketed expression. Put the immediate displacement diff --git a/lib/Transforms/Vectorize/VecUtils.cpp b/lib/Transforms/Vectorize/VecUtils.cpp index 80d61616aa..50d2af0f65 100644 --- a/lib/Transforms/Vectorize/VecUtils.cpp +++ b/lib/Transforms/Vectorize/VecUtils.cpp @@ -639,6 +639,7 @@ Value *BoUpSLP::vectorizeTree(ArrayRef VL, int VF) { Replaced = true; } assert(Replaced && "Must replace at least one outside user"); + (void)Replaced; } // We moved some instructions around. We have to number them again -- cgit v1.2.3 From d26c93d3a8a484c5b42f06163ae5de787f0ac276 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Mon, 13 May 2013 10:21:19 +0000 Subject: Correctly preserve the input chain for potential tailcall nodes whose return values are bitcasts. The chain had previously been being clobbered with the entry node to the dag, which sometimes caused other code in the function to be erroneously deleted when tailcall optimization kicked in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181696 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 2 +- test/CodeGen/ARM/call-tc.ll | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index fd77732364..008edbe4a7 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2147,7 +2147,7 @@ bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { Copy = *Copy->use_begin(); if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0)) return false; - Chain = Copy->getOperand(0); + TCChain = Copy->getOperand(0); } else { return false; } diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index 58fbbda0f6..c7e17ea353 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -162,3 +162,20 @@ define i32 @t9() nounwind { declare %class.MutexLock* @_ZN9MutexLockC1Ev(%class.MutexLock*) unnamed_addr nounwind align 2 declare %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock*) unnamed_addr nounwind align 2 + +; rdar://13827621 +; Correctly preserve the input chain for the tailcall node in the bitcast case, +; otherwise the call to floorf is lost. +define float @libcall_tc_test2(float* nocapture %a, float %b) { +; CHECKT2D: libcall_tc_test2: +; CHECKT2D: blx _floorf +; CHECKT2D: b.w _truncf + %1 = load float* %a, align 4 + %call = tail call float @floorf(float %1) + store float %call, float* %a, align 4 + %call1 = tail call float @truncf(float %b) + ret float %call1 +} + +declare float @floorf(float) readnone +declare float @truncf(float) readnone -- cgit v1.2.3 From f86e436fb95670ed110818fefa403f21ae104639 Mon Sep 17 00:00:00 2001 From: Mihai Popa Date: Mon, 13 May 2013 14:10:04 +0000 Subject: The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 1 + lib/Target/ARM/ARMInstrInfo.td | 10 ++++----- lib/Target/ARM/ARMRegisterInfo.td | 25 ++++++++++++++++------ lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 18 ++++++++++++++++ test/MC/ARM/basic-arm-instructions.s | 14 +++++++++--- .../MC/Disassembler/ARM/basic-arm-instructions.txt | 4 ++++ 6 files changed, 58 insertions(+), 14 deletions(-) diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index b0d34a76b0..4de5b4f41c 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -94,6 +94,7 @@ getReservedRegs(const MachineFunction &MF) const { Reserved.set(ARM::SP); Reserved.set(ARM::PC); Reserved.set(ARM::FPSCR); + Reserved.set(ARM::APSR_NZCV); if (TFI->hasFP(MF)) Reserved.set(FramePtr); if (hasBasePointer(MF)) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 1bd174e341..89f92a589d 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4636,11 +4636,11 @@ def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)>; def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, - (outs GPR:$Rt), + (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), []>; def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", - (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, + (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)>; def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), @@ -4650,7 +4650,7 @@ class MovRCopro2 pattern> : ABXI<0b1110, oops, iops, NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { - let Inst{31-28} = 0b1111; + let Inst{31-24} = 0b11111110; let Inst{20} = direction; let Inst{4} = 1; @@ -4679,11 +4679,11 @@ def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm", (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0)>; def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, - (outs GPR:$Rt), + (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), []>; def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm", - (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, + (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0)>; def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index b0f576bc2b..85743d8d5a 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -157,12 +157,15 @@ def Q15 : ARMReg<15, "q15", [D30, D31]>; // Current Program Status Register. // We model fpscr with two registers: FPSCR models the control bits and will be -// reserved. FPSCR_NZCV models the flag bits and will be unreserved. -def CPSR : ARMReg<0, "cpsr">; -def APSR : ARMReg<1, "apsr">; -def SPSR : ARMReg<2, "spsr">; -def FPSCR : ARMReg<3, "fpscr">; -def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> { +// reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV +// models the APSR when it's accessed by some special instructions. In such cases +// it has the same encoding as PC. +def CPSR : ARMReg<0, "cpsr">; +def APSR : ARMReg<1, "apsr">; +def APSR_NZCV : ARMReg<15, "apsr_nzcv">; +def SPSR : ARMReg<2, "spsr">; +def FPSCR : ARMReg<3, "fpscr">; +def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> { let Aliases = [FPSCR]; } def ITSTATE : ARMReg<4, "itstate">; @@ -207,6 +210,16 @@ def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { }]; } +// GPRs without the PC but with APSR. Some instructions allow accessing the +// APSR, while actually encoding PC in the register field. This is usefull +// for assembly and disassembly only. +def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add GPR, APSR_NZCV)> { + let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; + let AltOrderSelect = [{ + return 1 + MF.getTarget().getSubtarget().isThumb1Only(); + }]; +} + // GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the // implied SP argument list. // FIXME: It would be better to not use this at all and refactor the diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index ac937f3534..d2896377cc 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -156,6 +156,9 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, + unsigned RegNo, uint64_t Address, + const void *Decoder); static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, @@ -920,6 +923,21 @@ DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, return S; } +static DecodeStatus +DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + if (RegNo == 15) + { + Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); + return MCDisassembler::Success; + } + + Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 71b5b5da09..5227bdd239 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1062,10 +1062,18 @@ Lforward: @ MRC/MRC2 @------------------------------------------------------------------------------ mrc p14, #0, r1, c1, c2, #4 + mrc p15, #7, apsr_nzcv, c15, c6, #6 + mrc p15, #7, pc, c15, c6, #6 mrc2 p14, #0, r1, c1, c2, #4 - -@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] -@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] + mrc2 p10, #7, apsr_nzcv, c15, c0, #1 + mrc2 p10, #7, pc, c15, c0, #1 + +@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] +@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee] +@ CHECK: mrc p15, #7, pc, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee] +@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] +@ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe] +@ CHECK: mrc2 p10, #7, pc, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe] @------------------------------------------------------------------------------ @ MRRC/MRRC2 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index 9f63e1e914..c92322e8d7 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -757,10 +757,14 @@ # MRC/MRC2 #------------------------------------------------------------------------------ # CHECK: mrc p14, #0, r1, c1, c2, #4 +# CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 # CHECK: mrc2 p14, #0, r1, c1, c2, #4 +# CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 0x92 0x1e 0x11 0xee +0xd6 0xff 0xff 0xee 0x92 0x1e 0x11 0xfe +0x30 0xf9 0xff 0xfe #------------------------------------------------------------------------------ # MRRC/MRRC2 -- cgit v1.2.3 From 6eb70ac034a4b23a129fa674dd9852b6d3a615c8 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Mon, 13 May 2013 14:34:48 +0000 Subject: Remove unused fields and arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181706 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp | 2 +- lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h | 4 +--- lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp | 13 ++++--------- 3 files changed, 6 insertions(+), 13 deletions(-) diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp index 45d009c2a0..6f66aa898a 100644 --- a/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ b/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -78,7 +78,7 @@ static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); } else { - return createR600MCCodeEmitter(MCII, MRI, STI, Ctx); + return createR600MCCodeEmitter(MCII, MRI); } } diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h b/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h index 09d0d5b61c..95c572c21b 100644 --- a/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h +++ b/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -32,9 +32,7 @@ class raw_ostream; extern Target TheAMDGPUTarget; MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII, - const MCRegisterInfo &MRI, - const MCSubtargetInfo &STI, - MCContext &Ctx); + const MCRegisterInfo &MRI); MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp index 271a974734..3404844435 100644 --- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp @@ -35,14 +35,11 @@ class R600MCCodeEmitter : public AMDGPUMCCodeEmitter { void operator=(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION; const MCInstrInfo &MCII; const MCRegisterInfo &MRI; - const MCSubtargetInfo &STI; - MCContext &Ctx; public: - R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri, - const MCSubtargetInfo &sti, MCContext &ctx) - : MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { } + R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri) + : MCII(mcii), MRI(mri) { } /// \brief Encode the instruction and write it to the OS. virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, @@ -98,10 +95,8 @@ enum TextureTypes { }; MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, - const MCRegisterInfo &MRI, - const MCSubtargetInfo &STI, - MCContext &Ctx) { - return new R600MCCodeEmitter(MCII, MRI, STI, Ctx); + const MCRegisterInfo &MRI) { + return new R600MCCodeEmitter(MCII, MRI); } void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, -- cgit v1.2.3 From 6daba286836e6fb2351e7ebc248e18a5c80e8a31 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Mon, 13 May 2013 17:43:19 +0000 Subject: [mips] Rename functions. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16InstrInfo.cpp | 4 ++-- lib/Target/Mips/Mips16InstrInfo.h | 4 ++-- lib/Target/Mips/MipsInstrInfo.cpp | 10 +++++----- lib/Target/Mips/MipsInstrInfo.h | 4 ++-- lib/Target/Mips/MipsLongBranch.cpp | 2 +- lib/Target/Mips/MipsSEInstrInfo.cpp | 22 +++++++++++----------- lib/Target/Mips/MipsSEInstrInfo.h | 12 ++++++------ 7 files changed, 29 insertions(+), 29 deletions(-) diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index 17dd2c0796..ab9e62703b 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -145,7 +145,7 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { /// GetOppositeBranchOpc - Return the inverse of the specified /// opcode, e.g. turning BEQ to BNE. -unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const { +unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const { switch (Opc) { default: llvm_unreachable("Illegal opcode!"); case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16; @@ -380,7 +380,7 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg, return Reg; } -unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const { +unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const { return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 || Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 || Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 || diff --git a/lib/Target/Mips/Mips16InstrInfo.h b/lib/Target/Mips/Mips16InstrInfo.h index a77a9043bb..a3bd31e94f 100644 --- a/lib/Target/Mips/Mips16InstrInfo.h +++ b/lib/Target/Mips/Mips16InstrInfo.h @@ -64,7 +64,7 @@ public: virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; - virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; + virtual unsigned getOppositeBranchOpc(unsigned Opc) const; // Adjust SP by FrameSize bytes. Save RA, S0, S1 void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, @@ -102,7 +102,7 @@ public: (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const; private: - virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; + virtual unsigned getAnalyzableBrOpc(unsigned Opc) const; void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opc) const; diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index ad92d41209..336b62dbcd 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -77,7 +77,7 @@ MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, MachineBasicBlock *&BB, SmallVectorImpl &Cond) const { - assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch"); + assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch"); int NumOp = Inst->getNumExplicitOperands(); // for both int and fp branches, the last explicit operand is the @@ -167,7 +167,7 @@ RemoveBranch(MachineBasicBlock &MBB) const // Up to 2 branches are removed. // Note that indirect branches are not removed. for(removed = 0; I != REnd && removed < 2; ++I, ++removed) - if (!GetAnalyzableBrOpc(I->getOpcode())) + if (!getAnalyzableBrOpc(I->getOpcode())) break; MBB.erase(I.base(), FirstBr.base()); @@ -182,7 +182,7 @@ ReverseBranchCondition(SmallVectorImpl &Cond) const { assert( (Cond.size() && Cond.size() <= 3) && "Invalid Mips branch condition!"); - Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm())); + Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); return false; } @@ -210,7 +210,7 @@ AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, BranchInstrs.push_back(LastInst); // Not an analyzable branch (e.g., indirect jump). - if (!GetAnalyzableBrOpc(LastOpc)) + if (!getAnalyzableBrOpc(LastOpc)) return LastInst->isIndirectBranch() ? BT_Indirect : BT_None; // Get the second to last instruction in the block. @@ -219,7 +219,7 @@ AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, if (++I != REnd) { SecondLastInst = &*I; - SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode()); + SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode()); // Not an analyzable branch (must be an indirect jump). if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc) diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 8c05d97bea..6a57736aad 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -81,7 +81,7 @@ public: /// virtual const MipsRegisterInfo &getRegisterInfo() const = 0; - virtual unsigned GetOppositeBranchOpc(unsigned Opc) const = 0; + virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; /// Return the number of bytes of code the specified instruction may be. unsigned GetInstSizeInBytes(const MachineInstr *MI) const; @@ -123,7 +123,7 @@ protected: unsigned Flag) const; private: - virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const = 0; + virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, MachineBasicBlock *&BB, diff --git a/lib/Target/Mips/MipsLongBranch.cpp b/lib/Target/Mips/MipsLongBranch.cpp index bf5ad37031..daabf3d25a 100644 --- a/lib/Target/Mips/MipsLongBranch.cpp +++ b/lib/Target/Mips/MipsLongBranch.cpp @@ -217,7 +217,7 @@ int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) { // MachineBasicBlock operand MBBOpnd. void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL, MachineBasicBlock *MBBOpnd) { - unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode()); + unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); const MCInstrDesc &NewDesc = TII->get(NewOpc); MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index a0768e51c0..4183a72940 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -245,17 +245,17 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { default: return false; case Mips::RetRA: - ExpandRetRA(MBB, MI, Mips::RET); + expandRetRA(MBB, MI, Mips::RET); break; case Mips::BuildPairF64: - ExpandBuildPairF64(MBB, MI); + expandBuildPairF64(MBB, MI); break; case Mips::ExtractElementF64: - ExpandExtractElementF64(MBB, MI); + expandExtractElementF64(MBB, MI); break; case Mips::MIPSeh_return32: case Mips::MIPSeh_return64: - ExpandEhReturn(MBB, MI); + expandEhReturn(MBB, MI); break; } @@ -263,9 +263,9 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { return true; } -/// GetOppositeBranchOpc - Return the inverse of the specified +/// getOppositeBranchOpc - Return the inverse of the specified /// opcode, e.g. turning BEQ to BNE. -unsigned MipsSEInstrInfo::GetOppositeBranchOpc(unsigned Opc) const { +unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { switch (Opc) { default: llvm_unreachable("Illegal opcode!"); case Mips::BEQ: return Mips::BNE; @@ -346,7 +346,7 @@ MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, return Reg; } -unsigned MipsSEInstrInfo::GetAnalyzableBrOpc(unsigned Opc) const { +unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || @@ -356,13 +356,13 @@ unsigned MipsSEInstrInfo::GetAnalyzableBrOpc(unsigned Opc) const { Opc : 0; } -void MipsSEInstrInfo::ExpandRetRA(MachineBasicBlock &MBB, +void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opc) const { BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA); } -void MipsSEInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB, +void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); @@ -377,7 +377,7 @@ void MipsSEInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB, BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg); } -void MipsSEInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB, +void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { unsigned DstReg = I->getOperand(0).getReg(); unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); @@ -393,7 +393,7 @@ void MipsSEInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB, .addReg(HiReg); } -void MipsSEInstrInfo::ExpandEhReturn(MachineBasicBlock &MBB, +void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { // This pseudo instruction is generated as part of the lowering of // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and diff --git a/lib/Target/Mips/MipsSEInstrInfo.h b/lib/Target/Mips/MipsSEInstrInfo.h index 0bf7876f0f..821d751c6d 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.h +++ b/lib/Target/Mips/MipsSEInstrInfo.h @@ -65,7 +65,7 @@ public: virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; - virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; + virtual unsigned getOppositeBranchOpc(unsigned Opc) const; /// Adjust SP by Amount bytes. void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, @@ -79,15 +79,15 @@ public: unsigned *NewImm) const; private: - virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; + virtual unsigned getAnalyzableBrOpc(unsigned Opc) const; - void ExpandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opc) const; - void ExpandExtractElementF64(MachineBasicBlock &MBB, + void expandExtractElementF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; - void ExpandBuildPairF64(MachineBasicBlock &MBB, + void expandBuildPairF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; - void ExpandEhReturn(MachineBasicBlock &MBB, + void expandEhReturn(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; }; -- cgit v1.2.3 From 151687cb8c4fc65fefcd8964a0c3d77680e90a5c Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Mon, 13 May 2013 17:57:42 +0000 Subject: [mips] Define a helper function which creates an instruction with the same operands as the prototype instruction but with a different opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181714 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsInstrInfo.cpp | 13 +++++++++++++ lib/Target/Mips/MipsInstrInfo.h | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 336b62dbcd..3144daebd7 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -282,3 +282,16 @@ unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { } } } + +MachineInstrBuilder +MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, + MachineBasicBlock::iterator I) const { + MachineInstrBuilder MIB; + MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); + + for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) + MIB.addOperand(I->getOperand(J)); + + MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end()); + return MIB; +} diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 6a57736aad..0f075ec6d0 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -17,6 +17,7 @@ #include "Mips.h" #include "MipsAnalyzeImmediate.h" #include "MipsRegisterInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetInstrInfo.h" @@ -116,6 +117,11 @@ public: const TargetRegisterInfo *TRI, int64_t Offset) const = 0; + /// Create an instruction which has the same operands and memory operands + /// as MI but has a new opcode. + MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, + MachineBasicBlock::iterator I) const; + protected: bool isZeroImm(const MachineOperand &op) const; -- cgit v1.2.3 From 4b6b53b0cec4fcf4d570daed3be41d6147d05224 Mon Sep 17 00:00:00 2001 From: Shuxin Yang Date: Mon, 13 May 2013 18:03:12 +0000 Subject: Fix a bug that APFloat::fusedMultiplyAdd() mistakenly evaluate "14.5f * -14.5f + 225.0f" to 225.0f. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181715 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/APFloat.cpp | 29 +++++++++++++++++++++++++++-- unittests/ADT/APFloatTest.cpp | 23 +++++++++++++++++++++++ 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/lib/Support/APFloat.cpp b/lib/Support/APFloat.cpp index 6182e34150..57e60dac45 100644 --- a/lib/Support/APFloat.cpp +++ b/lib/Support/APFloat.cpp @@ -872,7 +872,21 @@ APFloat::multiplySignificand(const APFloat &rhs, const APFloat *addend) omsb = APInt::tcMSB(fullSignificand, newPartsCount) + 1; exponent += rhs.exponent; + // Assume the operands involved in the multiplication are single-precision + // FP, and the two multiplicants are: + // *this = a23 . a22 ... a0 * 2^e1 + // rhs = b23 . b22 ... b0 * 2^e2 + // the result of multiplication is: + // *this = c47 c46 . c45 ... c0 * 2^(e1+e2) + // Note that there are two significant bits at the left-hand side of the + // radix point. Move the radix point toward left by one bit, and adjust + // exponent accordingly. + exponent += 1; + if (addend) { + // The intermediate result of the multiplication has "2 * precision" + // signicant bit; adjust the addend to be consistent with mul result. + // Significand savedSignificand = significand; const fltSemantics *savedSemantics = semantics; fltSemantics extendedSemantics; @@ -880,8 +894,9 @@ APFloat::multiplySignificand(const APFloat &rhs, const APFloat *addend) unsigned int extendedPrecision; /* Normalize our MSB. */ - extendedPrecision = precision + precision - 1; + extendedPrecision = 2 * precision; if (omsb != extendedPrecision) { + assert(extendedPrecision > omsb); APInt::tcShiftLeft(fullSignificand, newPartsCount, extendedPrecision - omsb); exponent -= extendedPrecision - omsb; @@ -912,8 +927,18 @@ APFloat::multiplySignificand(const APFloat &rhs, const APFloat *addend) omsb = APInt::tcMSB(fullSignificand, newPartsCount) + 1; } - exponent -= (precision - 1); + // Convert the result having "2 * precision" significant-bits back to the one + // having "precision" significant-bits. First, move the radix point from + // poision "2*precision - 1" to "precision - 1". The exponent need to be + // adjusted by "2*precision - 1" - "precision - 1" = "precision". + exponent -= precision; + // In case MSB resides at the left-hand side of radix point, shift the + // mantissa right by some amount to make sure the MSB reside right before + // the radix point (i.e. "MSB . rest-significant-bits"). + // + // Note that the result is not normalized when "omsb < precision". So, the + // caller needs to call APFloat::normalize() if normalized value is expected. if (omsb > precision) { unsigned int bits, significantParts; lostFraction lf; diff --git a/unittests/ADT/APFloatTest.cpp b/unittests/ADT/APFloatTest.cpp index 278983565c..099f6db7cb 100644 --- a/unittests/ADT/APFloatTest.cpp +++ b/unittests/ADT/APFloatTest.cpp @@ -33,6 +33,29 @@ static std::string convertToString(double d, unsigned Prec, unsigned Pad) { namespace { +TEST(APFloatTest, FMA) { + APFloat::roundingMode rdmd = APFloat::rmNearestTiesToEven; + + { + APFloat f1(14.5f); + APFloat f2(-14.5f); + APFloat f3(225.0f); + f1.fusedMultiplyAdd(f2, f3, APFloat::rmNearestTiesToEven); + EXPECT_EQ(14.75f, f1.convertToFloat()); + } + + { + APFloat Val2(2.0f); + APFloat f1((float)1.17549435e-38F); + APFloat f2((float)1.17549435e-38F); + f1.divide(Val2, rdmd); + f2.divide(Val2, rdmd); + APFloat f3(12.0f); + f1.fusedMultiplyAdd(f2, f3, APFloat::rmNearestTiesToEven); + EXPECT_EQ(12.0f, f1.convertToFloat()); + } +} + TEST(APFloatTest, Denormal) { APFloat::roundingMode rdmd = APFloat::rmNearestTiesToEven; -- cgit v1.2.3 From 42f562a1694d24b41f36bbb4d4a086a2a470c625 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Mon, 13 May 2013 18:23:35 +0000 Subject: [mips] Add option -mno-ldc1-sdc1. This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsInstrFPU.td | 14 ++++++--- lib/Target/Mips/MipsSEInstrInfo.cpp | 62 +++++++++++++++++++++++++++++++++++++ lib/Target/Mips/MipsSEInstrInfo.h | 3 ++ test/CodeGen/Mips/mno-ldc1-sdc1.ll | 45 +++++++++++++++++++++++++++ 4 files changed, 120 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/Mips/mno-ldc1-sdc1.ll diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 6b23057c9c..5fa79cb159 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -154,6 +154,7 @@ class LW_FT { let DecoderMethod = "DecodeFMem"; + let mayLoad = 1; } class SW_FT { let DecoderMethod = "DecodeFMem"; + let mayStore = 1; } class MADDS_FT, LW_FM<0x35>; - def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem, store>, LW_FM<0x3d>; + let isPseudo = 1, isCodeGenOnly = 1 in { + def PseudoLDC1 : LW_FT<"", AFGR64, IILoad, mem, load>; + def PseudoSDC1 : SW_FT<"", AFGR64, IIStore, mem, store>; + } + def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem>, LW_FM<0x35>; + def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem>, LW_FM<0x3d>; } // Indexed loads and stores. @@ -523,7 +529,7 @@ let AddedComplexity = 40 in { } let Predicates = [NotN64, NotMips64, HasStdEnc] in { - def : LoadRegImmPat; - def : StoreRegImmPat; + def : LoadRegImmPat; + def : StoreRegImmPat; } } diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index 4183a72940..12ed1bc186 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -18,11 +18,17 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; +static cl::opt NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), + cl::desc("Expand double precision loads and " + "stores to their single precision " + "counterparts.")); + MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm) : MipsInstrInfo(tm, tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J), @@ -253,6 +259,12 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { case Mips::ExtractElementF64: expandExtractElementF64(MBB, MI); break; + case Mips::PseudoLDC1: + expandDPLoadStore(MBB, MI, Mips::LDC1, Mips::LWC1); + break; + case Mips::PseudoSDC1: + expandDPLoadStore(MBB, MI, Mips::SDC1, Mips::SWC1); + break; case Mips::MIPSeh_return32: case Mips::MIPSeh_return64: expandEhReturn(MBB, MI); @@ -393,6 +405,56 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, .addReg(HiReg); } +/// Add 4 to the displacement of operand MO. +static void fixDisp(MachineOperand &MO) { + switch (MO.getType()) { + default: + llvm_unreachable("Unhandled operand type."); + case MachineOperand::MO_Immediate: + MO.setImm(MO.getImm() + 4); + break; + case MachineOperand::MO_GlobalAddress: + case MachineOperand::MO_ConstantPoolIndex: + case MachineOperand::MO_BlockAddress: + case MachineOperand::MO_TargetIndex: + case MachineOperand::MO_ExternalSymbol: + MO.setOffset(MO.getOffset() + 4); + break; + } +} + +void MipsSEInstrInfo::expandDPLoadStore(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned OpcD, unsigned OpcS) const { + // If NoDPLoadStore is false, just change the opcode. + if (!NoDPLoadStore) { + genInstrWithNewOpc(OpcD, I); + return; + } + + // Expand a double precision FP load or store to two single precision + // instructions. + + const TargetRegisterInfo &TRI = getRegisterInfo(); + const MachineOperand &ValReg = I->getOperand(0); + unsigned LoReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpeven); + unsigned HiReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpodd); + + if (!TM.getSubtarget().isLittle()) + std::swap(LoReg, HiReg); + + // Create an instruction which loads from or stores to the lower memory + // address. + MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I); + MIB->getOperand(0).setReg(LoReg); + + // Create an instruction which loads from or stores to the higher memory + // address. + MIB = genInstrWithNewOpc(OpcS, I); + MIB->getOperand(0).setReg(HiReg); + fixDisp(MIB->getOperand(2)); +} + void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { // This pseudo instruction is generated as part of the lowering of diff --git a/lib/Target/Mips/MipsSEInstrInfo.h b/lib/Target/Mips/MipsSEInstrInfo.h index 821d751c6d..416fff8a60 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.h +++ b/lib/Target/Mips/MipsSEInstrInfo.h @@ -87,6 +87,9 @@ private: MachineBasicBlock::iterator I) const; void expandBuildPairF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; + void expandDPLoadStore(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, unsigned OpcD, + unsigned OpcS) const; void expandEhReturn(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; }; diff --git a/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/test/CodeGen/Mips/mno-ldc1-sdc1.ll new file mode 100644 index 0000000000..eae9a2216a --- /dev/null +++ b/test/CodeGen/Mips/mno-ldc1-sdc1.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 < %s | \ +; RUN: FileCheck %s -check-prefix=LE-PIC +; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 < %s | \ +; RUN: FileCheck %s -check-prefix=LE-STATIC +; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 < %s | \ +; RUN: FileCheck %s -check-prefix=BE-PIC +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK-LDC1-SDC1 + +@g0 = common global double 0.000000e+00, align 8 + +; LE-PIC: test_ldc1: +; LE-PIC: lwc1 $f0, 0(${{[0-9]+}}) +; LE-PIC: lwc1 $f1, 4(${{[0-9]+}}) +; LE-STATIC: test_ldc1: +; LE-STATIC: lwc1 $f0, %lo(g0)(${{[0-9]+}}) +; LE-STATIC: lwc1 $f1, %lo(g0+4)(${{[0-9]+}}) +; BE-PIC: test_ldc1: +; BE-PIC: lwc1 $f1, 0(${{[0-9]+}}) +; BE-PIC: lwc1 $f0, 4(${{[0-9]+}}) +; CHECK-LDC1-SDC1: test_ldc1: +; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}} + +define double @test_ldc1() { +entry: + %0 = load double* @g0, align 8 + ret double %0 +} + +; LE-PIC: test_sdc1: +; LE-PIC: swc1 $f12, 0(${{[0-9]+}}) +; LE-PIC: swc1 $f13, 4(${{[0-9]+}}) +; LE-STATIC: test_sdc1: +; LE-STATIC: swc1 $f12, %lo(g0)(${{[0-9]+}}) +; LE-STATIC: swc1 $f13, %lo(g0+4)(${{[0-9]+}}) +; BE-PIC: test_sdc1: +; BE-PIC: swc1 $f13, 0(${{[0-9]+}}) +; BE-PIC: swc1 $f12, 4(${{[0-9]+}}) +; CHECK-LDC1-SDC1: test_sdc1: +; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}} + +define void @test_sdc1(double %a) { +entry: + store double %a, double* @g0, align 8 + ret void +} -- cgit v1.2.3 From fa709768b91df14bb7b5606700d92c3c10aba625 Mon Sep 17 00:00:00 2001 From: Michael Gottesman Date: Mon, 13 May 2013 18:29:07 +0000 Subject: [objc-arc] Move the before optimization statistics gathering phase out of OptimizeIndividualCalls. This makes the statistics gathering completely independent of the actual optimization occuring, preventing any sort of bleeding over from occuring. Additionally, it simplifies a switch statement in the non-statistic gathering case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181719 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/ObjCARC/ObjCARCOpts.cpp | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp index 43e2e20035..6d2d630bb6 100644 --- a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp +++ b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp @@ -1440,11 +1440,7 @@ void ObjCARCOpt::OptimizeIndividualCalls(Function &F) { case IC_RetainBlock: // If we strength reduce an objc_retainBlock to an objc_retain, continue // onto the objc_retain peephole optimizations. Otherwise break. - if (!OptimizeRetainBlockCall(F, Inst, Class)) - break; - // FALLTHROUGH - case IC_Retain: - ++NumRetainsBeforeOpt; + OptimizeRetainBlockCall(F, Inst, Class); break; case IC_RetainRV: if (OptimizeRetainRVCall(F, Inst)) @@ -1453,9 +1449,6 @@ void ObjCARCOpt::OptimizeIndividualCalls(Function &F) { case IC_AutoreleaseRV: OptimizeAutoreleaseRVCall(F, Inst, Class); break; - case IC_Release: - ++NumReleasesBeforeOpt; - break; } // objc_autorelease(x) -> objc_release(x) if x is otherwise unused. @@ -3050,6 +3043,12 @@ bool ObjCARCOpt::runOnFunction(Function &F) { PA.setAA(&getAnalysis()); +#ifndef NDEBUG + if (AreStatisticsEnabled()) { + GatherStatistics(F, false); + } +#endif + // This pass performs several distinct transformations. As a compile-time aid // when compiling code that isn't ObjC, skip these if the relevant ObjC // library functions aren't declared. -- cgit v1.2.3 From a753ff72b2dfcd9c09451a124373e0a8ed1a1d47 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Mon, 13 May 2013 19:02:31 +0000 Subject: Remove redundant variable introduced by r181682. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181721 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 076684993a..a8621a89a8 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9263,7 +9263,6 @@ static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) { } if (NoUndef) { - unsigned Begin = I * NumElemsPerConcat; if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0) return SDValue(); -- cgit v1.2.3 From 240b9b6078cdf8048945107b4ff7d517729dab96 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Mon, 13 May 2013 19:34:37 +0000 Subject: PPC64: Constant initializers with dynamic relocations go in .data.rel.ro. This fixes warning messages observed in the oggenc application test in projects/test-suite. Special handling is needed for the 64-bit PowerPC SVR4 ABI when a constant is initialized with a pointer to a function in a shared library. Because a function address is implemented as the address of a function descriptor, the use of copy relocations can lead to problems with initialization. GNU ld therefore replaces copy relocations with dynamic relocations to be resolved by the dynamic linker. This means the constant cannot reside in the read-only data section, but instead belongs in .data.rel.ro, which is designed for constants containing dynamic relocations. The implementation creates a class PPC64LinuxTargetObjectFile inheriting from TargetLoweringObjectFileELF, which behaves like its parent except to place constants of this sort into .data.rel.ro. The test case is reduced from the oggenc application. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181723 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/CMakeLists.txt | 1 + lib/Target/PowerPC/PPCISelLowering.cpp | 4 +++ lib/Target/PowerPC/PPCTargetObjectFile.cpp | 57 ++++++++++++++++++++++++++++++ lib/Target/PowerPC/PPCTargetObjectFile.h | 32 +++++++++++++++++ test/CodeGen/PowerPC/addrfuncstr.ll | 27 ++++++++++++++ 5 files changed, 121 insertions(+) create mode 100644 lib/Target/PowerPC/PPCTargetObjectFile.cpp create mode 100644 lib/Target/PowerPC/PPCTargetObjectFile.h create mode 100644 test/CodeGen/PowerPC/addrfuncstr.ll diff --git a/lib/Target/PowerPC/CMakeLists.txt b/lib/Target/PowerPC/CMakeLists.txt index 71803cdac9..e5c5204708 100644 --- a/lib/Target/PowerPC/CMakeLists.txt +++ b/lib/Target/PowerPC/CMakeLists.txt @@ -27,6 +27,7 @@ add_llvm_target(PowerPCCodeGen PPCRegisterInfo.cpp PPCSubtarget.cpp PPCTargetMachine.cpp + PPCTargetObjectFile.cpp PPCTargetTransformInfo.cpp PPCSelectionDAGInfo.cpp ) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 3819bc8f15..f6972bdd6c 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -16,6 +16,7 @@ #include "PPCMachineFunctionInfo.h" #include "PPCPerfectShuffle.h" #include "PPCTargetMachine.h" +#include "PPCTargetObjectFile.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -64,6 +65,9 @@ static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { if (TM.getSubtargetImpl()->isDarwin()) return new TargetLoweringObjectFileMachO(); + if (TM.getSubtargetImpl()->isSVR4ABI()) + return new PPC64LinuxTargetObjectFile(); + return new TargetLoweringObjectFileELF(); } diff --git a/lib/Target/PowerPC/PPCTargetObjectFile.cpp b/lib/Target/PowerPC/PPCTargetObjectFile.cpp new file mode 100644 index 0000000000..b374b5992a --- /dev/null +++ b/lib/Target/PowerPC/PPCTargetObjectFile.cpp @@ -0,0 +1,57 @@ +//===-- PPCTargetObjectFile.cpp - PPC Object Info -------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "PPCTargetObjectFile.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/Target/Mangler.h" + +using namespace llvm; + +void +PPC64LinuxTargetObjectFile:: +Initialize(MCContext &Ctx, const TargetMachine &TM) { + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + InitializeELF(TM.Options.UseInitArray); +} + +const MCSection * PPC64LinuxTargetObjectFile:: +SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, + Mangler *Mang, const TargetMachine &TM) const { + + const MCSection *DefaultSection = + TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang, TM); + + if (DefaultSection != ReadOnlySection) + return DefaultSection; + + // Here override isReadOnly() to isReadOnlyWithRel() for PPC64 SVR4 ABI + // when we have a constant that contains global relocations. This is + // necessary because of this ABI's handling of pointers to functions in + // a shared library. The address of a function is actually the address + // of a function descriptor, which resides in the .opd section. Generated + // code uses the descriptor directly rather than going via the GOT as some + // other ABIs do, which means that initialized function pointers must + // reference the descriptor. The linker must convert copy relocs of + // pointers to functions in shared libraries into dynamic relocations, + // because of an ordering problem with initialization of copy relocs and + // PLT entries. The dynamic relocation will be initialized by the dynamic + // linker, so we must use the DataRelRO section instead of ReadOnlySection. + // For more information, see the description of ELIMINATE_COPY_RELOCS in + // GNU ld. + const GlobalVariable *GVar = dyn_cast(GV); + + if (GVar && GVar->isConstant() && + (GVar->getInitializer()->getRelocationInfo() == + Constant::GlobalRelocations)) + return DataRelROSection; + + return DefaultSection; +} diff --git a/lib/Target/PowerPC/PPCTargetObjectFile.h b/lib/Target/PowerPC/PPCTargetObjectFile.h new file mode 100644 index 0000000000..9203e23574 --- /dev/null +++ b/lib/Target/PowerPC/PPCTargetObjectFile.h @@ -0,0 +1,32 @@ +//===-- PPCTargetObjectFile.h - PPC Object Info -----------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TARGET_PPC_TARGETOBJECTFILE_H +#define LLVM_TARGET_PPC_TARGETOBJECTFILE_H + +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/Target/TargetLoweringObjectFile.h" +#include "llvm/Target/TargetMachine.h" + +namespace llvm { + + /// PPC64LinuxTargetObjectFile - This implementation is used for + /// 64-bit PowerPC Linux. + class PPC64LinuxTargetObjectFile : public TargetLoweringObjectFileELF { + + virtual void Initialize(MCContext &Ctx, const TargetMachine &TM); + + virtual const MCSection * + SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, + Mangler *Mang, const TargetMachine &TM) const; + }; + +} // end namespace llvm + +#endif diff --git a/test/CodeGen/PowerPC/addrfuncstr.ll b/test/CodeGen/PowerPC/addrfuncstr.ll new file mode 100644 index 0000000000..60c02d498f --- /dev/null +++ b/test/CodeGen/PowerPC/addrfuncstr.ll @@ -0,0 +1,27 @@ +; RUN: llc -O0 < %s | FileCheck %s + +; Verify that a constant with an initializer that may turn into a dynamic +; relocation is not placed in .rodata, but rather in .data.rel.ro. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.x = type { i64 (i8*, i64, i64, %struct._IO_FILE*)* } +%struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] } +%struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 } + +@_ZL1y = internal constant %struct.x { i64 (i8*, i64, i64, %struct._IO_FILE*)* @fread }, align 8 + +; Function Attrs: nounwind +define %struct.x* @_Z3foov() #0 { +entry: + ret %struct.x* @_ZL1y +} + +declare i64 @fread(i8*, i64, i64, %struct._IO_FILE*) #1 + +; CHECK: .section .data.rel.ro +; CHECK: .quad fread + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -- cgit v1.2.3 From 59b078fc56e64b9b2d13521670648034cd870c0f Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Mon, 13 May 2013 19:40:36 +0000 Subject: Fix goofy commentary in PPCTargetObjectFile.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181725 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCTargetObjectFile.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/PowerPC/PPCTargetObjectFile.cpp b/lib/Target/PowerPC/PPCTargetObjectFile.cpp index b374b5992a..90e4f15452 100644 --- a/lib/Target/PowerPC/PPCTargetObjectFile.cpp +++ b/lib/Target/PowerPC/PPCTargetObjectFile.cpp @@ -32,7 +32,7 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, if (DefaultSection != ReadOnlySection) return DefaultSection; - // Here override isReadOnly() to isReadOnlyWithRel() for PPC64 SVR4 ABI + // Here override ReadOnlySection to DataRelROSection for PPC64 SVR4 ABI // when we have a constant that contains global relocations. This is // necessary because of this ABI's handling of pointers to functions in // a shared library. The address of a function is actually the address @@ -43,7 +43,7 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, // pointers to functions in shared libraries into dynamic relocations, // because of an ordering problem with initialization of copy relocs and // PLT entries. The dynamic relocation will be initialized by the dynamic - // linker, so we must use the DataRelRO section instead of ReadOnlySection. + // linker, so we must use DataRelROSection instead of ReadOnlySection. // For more information, see the description of ELIMINATE_COPY_RELOCS in // GNU ld. const GlobalVariable *GVar = dyn_cast(GV); -- cgit v1.2.3 From 774a8cf2f5a5f8cd580c71f5eb3055a293917102 Mon Sep 17 00:00:00 2001 From: Michael Gottesman Date: Mon, 13 May 2013 19:40:39 +0000 Subject: [objc-arc-opts] Add comment to BBState making it clear that get{TopDown,BottomUp}PtrState will create a new PtrState object if it does not find a PtrState for Arg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181726 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/ObjCARC/ObjCARCOpts.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp index 6d2d630bb6..d2d8325d1f 100644 --- a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp +++ b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp @@ -587,10 +587,16 @@ namespace { /// definition. void SetAsExit() { BottomUpPathCount = 1; } + /// Attempt to find the PtrState object describing the top down state for + /// pointer Arg. Return a new initialized PtrState describing the top down + /// state for Arg if we do not find one. PtrState &getPtrTopDownState(const Value *Arg) { return PerPtrTopDown[Arg]; } + /// Attempt to find the PtrState object describing the bottom up state for + /// pointer Arg. Return a new initialized PtrState describing the bottom up + /// state for Arg if we do not find one. PtrState &getPtrBottomUpState(const Value *Arg) { return PerPtrBottomUp[Arg]; } -- cgit v1.2.3 From f4a1377322a9234c17b1d324c47248bdb5f62158 Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Mon, 13 May 2013 20:26:46 +0000 Subject: Mips assembler: Assembler macro ADDIU $rs,imm This patch adds alias for addiu instruction which enables following syntax: addiu $rs,imm The macro is translated as: addiu $rs,$rs,imm Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsInstrInfo.td | 3 ++- test/MC/Mips/mips-alu-instructions.s | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 3d319373fe..5ada1df267 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1095,7 +1095,8 @@ def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; - +def : InstAlias<"addiu $rs, $imm", + (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rs, simm16:$imm), 0>; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index 586e88bc48..0df6f85442 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -70,6 +70,7 @@ # CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24] # CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20] # CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24] +# CHECK: addiu $11, $11, 40 # encoding: [0x28,0x00,0x6b,0x25] # CHECK: addu $9, $6, $7 # encoding: [0x21,0x48,0xc7,0x00] # CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70] # CHECK: maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70] @@ -91,6 +92,7 @@ addu $9,$6,-15001 addi $9,$6,17767 addiu $9,$6,-15001 + addiu $11,40 addu $9,$6,$7 madd $6,$7 maddu $6,$7 -- cgit v1.2.3 From 9b5e6c0943dcfced64980240e25427cdc06c9bad Mon Sep 17 00:00:00 2001 From: Matt Beaumont-Gay Date: Mon, 13 May 2013 21:10:49 +0000 Subject: Move a couple more statistics inside '#ifndef NDEBUG'. Suppresses an unused-variable warning in -Asserts builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181733 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/ObjCARC/ObjCARCOpts.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp index d2d8325d1f..bab49e75b7 100644 --- a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp +++ b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp @@ -303,11 +303,11 @@ STATISTIC(NumRets, "Number of return value forwarding " "retain+autoreleaes eliminated"); STATISTIC(NumRRs, "Number of retain+release paths eliminated"); STATISTIC(NumPeeps, "Number of calls peephole-optimized"); +#ifndef NDEBUG STATISTIC(NumRetainsBeforeOpt, "Number of retains before optimization."); STATISTIC(NumReleasesBeforeOpt, "Number of releases before optimization."); -#ifndef NDEBUG STATISTIC(NumRetainsAfterOpt, "Number of retains after optimization."); STATISTIC(NumReleasesAfterOpt, -- cgit v1.2.3 From acfb3584c58159ec20a8379c864c9d644f8d967e Mon Sep 17 00:00:00 2001 From: Michael Gottesman Date: Mon, 13 May 2013 23:49:42 +0000 Subject: [objc-arc-opts] In the presense of an alloca unconditionally remove RR pairs if and only if we are both KnownSafeBU/KnownSafeTD rather than just either or. In the presense of a block being initialized, the frontend will emit the objc_retain on the original pointer and the release on the pointer loaded from the alloca. The optimizer will through the provenance analysis realize that the two are related (albiet different), but since we only require KnownSafe in one direction, will match the inner retain on the original pointer with the guard release on the original pointer. This is fixed by ensuring that in the presense of allocas we only unconditionally remove pointers if both our retain and our release are KnownSafe (i.e. we are KnownSafe in both directions) since we must deal with the possibility that the frontend will emit what (to the optimizer) appears to be unbalanced retain/releases. An example of the miscompile is: %A = alloca retain(%x) retain(%x) <--- Inner Retain store %x, %A %y = load %A ... DO STUFF ... release(%y) call void @use(%x) release(%x) <--- Guarding Release getting optimized to: %A = alloca retain(%x) store %x, %A %y = load %A ... DO STUFF ... release(%y) call void @use(%x) rdar://13750319 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181743 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/ObjCARC/ObjCARCOpts.cpp | 96 +++++++++++++++- test/Transforms/ObjCARC/allocas.ll | 203 +++++++++++++++++++++++++++++++++ 2 files changed, 294 insertions(+), 5 deletions(-) create mode 100644 test/Transforms/ObjCARC/allocas.ll diff --git a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp index bab49e75b7..2932af10c2 100644 --- a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp +++ b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp @@ -107,6 +107,12 @@ namespace { return std::make_pair(Vector.begin() + Pair.first->second, false); } + iterator find(const KeyT &Key) { + typename MapTy::iterator It = Map.find(Key); + if (It == Map.end()) return Vector.end(); + return Vector.begin() + It->second; + } + const_iterator find(const KeyT &Key) const { typename MapTy::const_iterator It = Map.find(Key); if (It == Map.end()) return Vector.end(); @@ -253,6 +259,40 @@ static bool DoesRetainableObjPtrEscape(const User *Ptr) { return false; } +/// This is a wrapper around getUnderlyingObjCPtr along the lines of +/// GetUnderlyingObjects except that it returns early when it sees the first +/// alloca. +static inline bool AreAnyUnderlyingObjectsAnAlloca(const Value *V) { + SmallPtrSet Visited; + SmallVector Worklist; + Worklist.push_back(V); + do { + const Value *P = Worklist.pop_back_val(); + P = GetUnderlyingObjCPtr(P); + + if (isa(P)) + return true; + + if (!Visited.insert(P)) + continue; + + if (const SelectInst *SI = dyn_cast(P)) { + Worklist.push_back(SI->getTrueValue()); + Worklist.push_back(SI->getFalseValue()); + continue; + } + + if (const PHINode *PN = dyn_cast(P)) { + for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) + Worklist.push_back(PN->getIncomingValue(i)); + continue; + } + } while (!Worklist.empty()); + + return false; +} + + /// @} /// /// \defgroup ARCOpt ARC Optimization. @@ -414,8 +454,18 @@ namespace { /// sequence. SmallPtrSet ReverseInsertPts; + /// Does this pointer have multiple owners? + /// + /// In the presence of multiple owners with the same provenance caused by + /// allocas, we can not assume that the frontend will emit balanced code + /// since it could put the release on the pointer loaded from the + /// alloca. This confuses the optimizer so we must be more conservative in + /// that case. + bool MultipleOwners; + RRInfo() : - KnownSafe(false), IsTailCallRelease(false), ReleaseMetadata(0) {} + KnownSafe(false), IsTailCallRelease(false), ReleaseMetadata(0), + MultipleOwners(false) {} void clear(); @@ -428,6 +478,7 @@ namespace { void RRInfo::clear() { KnownSafe = false; IsTailCallRelease = false; + MultipleOwners = false; ReleaseMetadata = 0; Calls.clear(); ReverseInsertPts.clear(); @@ -516,6 +567,7 @@ PtrState::Merge(const PtrState &Other, bool TopDown) { RRI.IsTailCallRelease = RRI.IsTailCallRelease && Other.RRI.IsTailCallRelease; RRI.Calls.insert(Other.RRI.Calls.begin(), Other.RRI.Calls.end()); + RRI.MultipleOwners |= Other.RRI.MultipleOwners; // Merge the insert point sets. If there are any differences, // that makes this a partial merge. @@ -601,6 +653,12 @@ namespace { return PerPtrBottomUp[Arg]; } + /// Attempt to find the PtrState object describing the bottom up state for + /// pointer Arg. + ptr_iterator findPtrBottomUpState(const Value *Arg) { + return PerPtrBottomUp.find(Arg); + } + void clearBottomUpPointers() { PerPtrBottomUp.clear(); } @@ -1865,6 +1923,28 @@ ObjCARCOpt::VisitInstructionBottomUp(Instruction *Inst, case IC_None: // These are irrelevant. return NestingDetected; + case IC_User: + // If we have a store into an alloca of a pointer we are tracking, the + // pointer has multiple owners implying that we must be more conservative. + // + // This comes up in the context of a pointer being ``KnownSafe''. In the + // presense of a block being initialized, the frontend will emit the + // objc_retain on the original pointer and the release on the pointer loaded + // from the alloca. The optimizer will through the provenance analysis + // realize that the two are related, but since we only require KnownSafe in + // one direction, will match the inner retain on the original pointer with + // the guard release on the original pointer. This is fixed by ensuring that + // in the presense of allocas we only unconditionally remove pointers if + // both our retain and our release are KnownSafe. + if (StoreInst *SI = dyn_cast(Inst)) { + if (AreAnyUnderlyingObjectsAnAlloca(SI->getPointerOperand())) { + BBState::ptr_iterator I = MyStates.findPtrBottomUpState( + StripPointerCastsAndObjCCalls(SI->getValueOperand())); + if (I != MyStates.bottom_up_ptr_end()) + I->second.RRI.MultipleOwners = true; + } + } + break; default: break; } @@ -2411,8 +2491,10 @@ ObjCARCOpt::ConnectTDBUTraversals(DenseMap bool KnownSafe, bool &AnyPairsCompletelyEliminated) { // If a pair happens in a region where it is known that the reference count - // is already incremented, we can similarly ignore possible decrements. + // is already incremented, we can similarly ignore possible decrements unless + // we are dealing with a retainable object with multiple provenance sources. bool KnownSafeTD = true, KnownSafeBU = true; + bool MultipleOwners = false; // Connect the dots between the top-down-collected RetainsToMove and // bottom-up-collected ReleasesToMove to form sets of related calls. @@ -2431,6 +2513,7 @@ ObjCARCOpt::ConnectTDBUTraversals(DenseMap assert(It != Retains.end()); const RRInfo &NewRetainRRI = It->second; KnownSafeTD &= NewRetainRRI.KnownSafe; + MultipleOwners |= NewRetainRRI.MultipleOwners; for (SmallPtrSet::const_iterator LI = NewRetainRRI.Calls.begin(), LE = NewRetainRRI.Calls.end(); LI != LE; ++LI) { @@ -2524,9 +2607,12 @@ ObjCARCOpt::ConnectTDBUTraversals(DenseMap if (NewRetains.empty()) break; } - // If the pointer is known incremented or nested, we can safely delete the - // pair regardless of what's between them. - if (KnownSafeTD || KnownSafeBU) { + // If the pointer is known incremented in 1 direction and we do not have + // MultipleOwners, we can safely remove the retain/releases. Otherwise we need + // to be known safe in both directions. + bool UnconditionallySafe = (KnownSafeTD && KnownSafeBU) || + ((KnownSafeTD || KnownSafeBU) && !MultipleOwners); + if (UnconditionallySafe) { RetainsToMove.ReverseInsertPts.clear(); ReleasesToMove.ReverseInsertPts.clear(); NewCount = 0; diff --git a/test/Transforms/ObjCARC/allocas.ll b/test/Transforms/ObjCARC/allocas.ll new file mode 100644 index 0000000000..eabd54deb7 --- /dev/null +++ b/test/Transforms/ObjCARC/allocas.ll @@ -0,0 +1,203 @@ +; RUN: opt -objc-arc -S < %s | FileCheck %s + +declare i8* @objc_retain(i8*) +declare i8* @objc_retainAutoreleasedReturnValue(i8*) +declare void @objc_release(i8*) +declare i8* @objc_autorelease(i8*) +declare i8* @objc_autoreleaseReturnValue(i8*) +declare void @objc_autoreleasePoolPop(i8*) +declare i8* @objc_autoreleasePoolPush() +declare i8* @objc_retainBlock(i8*) + +declare i8* @objc_retainedObject(i8*) +declare i8* @objc_unretainedObject(i8*) +declare i8* @objc_unretainedPointer(i8*) + +declare void @use_pointer(i8*) +declare void @callee() +declare void @callee_fnptr(void ()*) +declare void @invokee() +declare i8* @returner() +declare void @bar(i32 ()*) +declare void @use_alloca(i8**) + +declare void @llvm.dbg.value(metadata, i64, metadata) + +declare i8* @objc_msgSend(i8*, i8*, ...) + + +; In the presense of allocas, unconditionally remove retain/release pairs only +; if they are known safe in both directions. This prevents matching up an inner +; retain with the boundary guarding release in the following situation: +; +; %A = alloca +; retain(%x) +; retain(%x) <--- Inner Retain +; store %x, %A +; %y = load %A +; ... DO STUFF ... +; release(%y) +; release(%x) <--- Guarding Release +; +; rdar://13750319 + +; CHECK: define void @test1a(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_release(i8* %y) +; CHECK: @objc_release(i8* %x) +; CHECK: ret void +; CHECK: } +define void @test1a(i8* %x) { +entry: + %A = alloca i8* + tail call i8* @objc_retain(i8* %x) + tail call i8* @objc_retain(i8* %x) + store i8* %x, i8** %A, align 8 + %y = load i8** %A + call void @use_alloca(i8** %A) + call void @objc_release(i8* %y), !clang.imprecise_release !0 + call void @use_pointer(i8* %x) + call void @objc_release(i8* %x), !clang.imprecise_release !0 + ret void +} + +; CHECK: define void @test1b(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_release(i8* %y) +; CHECK: @objc_release(i8* %x) +; CHECK: ret void +; CHECK: } +define void @test1b(i8* %x) { +entry: + %A = alloca i8* + %gep = getelementptr i8** %A, i32 0 + tail call i8* @objc_retain(i8* %x) + tail call i8* @objc_retain(i8* %x) + store i8* %x, i8** %gep, align 8 + %y = load i8** %A + call void @use_alloca(i8** %A) + call void @objc_release(i8* %y), !clang.imprecise_release !0 + call void @use_pointer(i8* %x) + call void @objc_release(i8* %x), !clang.imprecise_release !0 + ret void +} + + +; CHECK: define void @test1c(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_release(i8* %y) +; CHECK: @objc_release(i8* %x) +; CHECK: ret void +; CHECK: } +define void @test1c(i8* %x) { +entry: + %A = alloca i8*, i32 3 + %gep = getelementptr i8** %A, i32 2 + tail call i8* @objc_retain(i8* %x) + tail call i8* @objc_retain(i8* %x) + store i8* %x, i8** %gep, align 8 + %y = load i8** %gep + call void @use_alloca(i8** %A) + call void @objc_release(i8* %y), !clang.imprecise_release !0 + call void @use_pointer(i8* %x) + call void @objc_release(i8* %x), !clang.imprecise_release !0 + ret void +} + + +; CHECK: define void @test1d(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_release(i8* %y) +; CHECK: @objc_release(i8* %x) +; CHECK: ret void +; CHECK: } +define void @test1d(i8* %x) { +entry: + br i1 undef, label %use_allocaA, label %use_allocaB + +use_allocaA: + %allocaA = alloca i8* + br label %exit + +use_allocaB: + %allocaB = alloca i8* + br label %exit + +exit: + %A = phi i8** [ %allocaA, %use_allocaA ], [ %allocaB, %use_allocaB ] + %gep = getelementptr i8** %A, i32 0 + tail call i8* @objc_retain(i8* %x) + tail call i8* @objc_retain(i8* %x) + store i8* %x, i8** %gep, align 8 + %y = load i8** %gep + call void @use_alloca(i8** %A) + call void @objc_release(i8* %y), !clang.imprecise_release !0 + call void @use_pointer(i8* %x) + call void @objc_release(i8* %x), !clang.imprecise_release !0 + ret void +} + +; CHECK: define void @test1e(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_release(i8* %y) +; CHECK: @objc_release(i8* %x) +; CHECK: ret void +; CHECK: } +define void @test1e(i8* %x) { +entry: + br i1 undef, label %use_allocaA, label %use_allocaB + +use_allocaA: + %allocaA = alloca i8*, i32 4 + br label %exit + +use_allocaB: + %allocaB = alloca i8*, i32 4 + br label %exit + +exit: + %A = phi i8** [ %allocaA, %use_allocaA ], [ %allocaB, %use_allocaB ] + %gep = getelementptr i8** %A, i32 2 + tail call i8* @objc_retain(i8* %x) + tail call i8* @objc_retain(i8* %x) + store i8* %x, i8** %gep, align 8 + %y = load i8** %gep + call void @use_alloca(i8** %A) + call void @objc_release(i8* %y), !clang.imprecise_release !0 + call void @use_pointer(i8* %x) + call void @objc_release(i8* %x), !clang.imprecise_release !0 + ret void +} + +; CHECK: define void @test1f(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_retain(i8* %x) +; CHECK: @objc_release(i8* %y) +; CHECK: @objc_release(i8* %x) +; CHECK: ret void +; CHECK: } +define void @test1f(i8* %x) { +entry: + %allocaOne = alloca i8* + %allocaTwo = alloca i8* + %A = select i1 undef, i8** %allocaOne, i8** %allocaTwo + tail call i8* @objc_retain(i8* %x) + tail call i8* @objc_retain(i8* %x) + store i8* %x, i8** %A, align 8 + %y = load i8** %A + call void @use_alloca(i8** %A) + call void @objc_release(i8* %y), !clang.imprecise_release !0 + call void @use_pointer(i8* %x) + call void @objc_release(i8* %x), !clang.imprecise_release !0 + ret void +} + + +!0 = metadata !{} + +declare i32 @__gxx_personality_v0(...) -- cgit v1.2.3 From dba53a8c9d4ece0bf44acbf5fce871f2e754d97d Mon Sep 17 00:00:00 2001 From: Michael Gottesman Date: Tue, 14 May 2013 00:08:09 +0000 Subject: [objc-arc-opts] Added debug statements when we set and unset whether a pointer is known positive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181745 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/ObjCARC/ObjCARCOpts.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp index 2932af10c2..5db4797aeb 100644 --- a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp +++ b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp @@ -508,10 +508,12 @@ namespace { Seq(S_None) {} void SetKnownPositiveRefCount() { + DEBUG(dbgs() << "Setting Known Positive.\n"); KnownPositiveRefCount = true; } void ClearKnownPositiveRefCount() { + DEBUG(dbgs() << "Clearing Known Positive.\n"); KnownPositiveRefCount = false; } -- cgit v1.2.3 From 123f18bcb9baeb6dc177cb642126a3a4d9ca8b43 Mon Sep 17 00:00:00 2001 From: Arnold Schwaighofer Date: Tue, 14 May 2013 00:21:18 +0000 Subject: LoopVectorize: Handle loops with multiple forward inductions We used to give up if we saw two integer inductions. After this patch, we base further induction variables on the chosen one like we do in the reverse induction and pointer induction case. Fixes PR15720. radar://13851975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181746 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/Vectorize/LoopVectorize.cpp | 57 +++++++++++++++++++++--------- test/Transforms/LoopVectorize/induction.ll | 30 ++++++++++++++++ 2 files changed, 70 insertions(+), 17 deletions(-) create mode 100644 test/Transforms/LoopVectorize/induction.ll diff --git a/lib/Transforms/Vectorize/LoopVectorize.cpp b/lib/Transforms/Vectorize/LoopVectorize.cpp index 0dd6abb1ae..0b29445dd0 100644 --- a/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -1389,9 +1389,10 @@ InnerLoopVectorizer::createEmptyLoop(LoopVectorizationLegality *Legal) { case LoopVectorizationLegality::IK_NoInduction: llvm_unreachable("Unknown induction"); case LoopVectorizationLegality::IK_IntInduction: { - // Handle the integer induction counter: + // Handle the integer induction counter. assert(OrigPhi->getType()->isIntegerTy() && "Invalid type"); - assert(OrigPhi == OldInduction && "Unknown integer PHI"); + + // We have the canonical induction variable. if (OrigPhi == OldInduction) { // Create a truncated version of the resume value for the scalar loop, // we might have promoted the type to a larger width. @@ -1402,11 +1403,20 @@ InnerLoopVectorizer::createEmptyLoop(LoopVectorizationLegality *Legal) { for (unsigned I = 0, E = LoopBypassBlocks.size(); I != E; ++I) TruncResumeVal->addIncoming(II.StartValue, LoopBypassBlocks[I]); TruncResumeVal->addIncoming(EndValue, VecBody); + + // We know what the end value is. + EndValue = IdxEndRoundDown; + // We also know which PHI node holds it. + ResumeIndex = ResumeVal; + break; } - // We know what the end value is. - EndValue = IdxEndRoundDown; - // We also know which PHI node holds it. - ResumeIndex = ResumeVal; + + // Not the canonical induction variable - add the vector loop count to the + // start value. + Value *CRD = BypassBuilder.CreateSExtOrTrunc(CountRoundDown, + II.StartValue->getType(), + "cast.crd"); + EndValue = BypassBuilder.CreateAdd(CRD, II.StartValue , "ind.end"); break; } case LoopVectorizationLegality::IK_ReverseIntInduction: { @@ -2056,12 +2066,25 @@ InnerLoopVectorizer::vectorizeBlockInLoop(LoopVectorizationLegality *Legal, case LoopVectorizationLegality::IK_NoInduction: llvm_unreachable("Unknown induction"); case LoopVectorizationLegality::IK_IntInduction: { - assert(P == OldInduction && "Unexpected PHI"); - // We might have had to extend the type. - Value *Trunc = Builder.CreateTrunc(Induction, P->getType()); - Value *Broadcasted = getBroadcastInstrs(Trunc); - // After broadcasting the induction variable we need to make the - // vector consecutive by adding 0, 1, 2 ... + assert(P->getType() == II.StartValue->getType() && "Types must match"); + Type *PhiTy = P->getType(); + Value *Broadcasted; + if (P == OldInduction) { + // Handle the canonical induction variable. We might have had to + // extend the type. + Broadcasted = Builder.CreateTrunc(Induction, PhiTy); + } else { + // Handle other induction variables that are now based on the + // canonical one. + Value *NormalizedIdx = Builder.CreateSub(Induction, ExtendedIdx, + "normalized.idx"); + NormalizedIdx = Builder.CreateSExtOrTrunc(NormalizedIdx, PhiTy); + Broadcasted = Builder.CreateAdd(II.StartValue, NormalizedIdx, + "offset.idx"); + } + Broadcasted = getBroadcastInstrs(Broadcasted); + // After broadcasting the induction variable we need to make the vector + // consecutive by adding 0, 1, 2, etc. for (unsigned part = 0; part < UF; ++part) Entry[part] = getConsecutiveVector(Broadcasted, VF * part, false); continue; @@ -2466,11 +2489,11 @@ bool LoopVectorizationLegality::canVectorizeInstrs() { // Int inductions are special because we only allow one IV. if (IK == IK_IntInduction) { - if (Induction) { - DEBUG(dbgs() << "LV: Found too many inductions."<< *Phi <<"\n"); - return false; - } - Induction = Phi; + // Use the phi node with the widest type as induction. Use the last + // one if there are multiple (no good reason for doing this other + // than it is expedient). + if (!Induction || PhiTy == WidestIndTy) + Induction = Phi; } DEBUG(dbgs() << "LV: Found an induction variable.\n"); diff --git a/test/Transforms/LoopVectorize/induction.ll b/test/Transforms/LoopVectorize/induction.ll new file mode 100644 index 0000000000..48bb438a86 --- /dev/null +++ b/test/Transforms/LoopVectorize/induction.ll @@ -0,0 +1,30 @@ +; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=2 -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +; Make sure that we can handle multiple integer induction variables. +; CHECK: multi_int_induction +; CHECK: vector.body: +; CHECK: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] +; CHECK: %normalized.idx = sub i64 %index, 0 +; CHECK: %[[VAR:.*]] = trunc i64 %normalized.idx to i32 +; CHECK: %offset.idx = add i32 190, %[[VAR]] +define void @multi_int_induction(i32* %A, i32 %N) { +for.body.lr.ph: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ] + %count.09 = phi i32 [ 190, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx2 = getelementptr inbounds i32* %A, i64 %indvars.iv + store i32 %count.09, i32* %arrayidx2, align 4 + %inc = add nsw i32 %count.09, 1 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp ne i32 %lftr.wideiv, %N + br i1 %exitcond, label %for.body, label %for.end + +for.end: + ret void +} + -- cgit v1.2.3 From 17a692e7f196c15118e69d7012d110aa00a362ba Mon Sep 17 00:00:00 2001 From: David Blaikie Date: Tue, 14 May 2013 00:35:19 +0000 Subject: Assert that DIEEntries are constructed with non-null DIEs This just brings a crash a little further forward from DWARF emission to DIE construction to make errors easier to diagnose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181748 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/AsmPrinter/DIE.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/AsmPrinter/DIE.h b/lib/CodeGen/AsmPrinter/DIE.h index 3c06001686..d8fa1f5a0e 100644 --- a/lib/CodeGen/AsmPrinter/DIE.h +++ b/lib/CodeGen/AsmPrinter/DIE.h @@ -325,7 +325,9 @@ namespace llvm { class DIEEntry : public DIEValue { DIE *const Entry; public: - explicit DIEEntry(DIE *E) : DIEValue(isEntry), Entry(E) {} + explicit DIEEntry(DIE *E) : DIEValue(isEntry), Entry(E) { + assert(E && "Cannot construct a DIEEntry with a null DIE"); + } DIE *getEntry() const { return Entry; } -- cgit v1.2.3 From dd29df06fa72de9e370cdd9d8e32ac5437a578c7 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Tue, 14 May 2013 01:42:44 +0000 Subject: StackColoring: don't clear an instruction's mem operand if the underlying object is a PseudoSourceValue and PseudoSourceValue::isConstant returns true (i.e., points to memory that has a constant value). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181751 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/StackColoring.cpp | 5 +++++ test/CodeGen/Mips/stackcoloring.ll | 39 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 test/CodeGen/Mips/stackcoloring.ll diff --git a/lib/CodeGen/StackColoring.cpp b/lib/CodeGen/StackColoring.cpp index a789a2596d..90b93aaa72 100644 --- a/lib/CodeGen/StackColoring.cpp +++ b/lib/CodeGen/StackColoring.cpp @@ -42,6 +42,7 @@ #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SlotIndexes.h" #include "llvm/DebugInfo.h" #include "llvm/IR/Function.h" @@ -528,6 +529,10 @@ void StackColoring::remapInstructions(DenseMap &SlotRemap) { if (!V) continue; + const PseudoSourceValue *PSV = dyn_cast(V); + if (PSV && PSV->isConstant(MFI)) + continue; + // Climb up and find the original alloca. V = GetUnderlyingObject(V); // If we did not find one, or if the one that we found is not in our diff --git a/test/CodeGen/Mips/stackcoloring.ll b/test/CodeGen/Mips/stackcoloring.ll new file mode 100644 index 0000000000..76cc08679d --- /dev/null +++ b/test/CodeGen/Mips/stackcoloring.ll @@ -0,0 +1,39 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +@g1 = external global i32* + +; CHECK: foo1: +; CHECK: lw ${{[0-9]+}}, %got(g1) +; CHECK: # %for.body +; CHECK: # %for.end + +define i32 @foo1() { +entry: + %b = alloca [16 x i32], align 4 + %0 = bitcast [16 x i32]* %b to i8* + call void @llvm.lifetime.start(i64 64, i8* %0) + %arraydecay = getelementptr inbounds [16 x i32]* %b, i32 0, i32 0 + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %v.04 = phi i32 [ 0, %entry ], [ %add, %for.body ] + %1 = load i32** @g1, align 4 + %arrayidx = getelementptr inbounds i32* %1, i32 %i.05 + %2 = load i32* %arrayidx, align 4 + %call = call i32 @foo2(i32 %2, i32* %arraydecay) + %add = add nsw i32 %call, %v.04 + %inc = add nsw i32 %i.05, 1 + %exitcond = icmp eq i32 %inc, 10000 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + call void @llvm.lifetime.end(i64 64, i8* %0) + ret i32 %add +} + +declare void @llvm.lifetime.start(i64, i8* nocapture) + +declare i32 @foo2(i32, i32*) + +declare void @llvm.lifetime.end(i64, i8* nocapture) -- cgit v1.2.3 From eafa96485a6c3ce0de4f511ed080a64a7a44f2bb Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Tue, 14 May 2013 02:00:24 +0000 Subject: This is the first of three patches which creates stubs used for Mips16/32 floating point interoperability. When Mips16 code calls external functions that would normally have some of its parameters or return values passed in floating point registers, it needs (Mips32) helper functions to do this because while in Mips16 mode there is no ability to access the floating point registers. In Pic mode, this is done with a set of predefined functions in libc. This case is already handled in llvm for Mips16. In static relocation mode, for efficiency reasons, the compiler generates stubs that the linker will use if it turns out that the external function is a Mips32 function. (If it's Mips16, then it does not need the helper stubs). These stubs are identically named and the linker knows about these tricks and will not create multiple copies and will delete them if they are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181753 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16HardFloat.cpp | 275 ++++++++++ test/CodeGen/Mips/hf16call32.ll | 1028 +++++++++++++++++++++++++++++++++++ 2 files changed, 1303 insertions(+) create mode 100644 test/CodeGen/Mips/hf16call32.ll diff --git a/lib/Target/Mips/Mips16HardFloat.cpp b/lib/Target/Mips/Mips16HardFloat.cpp index 4d1e61bb99..304715aaa4 100644 --- a/lib/Target/Mips/Mips16HardFloat.cpp +++ b/lib/Target/Mips/Mips16HardFloat.cpp @@ -18,6 +18,36 @@ #include "llvm/Support/raw_ostream.h" #include +static void inlineAsmOut + (LLVMContext &C, StringRef AsmString, BasicBlock *BB ) { + std::vector AsmArgTypes; + std::vector AsmArgs; + llvm::FunctionType *AsmFTy = + llvm::FunctionType::get(Type::getVoidTy(C), + AsmArgTypes, false); + llvm::InlineAsm *IA = + llvm::InlineAsm::get(AsmFTy, AsmString, "", true, + /* IsAlignStack */ false, + llvm::InlineAsm::AD_ATT); + CallInst::Create(IA, AsmArgs, "", BB); +} + +namespace { + +class InlineAsmHelper { + LLVMContext &C; + BasicBlock *BB; +public: + InlineAsmHelper(LLVMContext &C_, BasicBlock *BB_) : + C(C_), BB(BB_) { + } + + void Out(StringRef AsmString) { + inlineAsmOut(C, AsmString, BB); + } + +}; +} // // Return types that matter for hard float are: // float, double, complex float, and complex double @@ -51,6 +81,241 @@ static FPReturnVariant whichFPReturnVariant(Type *T) { return NoFPRet; } +// +// Parameter type that matter are float, (float, float), (float, double), +// double, (double, double), (double, float) +// +enum FPParamVariant { + FSig, FFSig, FDSig, + DSig, DDSig, DFSig, NoSig +}; + +// which floating point parameter signature variant we are dealing with +// +typedef Type::TypeID TypeID; +const Type::TypeID FloatTyID = Type::FloatTyID; +const Type::TypeID DoubleTyID = Type::DoubleTyID; + +static FPParamVariant whichFPParamVariantNeeded(Function &F) { + switch (F.arg_size()) { + case 0: + return NoSig; + case 1:{ + TypeID ArgTypeID = F.getFunctionType()->getParamType(0)->getTypeID(); + switch (ArgTypeID) { + case FloatTyID: + return FSig; + case DoubleTyID: + return DSig; + default: + return NoSig; + } + } + default: { + TypeID ArgTypeID0 = F.getFunctionType()->getParamType(0)->getTypeID(); + TypeID ArgTypeID1 = F.getFunctionType()->getParamType(1)->getTypeID(); + switch(ArgTypeID0) { + case FloatTyID: { + switch (ArgTypeID1) { + case FloatTyID: + return FFSig; + case DoubleTyID: + return FDSig; + default: + return FSig; + } + } + case DoubleTyID: { + switch (ArgTypeID1) { + case FloatTyID: + return DFSig; + case DoubleTyID: + return DDSig; + default: + return DSig; + } + } + default: + return NoSig; + } + } + } + llvm_unreachable("can't get here"); +} + +// Figure out if we need float point based on the function parameters. +// We need to move variables in and/or out of floating point +// registers because of the ABI +// +static bool needsFPStubFromParams(Function &F) { + if (F.arg_size() >=1) { + Type *ArgType = F.getFunctionType()->getParamType(0); + switch (ArgType->getTypeID()) { + case Type::FloatTyID: + case Type::DoubleTyID: + return true; + default: + break; + } + } + return false; +} + +static bool needsFPReturnHelper(Function &F) { + Type* RetType = F.getReturnType(); + return whichFPReturnVariant(RetType) != NoFPRet; +} + +static bool needsFPHelperFromSig(Function &F) { + return needsFPStubFromParams(F) || needsFPReturnHelper(F); +} + +// +// We swap between FP and Integer registers to allow Mips16 and Mips32 to +// interoperate +// + +void swapFPIntParams(FPParamVariant PV, Module *M, InlineAsmHelper &IAH, + bool LE, bool ToFP) { + //LLVMContext &Context = M->getContext(); + std::string MI = ToFP? "mtc1 ": "mfc1 "; + switch (PV) { + case FSig: + IAH.Out(MI + "$$4,$$f12"); + break; + case FFSig: + IAH.Out(MI +"$$4,$$f12"); + IAH.Out(MI + "$$5,$$f14"); + break; + case FDSig: + IAH.Out(MI + "$$4,$$f12"); + if (LE) { + IAH.Out(MI + "$$6,$$f14"); + IAH.Out(MI + "$$7,$$f15"); + } else { + IAH.Out(MI + "$$7,$$f14"); + IAH.Out(MI + "$$6,$$f15"); + } + break; + case DSig: + if (LE) { + IAH.Out(MI + "$$4,$$f12"); + IAH.Out(MI + "$$5,$$f13"); + } else { + IAH.Out(MI + "$$5,$$f12"); + IAH.Out(MI + "$$4,$$f13"); + } + break; + case DDSig: + if (LE) { + IAH.Out(MI + "$$4,$$f12"); + IAH.Out(MI + "$$5,$$f13"); + IAH.Out(MI + "$$6,$$f14"); + IAH.Out(MI + "$$7,$$f15"); + } else { + IAH.Out(MI + "$$5,$$f12"); + IAH.Out(MI + "$$4,$$f13"); + IAH.Out(MI + "$$7,$$f14"); + IAH.Out(MI + "$$6,$$f15"); + } + break; + case DFSig: + if (LE) { + IAH.Out(MI + "$$4,$$f12"); + IAH.Out(MI + "$$5,$$f13"); + } else { + IAH.Out(MI + "$$5,$$f12"); + IAH.Out(MI + "$$4,$$f13"); + } + IAH.Out(MI + "$$6,$$f14"); + break; + case NoSig: + return; + } +} +// +// Make sure that we know we already need a stub for this function. +// Having called needsFPHelperFromSig +// +void assureFPCallStub(Function &F, Module *M, const MipsSubtarget &Subtarget){ + // for now we only need them for static relocation + if (!Subtarget.getRelocationModel() == Reloc::PIC_) + return; + LLVMContext &Context = M->getContext(); + bool LE = Subtarget.isLittle(); + std::string Name = F.getName(); + std::string SectionName = ".mips16.call.fp." + Name; + std::string StubName = "__call_stub_" + Name; + // + // see if we already have the stub + // + Function *FStub = M->getFunction(StubName); + if (FStub && !FStub->isDeclaration()) return; + FStub = Function::Create(F.getFunctionType(), + Function::InternalLinkage, StubName, M); + FStub->addFnAttr("mips16_fp_stub"); + FStub->addFnAttr(llvm::Attribute::Naked); + FStub->addFnAttr(llvm::Attribute::NoUnwind); + FStub->addFnAttr("nomips16"); + FStub->setSection(SectionName); + BasicBlock *BB = BasicBlock::Create(Context, "entry", FStub); + InlineAsmHelper IAH(Context, BB); + FPReturnVariant RV = whichFPReturnVariant(FStub->getReturnType()); + FPParamVariant PV = whichFPParamVariantNeeded(F); + swapFPIntParams(PV, M, IAH, LE, true); + if (RV != NoFPRet) { + IAH.Out("move $$18, $$31"); + IAH.Out("jal " + Name); + } else { + IAH.Out("lui $$25,%hi(" + Name + ")"); + IAH.Out("addiu $$25,$$25,%lo(" + Name + ")" ); + } + switch (RV) { + case FRet: + IAH.Out("mfc1 $$2,$$f0"); + break; + case DRet: + if (LE) { + IAH.Out("mfc1 $$2,$$f0"); + IAH.Out("mfc1 $$3,$$f1"); + } else { + IAH.Out("mfc1 $$3,$$f0"); + IAH.Out("mfc1 $$2,$$f1"); + } + break; + case CFRet: + if (LE) { + IAH.Out("mfc1 $$2,$$f0"); + IAH.Out("mfc1 $$3,$$f2"); + } else { + IAH.Out("mfc1 $$3,$$f0"); + IAH.Out("mfc1 $$3,$$f2"); + } + break; + case CDRet: + if (LE) { + IAH.Out("mfc1 $$4,$$f2"); + IAH.Out("mfc1 $$5,$$f3"); + IAH.Out("mfc1 $$2,$$f0"); + IAH.Out("mfc1 $$3,$$f1"); + + } else { + IAH.Out("mfc1 $$5,$$f2"); + IAH.Out("mfc1 $$4,$$f3"); + IAH.Out("mfc1 $$3,$$f0"); + IAH.Out("mfc1 $$2,$$f1"); + } + break; + case NoFPRet: + break; + } + if (RV != NoFPRet) + IAH.Out("jr $$18"); + else + IAH.Out("jr $$25"); + new UnreachableInst(Context, BB); +} + // // Returns of float, double and complex need to be handled with a helper // function. The "AndCal" part is coming in a later patch. @@ -96,6 +361,16 @@ static bool fixupFPReturnAndCall Attribute::ReadNone); Value *F = (M->getOrInsertFunction(Name, A, MyVoid, T, NULL)); CallInst::Create(F, Params, "", &Inst ); + } else if (const CallInst *CI = dyn_cast(I)) { + // pic mode calls are handled by already defined + // helper functions + if (Subtarget.getRelocationModel() != Reloc::PIC_ ) { + Function *F_ = CI->getCalledFunction(); + if (F_ && needsFPHelperFromSig(*F_)) { + assureFPCallStub(*F_, M, Subtarget); + Modified=true; + } + } } } return Modified; diff --git a/test/CodeGen/Mips/hf16call32.ll b/test/CodeGen/Mips/hf16call32.ll new file mode 100644 index 0000000000..41249e1be2 --- /dev/null +++ b/test/CodeGen/Mips/hf16call32.ll @@ -0,0 +1,1028 @@ +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=stel + +@x = common global float 0.000000e+00, align 4 +@y = common global float 0.000000e+00, align 4 +@xd = common global double 0.000000e+00, align 8 +@yd = common global double 0.000000e+00, align 8 +@xy = common global { float, float } zeroinitializer, align 4 +@xyd = common global { double, double } zeroinitializer, align 8 +@ret_sf = common global float 0.000000e+00, align 4 +@ret_df = common global double 0.000000e+00, align 8 +@ret_sc = common global { float, float } zeroinitializer, align 4 +@ret_dc = common global { double, double } zeroinitializer, align 8 +@lx = common global float 0.000000e+00, align 4 +@ly = common global float 0.000000e+00, align 4 +@lxd = common global double 0.000000e+00, align 8 +@lyd = common global double 0.000000e+00, align 8 +@lxy = common global { float, float } zeroinitializer, align 4 +@lxyd = common global { double, double } zeroinitializer, align 8 +@lret_sf = common global float 0.000000e+00, align 4 +@lret_df = common global double 0.000000e+00, align 8 +@lret_sc = common global { float, float } zeroinitializer, align 4 +@lret_dc = common global { double, double } zeroinitializer, align 8 +@.str = private unnamed_addr constant [10 x i8] c"%f %f %i\0A\00", align 1 +@.str1 = private unnamed_addr constant [16 x i8] c"%f=%f %f=%f %i\0A\00", align 1 +@.str2 = private unnamed_addr constant [22 x i8] c"%f=%f %f=%f %f=%f %i\0A\00", align 1 +@.str3 = private unnamed_addr constant [18 x i8] c"%f+%fi=%f+%fi %i\0A\00", align 1 +@.str4 = private unnamed_addr constant [24 x i8] c"%f+%fi=%f+%fi %f=%f %i\0A\00", align 1 + +; Function Attrs: nounwind +define void @clear() #0 { +entry: + store float 1.000000e+00, float* @x, align 4 + store float 1.000000e+00, float* @y, align 4 + store double 1.000000e+00, double* @xd, align 8 + store double 1.000000e+00, double* @yd, align 8 + store float 1.000000e+00, float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 0) + store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 1) + store double 1.000000e+00, double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 0) + store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 1) + store float 1.000000e+00, float* @ret_sf, align 4 + store double 1.000000e+00, double* @ret_df, align 8 + store float 1.000000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0) + store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1) + store double 1.000000e+00, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0) + store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1) + store float 0.000000e+00, float* @lx, align 4 + store float 0.000000e+00, float* @ly, align 4 + store double 0.000000e+00, double* @lxd, align 8 + store double 0.000000e+00, double* @lyd, align 8 + store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @lxy, i32 0, i32 0) + store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @lxy, i32 0, i32 1) + store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @lxyd, i32 0, i32 0) + store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @lxyd, i32 0, i32 1) + store float 0.000000e+00, float* @lret_sf, align 4 + store double 0.000000e+00, double* @lret_df, align 8 + store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0) + store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1) + store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0) + store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1) + ret void +} + +; Function Attrs: nounwind +define i32 @main() #0 { +entry: + %retval = alloca i32, align 4 + store i32 0, i32* %retval + call void @clear() + store float 1.500000e+00, float* @lx, align 4 + %0 = load float* @lx, align 4 + call void @v_sf(float %0) + %1 = load float* @x, align 4 + %conv = fpext float %1 to double + %2 = load float* @lx, align 4 + %conv1 = fpext float %2 to double + %3 = load float* @x, align 4 + %4 = load float* @lx, align 4 + %cmp = fcmp oeq float %3, %4 + %conv2 = zext i1 %cmp to i32 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), double %conv, double %conv1, i32 %conv2) + call void @clear() + store double 0x41678C29C0000000, double* @lxd, align 8 + %5 = load double* @lxd, align 8 + call void @v_df(double %5) + %6 = load double* @xd, align 8 + %7 = load double* @lxd, align 8 + %8 = load double* @xd, align 8 + %9 = load double* @lxd, align 8 + %cmp3 = fcmp oeq double %8, %9 + %conv4 = zext i1 %cmp3 to i32 + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), double %6, double %7, i32 %conv4) + call void @clear() + store float 9.000000e+00, float* @lx, align 4 + store float 1.000000e+01, float* @ly, align 4 + %10 = load float* @lx, align 4 + %11 = load float* @ly, align 4 + call void @v_sf_sf(float %10, float %11) + %12 = load float* @x, align 4 + %conv6 = fpext float %12 to double + %13 = load float* @lx, align 4 + %conv7 = fpext float %13 to double + %14 = load float* @y, align 4 + %conv8 = fpext float %14 to double + %15 = load float* @ly, align 4 + %conv9 = fpext float %15 to double + %16 = load float* @x, align 4 + %17 = load float* @lx, align 4 + %cmp10 = fcmp oeq float %16, %17 + br i1 %cmp10, label %land.rhs, label %land.end + +land.rhs: ; preds = %entry + %18 = load float* @y, align 4 + %19 = load float* @ly, align 4 + %cmp12 = fcmp oeq float %18, %19 + br label %land.end + +land.end: ; preds = %land.rhs, %entry + %20 = phi i1 [ false, %entry ], [ %cmp12, %land.rhs ] + %land.ext = zext i1 %20 to i32 + %call14 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %conv6, double %conv7, double %conv8, double %conv9, i32 %land.ext) + call void @clear() + store float 0x3FFE666660000000, float* @lx, align 4 + store double 0x4007E613249FF279, double* @lyd, align 8 + %21 = load float* @lx, align 4 + %22 = load double* @lyd, align 8 + call void @v_sf_df(float %21, double %22) + %23 = load float* @x, align 4 + %conv15 = fpext float %23 to double + %24 = load float* @lx, align 4 + %conv16 = fpext float %24 to double + %25 = load double* @yd, align 8 + %26 = load double* @lyd, align 8 + %27 = load float* @x, align 4 + %28 = load float* @lx, align 4 + %cmp17 = fcmp oeq float %27, %28 + %conv18 = zext i1 %cmp17 to i32 + %29 = load double* @yd, align 8 + %30 = load double* @lyd, align 8 + %cmp19 = fcmp oeq double %29, %30 + %conv20 = zext i1 %cmp19 to i32 + %and = and i32 %conv18, %conv20 + %call21 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %conv15, double %conv16, double %25, double %26, i32 %and) + call void @clear() + store double 0x4194E54F94000000, double* @lxd, align 8 + store float 7.600000e+01, float* @ly, align 4 + %31 = load double* @lxd, align 8 + %32 = load float* @ly, align 4 + call void @v_df_sf(double %31, float %32) + %33 = load double* @xd, align 8 + %34 = load double* @lxd, align 8 + %35 = load float* @y, align 4 + %conv22 = fpext float %35 to double + %36 = load float* @ly, align 4 + %conv23 = fpext float %36 to double + %37 = load double* @xd, align 8 + %38 = load double* @lxd, align 8 + %cmp24 = fcmp oeq double %37, %38 + %conv25 = zext i1 %cmp24 to i32 + %39 = load float* @y, align 4 + %40 = load float* @ly, align 4 + %cmp26 = fcmp oeq float %39, %40 + %conv27 = zext i1 %cmp26 to i32 + %and28 = and i32 %conv25, %conv27 + %call29 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %33, double %34, double %conv22, double %conv23, i32 %and28) + call void @clear() + store double 7.365198e+07, double* @lxd, align 8 + store double 0x416536CD80000000, double* @lyd, align 8 + %41 = load double* @lxd, align 8 + %42 = load double* @lyd, align 8 + call void @v_df_df(double %41, double %42) + %43 = load double* @xd, align 8 + %44 = load double* @lxd, align 8 + %45 = load double* @yd, align 8 + %46 = load double* @lyd, align 8 + %47 = load double* @xd, align 8 + %48 = load double* @lxd, align 8 + %cmp30 = fcmp oeq double %47, %48 + %conv31 = zext i1 %cmp30 to i32 + %49 = load double* @yd, align 8 + %50 = load double* @lyd, align 8 + %cmp32 = fcmp oeq double %49, %50 + %conv33 = zext i1 %cmp32 to i32 + %and34 = and i32 %conv31, %conv33 + %call35 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %43, double %44, double %45, double %46, i32 %and34) + call void @clear() + store float 0x4016666660000000, float* @ret_sf, align 4 + %call36 = call float @sf_v() + store float %call36, float* @lret_sf, align 4 + %51 = load float* @ret_sf, align 4 + %conv37 = fpext float %51 to double + %52 = load float* @lret_sf, align 4 + %conv38 = fpext float %52 to double + %53 = load float* @ret_sf, align 4 + %54 = load float* @lret_sf, align 4 + %cmp39 = fcmp oeq float %53, %54 + %conv40 = zext i1 %cmp39 to i32 + %call41 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), double %conv37, double %conv38, i32 %conv40) + call void @clear() + store float 4.587300e+06, float* @ret_sf, align 4 + store float 3.420000e+02, float* @lx, align 4 + %55 = load float* @lx, align 4 + %call42 = call float @sf_sf(float %55) + store float %call42, float* @lret_sf, align 4 + %56 = load float* @ret_sf, align 4 + %conv43 = fpext float %56 to double + %57 = load float* @lret_sf, align 4 + %conv44 = fpext float %57 to double + %58 = load float* @x, align 4 + %conv45 = fpext float %58 to double + %59 = load float* @lx, align 4 + %conv46 = fpext float %59 to double + %60 = load float* @ret_sf, align 4 + %61 = load float* @lret_sf, align 4 + %cmp47 = fcmp oeq float %60, %61 + %conv48 = zext i1 %cmp47 to i32 + %62 = load float* @x, align 4 + %63 = load float* @lx, align 4 + %cmp49 = fcmp oeq float %62, %63 + %conv50 = zext i1 %cmp49 to i32 + %and51 = and i32 %conv48, %conv50 + %call52 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %conv43, double %conv44, double %conv45, double %conv46, i32 %and51) + call void @clear() + store float 4.445910e+06, float* @ret_sf, align 4 + store double 0x419A7DB294000000, double* @lxd, align 8 + %64 = load double* @lxd, align 8 + %call53 = call float @sf_df(double %64) + store float %call53, float* @lret_sf, align 4 + %65 = load float* @ret_sf, align 4 + %conv54 = fpext float %65 to double + %66 = load float* @lret_sf, align 4 + %conv55 = fpext float %66 to double + %67 = load double* @xd, align 8 + %68 = load double* @lxd, align 8 + %69 = load float* @ret_sf, align 4 + %70 = load float* @lret_sf, align 4 + %cmp56 = fcmp oeq float %69, %70 + %conv57 = zext i1 %cmp56 to i32 + %71 = load double* @xd, align 8 + %72 = load double* @lxd, align 8 + %cmp58 = fcmp oeq double %71, %72 + %conv59 = zext i1 %cmp58 to i32 + %and60 = and i32 %conv57, %conv59 + %call61 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %conv54, double %conv55, double %67, double %68, i32 %and60) + call void @clear() + store float 0x3FFF4BC6A0000000, float* @ret_sf, align 4 + store float 4.445500e+03, float* @lx, align 4 + store float 0x4068ACCCC0000000, float* @ly, align 4 + %73 = load float* @lx, align 4 + %74 = load float* @ly, align 4 + %call62 = call float @sf_sf_sf(float %73, float %74) + store float %call62, float* @lret_sf, align 4 + %75 = load float* @ret_sf, align 4 + %conv63 = fpext float %75 to double + %76 = load float* @lret_sf, align 4 + %conv64 = fpext float %76 to double + %77 = load float* @x, align 4 + %conv65 = fpext float %77 to double + %78 = load float* @lx, align 4 + %conv66 = fpext float %78 to double + %79 = load float* @y, align 4 + %conv67 = fpext float %79 to double + %80 = load float* @ly, align 4 + %conv68 = fpext float %80 to double + %81 = load float* @ret_sf, align 4 + %82 = load float* @lret_sf, align 4 + %cmp69 = fcmp oeq float %81, %82 + br i1 %cmp69, label %land.lhs.true, label %land.end76 + +land.lhs.true: ; preds = %land.end + %83 = load float* @x, align 4 + %84 = load float* @lx, align 4 + %cmp71 = fcmp oeq float %83, %84 + br i1 %cmp71, label %land.rhs73, label %land.end76 + +land.rhs73: ; preds = %land.lhs.true + %85 = load float* @y, align 4 + %86 = load float* @ly, align 4 + %cmp74 = fcmp oeq float %85, %86 + br label %land.end76 + +land.end76: ; preds = %land.rhs73, %land.lhs.true, %land.end + %87 = phi i1 [ false, %land.lhs.true ], [ false, %land.end ], [ %cmp74, %land.rhs73 ] + %land.ext77 = zext i1 %87 to i32 + %call78 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %conv63, double %conv64, double %conv65, double %conv66, double %conv67, double %conv68, i32 %land.ext77) + call void @clear() + store float 9.991300e+04, float* @ret_sf, align 4 + store float 1.114500e+04, float* @lx, align 4 + store double 9.994445e+07, double* @lyd, align 8 + %88 = load float* @lx, align 4 + %89 = load double* @lyd, align 8 + %call79 = call float @sf_sf_df(float %88, double %89) + store float %call79, float* @lret_sf, align 4 + %90 = load float* @ret_sf, align 4 + %conv80 = fpext float %90 to double + %91 = load float* @lret_sf, align 4 + %conv81 = fpext float %91 to double + %92 = load float* @x, align 4 + %conv82 = fpext float %92 to double + %93 = load float* @lx, align 4 + %conv83 = fpext float %93 to double + %94 = load double* @yd, align 8 + %95 = load double* @lyd, align 8 + %96 = load float* @ret_sf, align 4 + %97 = load float* @lret_sf, align 4 + %cmp84 = fcmp oeq float %96, %97 + br i1 %cmp84, label %land.lhs.true86, label %land.end92 + +land.lhs.true86: ; preds = %land.end76 + %98 = load float* @x, align 4 + %99 = load float* @lx, align 4 + %cmp87 = fcmp oeq float %98, %99 + br i1 %cmp87, label %land.rhs89, label %land.end92 + +land.rhs89: ; preds = %land.lhs.true86 + %100 = load double* @yd, align 8 + %101 = load double* @lyd, align 8 + %cmp90 = fcmp oeq double %100, %101 + br label %land.end92 + +land.end92: ; preds = %land.rhs89, %land.lhs.true86, %land.end76 + %102 = phi i1 [ false, %land.lhs.true86 ], [ false, %land.end76 ], [ %cmp90, %land.rhs89 ] + %land.ext93 = zext i1 %102 to i32 + %call94 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %conv80, double %conv81, double %conv82, double %conv83, double %94, double %95, i32 %land.ext93) + call void @clear() + store float 0x417CCC7A00000000, float* @ret_sf, align 4 + store double 0x4172034530000000, double* @lxd, align 8 + store float 4.456200e+04, float* @ly, align 4 + %103 = load double* @lxd, align 8 + %104 = load float* @ly, align 4 + %call95 = call float @sf_df_sf(double %103, float %104) + store float %call95, float* @lret_sf, align 4 + %105 = load float* @ret_sf, align 4 + %conv96 = fpext float %105 to double + %106 = load float* @lret_sf, align 4 + %conv97 = fpext float %106 to double + %107 = load double* @xd, align 8 + %108 = load double* @lxd, align 8 + %109 = load float* @y, align 4 + %conv98 = fpext float %109 to double + %110 = load float* @ly, align 4 + %conv99 = fpext float %110 to double + %111 = load float* @ret_sf, align 4 + %112 = load float* @lret_sf, align 4 + %cmp100 = fcmp oeq float %111, %112 + br i1 %cmp100, label %land.lhs.true102, label %land.end108 + +land.lhs.true102: ; preds = %land.end92 + %113 = load double* @xd, align 8 + %114 = load double* @lxd, align 8 + %cmp103 = fcmp oeq double %113, %114 + br i1 %cmp103, label %land.rhs105, label %land.end108 + +land.rhs105: ; preds = %land.lhs.true102 + %115 = load float* @y, align 4 + %116 = load float* @ly, align 4 + %cmp106 = fcmp oeq float %115, %116 + br label %land.end108 + +land.end108: ; preds = %land.rhs105, %land.lhs.true102, %land.end92 + %117 = phi i1 [ false, %land.lhs.true102 ], [ false, %land.end92 ], [ %cmp106, %land.rhs105 ] + %land.ext109 = zext i1 %117 to i32 + %call110 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %conv96, double %conv97, double %107, double %108, double %conv98, double %conv99, i32 %land.ext109) + call void @clear() + store float 3.987721e+06, float* @ret_sf, align 4 + store double 0x3FF1F49F6DDDC2D8, double* @lxd, align 8 + store double 0x409129F306A2B170, double* @lyd, align 8 + %118 = load double* @lxd, align 8 + %119 = load double* @lyd, align 8 + %call111 = call float @sf_df_df(double %118, double %119) + store float %call111, float* @lret_sf, align 4 + %120 = load float* @ret_sf, align 4 + %conv112 = fpext float %120 to double + %121 = load float* @lret_sf, align 4 + %conv113 = fpext float %121 to double + %122 = load double* @xd, align 8 + %123 = load double* @lxd, align 8 + %124 = load double* @yd, align 8 + %125 = load double* @lyd, align 8 + %126 = load float* @ret_sf, align 4 + %127 = load float* @lret_sf, align 4 + %cmp114 = fcmp oeq float %126, %127 + br i1 %cmp114, label %land.lhs.true116, label %land.end122 + +land.lhs.true116: ; preds = %land.end108 + %128 = load double* @xd, align 8 + %129 = load double* @lxd, align 8 + %cmp117 = fcmp oeq double %128, %129 + br i1 %cmp117, label %land.rhs119, label %land.end122 + +land.rhs119: ; preds = %land.lhs.true116 + %130 = load double* @yd, align 8 + %131 = load double* @lyd, align 8 + %cmp120 = fcmp oeq double %130, %131 + br label %land.end122 + +land.end122: ; preds = %land.rhs119, %land.lhs.true116, %land.end108 + %132 = phi i1 [ false, %land.lhs.true116 ], [ false, %land.end108 ], [ %cmp120, %land.rhs119 ] + %land.ext123 = zext i1 %132 to i32 + %call124 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %conv112, double %conv113, double %122, double %123, double %124, double %125, i32 %land.ext123) + call void @clear() + store double 1.561234e+01, double* @ret_df, align 8 + %call125 = call double @df_v() + store double %call125, double* @lret_df, align 8 + %133 = load double* @ret_df, align 8 + %134 = load double* @lret_df, align 8 + %135 = load double* @ret_df, align 8 + %136 = load double* @lret_df, align 8 + %cmp126 = fcmp oeq double %135, %136 + %conv127 = zext i1 %cmp126 to i32 + %call128 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), double %133, double %134, i32 %conv127) + call void @clear() + store double 1.345873e+01, double* @ret_df, align 8 + store float 3.434520e+05, float* @lx, align 4 + %137 = load float* @lx, align 4 + %call129 = call double @df_sf(float %137) + store double %call129, double* @lret_df, align 8 + %138 = load double* @ret_df, align 8 + %139 = load double* @lret_df, align 8 + %140 = load float* @x, align 4 + %conv130 = fpext float %140 to double + %141 = load float* @lx, align 4 + %conv131 = fpext float %141 to double + %142 = load double* @ret_df, align 8 + %143 = load double* @lret_df, align 8 + %cmp132 = fcmp oeq double %142, %143 + %conv133 = zext i1 %cmp132 to i32 + %144 = load float* @x, align 4 + %145 = load float* @lx, align 4 + %cmp134 = fcmp oeq float %144, %145 + %conv135 = zext i1 %cmp134 to i32 + %and136 = and i32 %conv133, %conv135 + %call137 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %138, double %139, double %conv130, double %conv131, i32 %and136) + call void @clear() + store double 0x4084F3AB7AA25D8D, double* @ret_df, align 8 + store double 0x4114F671D2F1A9FC, double* @lxd, align 8 + %146 = load double* @lxd, align 8 + %call138 = call double @df_df(double %146) + store double %call138, double* @lret_df, align 8 + %147 = load double* @ret_df, align 8 + %148 = load double* @lret_df, align 8 + %149 = load double* @xd, align 8 + %150 = load double* @lxd, align 8 + %151 = load double* @ret_df, align 8 + %152 = load double* @lret_df, align 8 + %cmp139 = fcmp oeq double %151, %152 + %conv140 = zext i1 %cmp139 to i32 + %153 = load double* @xd, align 8 + %154 = load double* @lxd, align 8 + %cmp141 = fcmp oeq double %153, %154 + %conv142 = zext i1 %cmp141 to i32 + %and143 = and i32 %conv140, %conv142 + %call144 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %147, double %148, double %149, double %150, i32 %and143) + call void @clear() + store double 6.781956e+03, double* @ret_df, align 8 + store float 4.445500e+03, float* @lx, align 4 + store float 0x4068ACCCC0000000, float* @ly, align 4 + %155 = load float* @lx, align 4 + %156 = load float* @ly, align 4 + %call145 = call double @df_sf_sf(float %155, float %156) + store double %call145, double* @lret_df, align 8 + %157 = load double* @ret_df, align 8 + %158 = load double* @lret_df, align 8 + %159 = load float* @x, align 4 + %conv146 = fpext float %159 to double + %160 = load float* @lx, align 4 + %conv147 = fpext float %160 to double + %161 = load float* @y, align 4 + %conv148 = fpext float %161 to double + %162 = load float* @ly, align 4 + %conv149 = fpext float %162 to double + %163 = load double* @ret_df, align 8 + %164 = load double* @lret_df, align 8 + %cmp150 = fcmp oeq double %163, %164 + br i1 %cmp150, label %land.lhs.true152, label %land.end158 + +land.lhs.true152: ; preds = %land.end122 + %165 = load float* @x, align 4 + %166 = load float* @lx, align 4 + %cmp153 = fcmp oeq float %165, %166 + br i1 %cmp153, label %land.rhs155, label %land.end158 + +land.rhs155: ; preds = %land.lhs.true152 + %167 = load float* @y, align 4 + %168 = load float* @ly, align 4 + %cmp156 = fcmp oeq float %167, %168 + br label %land.end158 + +land.end158: ; preds = %land.rhs155, %land.lhs.true152, %land.end122 + %169 = phi i1 [ false, %land.lhs.true152 ], [ false, %land.end122 ], [ %cmp156, %land.rhs155 ] + %land.ext159 = zext i1 %169 to i32 + %call160 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %157, double %158, double %conv146, double %conv147, double %conv148, double %conv149, i32 %land.ext159) + call void @clear() + store double 1.889130e+05, double* @ret_df, align 8 + store float 9.111450e+05, float* @lx, align 4 + store double 0x4185320A58000000, double* @lyd, align 8 + %170 = load float* @lx, align 4 + %171 = load double* @lyd, align 8 + %call161 = call double @df_sf_df(float %170, double %171) + store double %call161, double* @lret_df, align 8 + %172 = load double* @ret_df, align 8 + %173 = load double* @lret_df, align 8 + %174 = load float* @x, align 4 + %conv162 = fpext float %174 to double + %175 = load float* @lx, align 4 + %conv163 = fpext float %175 to double + %176 = load double* @yd, align 8 + %177 = load double* @lyd, align 8 + %178 = load double* @ret_df, align 8 + %179 = load double* @lret_df, align 8 + %cmp164 = fcmp oeq double %178, %179 + br i1 %cmp164, label %land.lhs.true166, label %land.end172 + +land.lhs.true166: ; preds = %land.end158 + %180 = load float* @x, align 4 + %181 = load float* @lx, align 4 + %cmp167 = fcmp oeq float %180, %181 + br i1 %cmp167, label %land.rhs169, label %land.end172 + +land.rhs169: ; preds = %land.lhs.true166 + %182 = load double* @yd, align 8 + %183 = load double* @lyd, align 8 + %cmp170 = fcmp oeq double %182, %183 + br label %land.end172 + +land.end172: ; preds = %land.rhs169, %land.lhs.true166, %land.end158 + %184 = phi i1 [ false, %land.lhs.true166 ], [ false, %land.end158 ], [ %cmp170, %land.rhs169 ] + %land.ext173 = zext i1 %184 to i32 + %call174 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %172, double %173, double %conv162, double %conv163, double %176, double %177, i32 %land.ext173) + call void @clear() + store double 0x418B2DB900000000, double* @ret_df, align 8 + store double 0x41B1EF2ED3000000, double* @lxd, align 8 + store float 1.244562e+06, float* @ly, align 4 + %185 = load double* @lxd, align 8 + %186 = load float* @ly, align 4 + %call175 = call double @df_df_sf(double %185, float %186) + store double %call175, double* @lret_df, align 8 + %187 = load double* @ret_df, align 8 + %188 = load double* @lret_df, align 8 + %189 = load double* @xd, align 8 + %190 = load double* @lxd, align 8 + %191 = load float* @y, align 4 + %conv176 = fpext float %191 to double + %192 = load float* @ly, align 4 + %conv177 = fpext float %192 to double + %193 = load double* @ret_df, align 8 + %194 = load double* @lret_df, align 8 + %cmp178 = fcmp oeq double %193, %194 + br i1 %cmp178, label %land.lhs.true180, label %land.end186 + +land.lhs.true180: ; preds = %land.end172 + %195 = load double* @xd, align 8 + %196 = load double* @lxd, align 8 + %cmp181 = fcmp oeq double %195, %196 + br i1 %cmp181, label %land.rhs183, label %land.end186 + +land.rhs183: ; preds = %land.lhs.true180 + %197 = load float* @y, align 4 + %198 = load float* @ly, align 4 + %cmp184 = fcmp oeq float %197, %198 + br label %land.end186 + +land.end186: ; preds = %land.rhs183, %land.lhs.true180, %land.end172 + %199 = phi i1 [ false, %land.lhs.true180 ], [ false, %land.end172 ], [ %cmp184, %land.rhs183 ] + %land.ext187 = zext i1 %199 to i32 + %call188 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %187, double %188, double %189, double %190, double %conv176, double %conv177, i32 %land.ext187) + call void @clear() + store double 3.987721e+06, double* @ret_df, align 8 + store double 5.223560e+00, double* @lxd, align 8 + store double 0x40B7D37CC1A8AC5C, double* @lyd, align 8 + %200 = load double* @lxd, align 8 + %201 = load double* @lyd, align 8 + %call189 = call double @df_df_df(double %200, double %201) + store double %call189, double* @lret_df, align 8 + %202 = load double* @ret_df, align 8 + %203 = load double* @lret_df, align 8 + %204 = load double* @xd, align 8 + %205 = load double* @lxd, align 8 + %206 = load double* @yd, align 8 + %207 = load double* @lyd, align 8 + %208 = load double* @ret_df, align 8 + %209 = load double* @lret_df, align 8 + %cmp190 = fcmp oeq double %208, %209 + br i1 %cmp190, label %land.lhs.true192, label %land.end198 + +land.lhs.true192: ; preds = %land.end186 + %210 = load double* @xd, align 8 + %211 = load double* @lxd, align 8 + %cmp193 = fcmp oeq double %210, %211 + br i1 %cmp193, label %land.rhs195, label %land.end198 + +land.rhs195: ; preds = %land.lhs.true192 + %212 = load double* @yd, align 8 + %213 = load double* @lyd, align 8 + %cmp196 = fcmp oeq double %212, %213 + br label %land.end198 + +land.end198: ; preds = %land.rhs195, %land.lhs.true192, %land.end186 + %214 = phi i1 [ false, %land.lhs.true192 ], [ false, %land.end186 ], [ %cmp196, %land.rhs195 ] + %land.ext199 = zext i1 %214 to i32 + %call200 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %202, double %203, double %204, double %205, double %206, double %207, i32 %land.ext199) + call void @clear() + store float 4.500000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0) + store float 7.000000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1) + %call201 = call { float, float } @sc_v() + %215 = extractvalue { float, float } %call201, 0 + %216 = extractvalue { float, float } %call201, 1 + store float %215, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0) + store float %216, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1) + %ret_sc.real = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0) + %ret_sc.imag = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1) + %conv202 = fpext float %ret_sc.real to double + %conv203 = fpext float %ret_sc.imag to double + %ret_sc.real204 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0) + %ret_sc.imag205 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1) + %conv206 = fpext float %ret_sc.real204 to double + %conv207 = fpext float %ret_sc.imag205 to double + %lret_sc.real = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0) + %lret_sc.imag = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1) + %conv208 = fpext float %lret_sc.real to double + %conv209 = fpext float %lret_sc.imag to double + %lret_sc.real210 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0) + %lret_sc.imag211 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1) + %conv212 = fpext float %lret_sc.real210 to double + %conv213 = fpext float %lret_sc.imag211 to double + %ret_sc.real214 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0) + %ret_sc.imag215 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1) + %lret_sc.real216 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0) + %lret_sc.imag217 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1) + %cmp.r = fcmp oeq float %ret_sc.real214, %lret_sc.real216 + %cmp.i = fcmp oeq float %ret_sc.imag215, %lret_sc.imag217 + %and.ri = and i1 %cmp.r, %cmp.i + %conv218 = zext i1 %and.ri to i32 + %call219 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8]* @.str3, i32 0, i32 0), double %conv202, double %conv207, double %conv208, double %conv213, i32 %conv218) + call void @clear() + store float 0x3FF7A99300000000, float* @lx, align 4 + store float 4.500000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0) + store float 7.000000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1) + %217 = load float* @lx, align 4 + %call220 = call { float, float } @sc_sf(float %217) + %218 = extractvalue { float, float } %call220, 0 + %219 = extractvalue { float, float } %call220, 1 + store float %218, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0) + store float %219, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1) + %ret_sc.real221 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0) + %ret_sc.imag222 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1) + %conv223 = fpext float %ret_sc.real221 to double + %conv224 = fpext float %ret_sc.imag222 to double + %ret_sc.real225 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0) + %ret_sc.imag226 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1) + %conv227 = fpext float %ret_sc.real225 to double + %conv228 = fpext float %ret_sc.imag226 to double + %lret_sc.real229 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0) + %lret_sc.imag230 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1) + %conv231 = fpext float %lret_sc.real229 to double + %conv232 = fpext float %lret_sc.imag230 to double + %lret_sc.real233 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0) + %lret_sc.imag234 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1) + %conv235 = fpext float %lret_sc.real233 to double + %conv236 = fpext float %lret_sc.imag234 to double + %220 = load float* @x, align 4 + %conv237 = fpext float %220 to double + %221 = load float* @lx, align 4 + %conv238 = fpext float %221 to double + %ret_sc.real239 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0) + %ret_sc.imag240 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1) + %lret_sc.real241 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0) + %lret_sc.imag242 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1) + %cmp.r243 = fcmp oeq float %ret_sc.real239, %lret_sc.real241 + %cmp.i244 = fcmp oeq float %ret_sc.imag240, %lret_sc.imag242 + %and.ri245 = and i1 %cmp.r243, %cmp.i244 + br i1 %and.ri245, label %land.rhs247, label %land.end250 + +land.rhs247: ; preds = %land.end198 + %222 = load float* @x, align 4 + %223 = load float* @lx, align 4 + %cmp248 = fcmp oeq float %222, %223 + br label %land.end250 + +land.end250: ; preds = %land.rhs247, %land.end198 + %224 = phi i1 [ false, %land.end198 ], [ %cmp248, %land.rhs247 ] + %land.ext251 = zext i1 %224 to i32 + %call252 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([24 x i8]* @.str4, i32 0, i32 0), double %conv223, double %conv228, double %conv231, double %conv236, double %conv237, double %conv238, i32 %land.ext251) + call void @clear() + store double 1.234500e+03, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0) + store double 7.677000e+03, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1) + %call253 = call { double, double } @dc_v() + %225 = extractvalue { double, double } %call253, 0 + %226 = extractvalue { double, double } %call253, 1 + store double %225, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0) + store double %226, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1) + %ret_dc.real = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0) + %ret_dc.imag = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1) + %ret_dc.real254 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0) + %ret_dc.imag255 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1) + %lret_dc.real = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0) + %lret_dc.imag = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1) + %lret_dc.real256 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0) + %lret_dc.imag257 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1) + %ret_dc.real258 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0) + %ret_dc.imag259 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1) + %lret_dc.real260 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0) + %lret_dc.imag261 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1) + %cmp.r262 = fcmp oeq double %ret_dc.real258, %lret_dc.real260 + %cmp.i263 = fcmp oeq double %ret_dc.imag259, %lret_dc.imag261 + %and.ri264 = and i1 %cmp.r262, %cmp.i263 + %conv265 = zext i1 %and.ri264 to i32 + %call266 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8]* @.str3, i32 0, i32 0), double %ret_dc.real, double %ret_dc.imag255, double %lret_dc.real, double %lret_dc.imag257, i32 %conv265) + call void @clear() + store double 0x40AAF6F532617C1C, double* @lxd, align 8 + store double 4.444500e+03, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0) + store double 7.888000e+03, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1) + %227 = load float* @lx, align 4 + %call267 = call { double, double } @dc_sf(float %227) + %228 = extractvalue { double, double } %call267, 0 + %229 = extractvalue { double, double } %call267, 1 + store double %228, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0) + store double %229, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1) + %ret_dc.real268 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0) + %ret_dc.imag269 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1) + %ret_dc.real270 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0) + %ret_dc.imag271 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1) + %lret_dc.real272 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0) + %lret_dc.imag273 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1) + %lret_dc.real274 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0) + %lret_dc.imag275 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1) + %230 = load float* @x, align 4 + %conv276 = fpext float %230 to double + %231 = load float* @lx, align 4 + %conv277 = fpext float %231 to double + %ret_dc.real278 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0) + %ret_dc.imag279 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1) + %lret_dc.real280 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0) + %lret_dc.imag281 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1) + %cmp.r282 = fcmp oeq double %ret_dc.real278, %lret_dc.real280 + %cmp.i283 = fcmp oeq double %ret_dc.imag279, %lret_dc.imag281 + %and.ri284 = and i1 %cmp.r282, %cmp.i283 + br i1 %and.ri284, label %land.rhs286, label %land.end289 + +land.rhs286: ; preds = %land.end250 + %232 = load float* @x, align 4 + %233 = load float* @lx, align 4 + %cmp287 = fcmp oeq float %232, %233 + br label %land.end289 + +land.end289: ; preds = %land.rhs286, %land.end250 + %234 = phi i1 [ false, %land.end250 ], [ %cmp287, %land.rhs286 ] + %land.ext290 = zext i1 %234 to i32 + %call291 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([24 x i8]* @.str4, i32 0, i32 0), double %ret_dc.real268, double %ret_dc.imag271, double %lret_dc.real272, double %lret_dc.imag275, double %conv276, double %conv277, i32 %land.ext290) + %235 = load i32* %retval + ret i32 %235 +} + +declare void @v_sf(float) #1 +; stel: .section .mips16.call.fp.v_sf,"ax",@progbits +; stel: .ent __call_stub_v_sf +; stel: mtc1 $4,$f12 +; stel: lui $25,%hi(v_sf) +; stel: addiu $25,$25,%lo(v_sf) +; stel: jr $25 +; stel: .end __call_stub_v_sf + +declare i32 @printf(i8*, ...) #1 + +declare void @v_df(double) #1 +; stel: .section .mips16.call.fp.v_df,"ax",@progbits +; stel: .ent __call_stub_v_df +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f13 +; stel: lui $25,%hi(v_df) +; stel: addiu $25,$25,%lo(v_df) +; stel: jr $25 +; stel: .end __call_stub_v_df + +declare void @v_sf_sf(float, float) #1 +; stel: .section .mips16.call.fp.v_sf_sf,"ax",@progbits +; stel: .ent __call_stub_v_sf_sf +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f14 +; stel: lui $25,%hi(v_sf_sf) +; stel: addiu $25,$25,%lo(v_sf_sf) +; stel: jr $25 +; stel: .end __call_stub_v_sf_sf + +declare void @v_sf_df(float, double) #1 +; stel: .section .mips16.call.fp.v_sf_df,"ax",@progbits +; stel: .ent __call_stub_v_sf_df +; stel: mtc1 $4,$f12 +; stel: mtc1 $6,$f14 +; stel: mtc1 $7,$f15 +; stel: lui $25,%hi(v_sf_df) +; stel: addiu $25,$25,%lo(v_sf_df) +; stel: jr $25 +; stel: .end __call_stub_v_sf_df + +declare void @v_df_sf(double, float) #1 +; stel: .section .mips16.call.fp.v_df_sf,"ax",@progbits +; stel: .ent __call_stub_v_df_sf +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f13 +; stel: mtc1 $6,$f14 +; stel: lui $25,%hi(v_df_sf) +; stel: addiu $25,$25,%lo(v_df_sf) +; stel: jr $25 +; stel: .end __call_stub_v_df_sf + +declare void @v_df_df(double, double) #1 +; stel: .section .mips16.call.fp.v_df_df,"ax",@progbits +; stel: .ent __call_stub_v_df_df +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f13 +; stel: mtc1 $6,$f14 +; stel: mtc1 $7,$f15 +; stel: lui $25,%hi(v_df_df) +; stel: addiu $25,$25,%lo(v_df_df) +; stel: jr $25 +; stel: .end __call_stub_v_df_df + +declare float @sf_v() #1 +; stel: .section .mips16.call.fp.sf_v,"ax",@progbits +; stel: .ent __call_stub_sf_v +; stel: move $18, $31 +; stel: jal sf_v +; stel: mfc1 $2,$f0 +; stel: jr $18 +; stel: .end __call_stub_sf_v + +declare float @sf_sf(float) #1 +; stel: .section .mips16.call.fp.sf_sf,"ax",@progbits +; stel: .ent __call_stub_sf_sf +; stel: mtc1 $4,$f12 +; stel: move $18, $31 +; stel: jal sf_sf +; stel: mfc1 $2,$f0 +; stel: jr $18 +; stel: .end __call_stub_sf_sf + +declare float @sf_df(double) #1 +; stel: .section .mips16.call.fp.sf_df,"ax",@progbits +; stel: .ent __call_stub_sf_df +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f13 +; stel: move $18, $31 +; stel: jal sf_df +; stel: mfc1 $2,$f0 +; stel: jr $18 +; stel: .end __call_stub_sf_df + +declare float @sf_sf_sf(float, float) #1 +; stel: .section .mips16.call.fp.sf_sf_sf,"ax",@progbits +; stel: .ent __call_stub_sf_sf_sf +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f14 +; stel: move $18, $31 +; stel: jal sf_sf_sf +; stel: mfc1 $2,$f0 +; stel: jr $18 +; stel: .end __call_stub_sf_sf_sf + +declare float @sf_sf_df(float, double) #1 +; stel: .section .mips16.call.fp.sf_sf_df,"ax",@progbits +; stel: .ent __call_stub_sf_sf_df +; stel: mtc1 $4,$f12 +; stel: mtc1 $6,$f14 +; stel: mtc1 $7,$f15 +; stel: move $18, $31 +; stel: jal sf_sf_df +; stel: mfc1 $2,$f0 +; stel: jr $18 +; stel: .end __call_stub_sf_sf_df + +declare float @sf_df_sf(double, float) #1 +; stel: .section .mips16.call.fp.sf_df_sf,"ax",@progbits +; stel: .ent __call_stub_sf_df_sf +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f13 +; stel: mtc1 $6,$f14 +; stel: move $18, $31 +; stel: jal sf_df_sf +; stel: mfc1 $2,$f0 +; stel: jr $18 +; stel: .end __call_stub_sf_df_sf + +declare float @sf_df_df(double, double) #1 +; stel: .section .mips16.call.fp.sf_df_df,"ax",@progbits +; stel: .ent __call_stub_sf_df_df +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f13 +; stel: mtc1 $6,$f14 +; stel: mtc1 $7,$f15 +; stel: move $18, $31 +; stel: jal sf_df_df +; stel: mfc1 $2,$f0 +; stel: jr $18 +; stel: .end __call_stub_sf_df_df + +declare double @df_v() #1 +; stel: .section .mips16.call.fp.df_v,"ax",@progbits +; stel: .ent __call_stub_df_v +; stel: move $18, $31 +; stel: jal df_v +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f1 +; stel: jr $18 +; stel: .end __call_stub_df_v + +declare double @df_sf(float) #1 +; stel: .section .mips16.call.fp.df_sf,"ax",@progbits +; stel: .ent __call_stub_df_sf +; stel: mtc1 $4,$f12 +; stel: move $18, $31 +; stel: jal df_sf +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f1 +; stel: jr $18 +; stel: .end __call_stub_df_sf + +declare double @df_df(double) #1 +; stel: .section .mips16.call.fp.df_df,"ax",@progbits +; stel: .ent __call_stub_df_df +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f13 +; stel: move $18, $31 +; stel: jal df_df +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f1 +; stel: jr $18 +; stel: .end __call_stub_df_df + +declare double @df_sf_sf(float, float) #1 +; stel: .section .mips16.call.fp.df_sf_sf,"ax",@progbits +; stel: .ent __call_stub_df_sf_sf +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f14 +; stel: move $18, $31 +; stel: jal df_sf_sf +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f1 +; stel: jr $18 +; stel: .end __call_stub_df_sf_sf + +declare double @df_sf_df(float, double) #1 +; stel: .section .mips16.call.fp.df_sf_df,"ax",@progbits +; stel: .ent __call_stub_df_sf_df +; stel: mtc1 $4,$f12 +; stel: mtc1 $6,$f14 +; stel: mtc1 $7,$f15 +; stel: move $18, $31 +; stel: jal df_sf_df +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f1 +; stel: jr $18 +; stel: .end __call_stub_df_sf_df + +declare double @df_df_sf(double, float) #1 +; stel: .section .mips16.call.fp.df_df_sf,"ax",@progbits +; stel: .ent __call_stub_df_df_sf +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f13 +; stel: mtc1 $6,$f14 +; stel: move $18, $31 +; stel: jal df_df_sf +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f1 +; stel: jr $18 +; stel: .end __call_stub_df_df_sf + +declare double @df_df_df(double, double) #1 +; stel: .section .mips16.call.fp.df_df_df,"ax",@progbits +; stel: .ent __call_stub_df_df_df +; stel: mtc1 $4,$f12 +; stel: mtc1 $5,$f13 +; stel: mtc1 $6,$f14 +; stel: mtc1 $7,$f15 +; stel: move $18, $31 +; stel: jal df_df_df +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f1 +; stel: jr $18 +; stel: .end __call_stub_df_df_df + +declare { float, float } @sc_v() #1 +; stel: .section .mips16.call.fp.sc_v,"ax",@progbits +; stel: .ent __call_stub_sc_v +; stel: move $18, $31 +; stel: jal sc_v +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f2 +; stel: jr $18 +; stel: .end __call_stub_sc_v + +declare { float, float } @sc_sf(float) #1 +; stel: .section .mips16.call.fp.sc_sf,"ax",@progbits +; stel: .ent __call_stub_sc_sf +; stel: mtc1 $4,$f12 +; stel: move $18, $31 +; stel: jal sc_sf +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f2 +; stel: jr $18 +; stel: .end __call_stub_sc_sf + +declare { double, double } @dc_v() #1 +; stel: .section .mips16.call.fp.dc_v,"ax",@progbits +; stel: .ent __call_stub_dc_v +; stel: move $18, $31 +; stel: jal dc_v +; stel: mfc1 $4,$f2 +; stel: mfc1 $5,$f3 +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f1 +; stel: jr $18 +; stel: .end __call_stub_dc_v + +declare { double, double } @dc_sf(float) #1 +; stel: .section .mips16.call.fp.dc_sf,"ax",@progbits +; stel: .ent __call_stub_dc_sf +; stel: mtc1 $4,$f12 +; stel: move $18, $31 +; stel: jal dc_sf +; stel: mfc1 $4,$f2 +; stel: mfc1 $5,$f3 +; stel: mfc1 $2,$f0 +; stel: mfc1 $3,$f1 +; stel: jr $18 +; stel: .end __call_stub_dc_sf + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -- cgit v1.2.3 From 5427aa88d5930655ef9e958446489acc1bf9a160 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Tue, 14 May 2013 02:13:45 +0000 Subject: Removed an unnamed namespace and forgot to make two of the functions inside "static". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181754 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16HardFloat.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/lib/Target/Mips/Mips16HardFloat.cpp b/lib/Target/Mips/Mips16HardFloat.cpp index 304715aaa4..e4ff4c49d6 100644 --- a/lib/Target/Mips/Mips16HardFloat.cpp +++ b/lib/Target/Mips/Mips16HardFloat.cpp @@ -175,8 +175,9 @@ static bool needsFPHelperFromSig(Function &F) { // interoperate // -void swapFPIntParams(FPParamVariant PV, Module *M, InlineAsmHelper &IAH, - bool LE, bool ToFP) { +static void swapFPIntParams + (FPParamVariant PV, Module *M, InlineAsmHelper &IAH, + bool LE, bool ToFP) { //LLVMContext &Context = M->getContext(); std::string MI = ToFP? "mtc1 ": "mfc1 "; switch (PV) { @@ -237,7 +238,8 @@ void swapFPIntParams(FPParamVariant PV, Module *M, InlineAsmHelper &IAH, // Make sure that we know we already need a stub for this function. // Having called needsFPHelperFromSig // -void assureFPCallStub(Function &F, Module *M, const MipsSubtarget &Subtarget){ +static void assureFPCallStub(Function &F, Module *M, + const MipsSubtarget &Subtarget){ // for now we only need them for static relocation if (!Subtarget.getRelocationModel() == Reloc::PIC_) return; -- cgit v1.2.3 From 0b95db8f2654cd19c029d024d931013bb7ecc14d Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Tue, 14 May 2013 06:00:01 +0000 Subject: Fix typo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181759 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16HardFloat.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/Mips/Mips16HardFloat.cpp b/lib/Target/Mips/Mips16HardFloat.cpp index e4ff4c49d6..cc7324f26e 100644 --- a/lib/Target/Mips/Mips16HardFloat.cpp +++ b/lib/Target/Mips/Mips16HardFloat.cpp @@ -241,7 +241,7 @@ static void swapFPIntParams static void assureFPCallStub(Function &F, Module *M, const MipsSubtarget &Subtarget){ // for now we only need them for static relocation - if (!Subtarget.getRelocationModel() == Reloc::PIC_) + if (Subtarget.getRelocationModel() == Reloc::PIC_) return; LLVMContext &Context = M->getContext(); bool LE = Subtarget.isLittle(); -- cgit v1.2.3 From cbe5f4c5d7a04d15dcc89a3f1de0936e5db54da7 Mon Sep 17 00:00:00 2001 From: Michael Gottesman Date: Tue, 14 May 2013 06:40:10 +0000 Subject: Removed trailing whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181760 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/ObjCARC/ObjCARCOpts.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp index 5db4797aeb..878da7d74c 100644 --- a/lib/Transforms/ObjCARC/ObjCARCOpts.cpp +++ b/lib/Transforms/ObjCARC/ObjCARCOpts.cpp @@ -269,19 +269,19 @@ static inline bool AreAnyUnderlyingObjectsAnAlloca(const Value *V) { do { const Value *P = Worklist.pop_back_val(); P = GetUnderlyingObjCPtr(P); - + if (isa(P)) return true; - + if (!Visited.insert(P)) continue; - + if (const SelectInst *SI = dyn_cast(P)) { Worklist.push_back(SI->getTrueValue()); Worklist.push_back(SI->getFalseValue()); continue; } - + if (const PHINode *PN = dyn_cast(P)) { for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) Worklist.push_back(PN->getIncomingValue(i)); -- cgit v1.2.3 From 055ac429cc995c78be4aee552ea51be7b32efbf1 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 14 May 2013 09:28:21 +0000 Subject: [SystemZ] Match operands to fields by name rather than by order The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181769 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp | 72 +++- lib/Target/SystemZ/SystemZInstrFP.td | 49 ++- lib/Target/SystemZ/SystemZInstrFormats.td | 428 ++++++++++----------- lib/Target/SystemZ/SystemZInstrInfo.td | 76 ++-- lib/Target/SystemZ/SystemZOperands.td | 13 +- 5 files changed, 326 insertions(+), 312 deletions(-) diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp index ea2250f546..70a3eb9420 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp @@ -45,30 +45,43 @@ private: // Called by the TableGen code to get the binary encoding of operand // MO in MI. Fixups is the list of fixups against MI. - unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, + uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups) const; + // Called by the TableGen code to get the binary encoding of an address. + // The index, if any, is encoded first, followed by the base, + // followed by the displacement. In a 20-bit displacement, + // the low 12 bits are encoded before the high 8 bits. + uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups) const; + uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups) const; + uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups) const; + uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups) const; + // Operand OpNum of MI needs a PC-relative fixup of kind Kind at // Offset bytes from the start of MI. Add the fixup to Fixups // and return the in-place addend, which since we're a RELA target // is always 0. - unsigned getPCRelEncoding(const MCInst &MI, unsigned int OpNum, + uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups, unsigned Kind, int64_t Offset) const; - unsigned getPC16DBLEncoding(const MCInst &MI, unsigned int OpNum, + uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups) const { return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2); } - unsigned getPC32DBLEncoding(const MCInst &MI, unsigned int OpNum, + uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups) const { return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2); } - unsigned getPLT16DBLEncoding(const MCInst &MI, unsigned int OpNum, + uint64_t getPLT16DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups) const { return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PLT16DBL, 2); } - unsigned getPLT32DBLEncoding(const MCInst &MI, unsigned int OpNum, + uint64_t getPLT32DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups) const { return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PLT32DBL, 2); } @@ -95,18 +108,57 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, } } -unsigned SystemZMCCodeEmitter:: +uint64_t SystemZMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups) const { if (MO.isReg()) return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()); if (MO.isImm()) - return static_cast(MO.getImm()); + return static_cast(MO.getImm()); llvm_unreachable("Unexpected operand type!"); } -unsigned -SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned int OpNum, +uint64_t SystemZMCCodeEmitter:: +getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); + assert(isUInt<4>(Base) && isUInt<12>(Disp)); + return (Base << 12) | Disp; +} + +uint64_t SystemZMCCodeEmitter:: +getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); + assert(isUInt<4>(Base) && isInt<20>(Disp)); + return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); +} + +uint64_t SystemZMCCodeEmitter:: +getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); + uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups); + assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); + return (Index << 16) | (Base << 12) | Disp; +} + +uint64_t SystemZMCCodeEmitter:: +getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); + uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups); + assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index)); + return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8) + | ((Disp & 0xff000) >> 12); +} + +uint64_t +SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups, unsigned Kind, int64_t Offset) const { const MCOperand &MO = MI.getOperand(OpNum); diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td index 7c9f0e668b..104af6e99d 100644 --- a/lib/Target/SystemZ/SystemZInstrFP.td +++ b/lib/Target/SystemZ/SystemZInstrFP.td @@ -40,24 +40,22 @@ def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>; // fcopysign with an FP32 result. let isCodeGenOnly = 1 in { - def CPSDRss : BinaryRevRRF<"cpsdr", 0xB372, fcopysign, FP32, FP32>; - def CPSDRsd : BinaryRevRRF<"cpsdr", 0xB372, fcopysign, FP32, FP64>; + def CPSDRss : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP32, FP32>; + def CPSDRsd : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP32, FP64>; } -// The sign of an FP128 is in the high register. Give the CPSDRsd -// operands in R1, R2, R3 order. +// The sign of an FP128 is in the high register. def : Pat<(fcopysign FP32:$src1, FP128:$src2), - (CPSDRsd (EXTRACT_SUBREG FP128:$src2, subreg_high), FP32:$src1)>; + (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>; // fcopysign with an FP64 result. let isCodeGenOnly = 1 in - def CPSDRds : BinaryRevRRF<"cpsdr", 0xB372, fcopysign, FP64, FP32>; -def CPSDRdd : BinaryRevRRF<"cpsdr", 0xB372, fcopysign, FP64, FP64>; + def CPSDRds : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP64, FP32>; +def CPSDRdd : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP64, FP64>; -// The sign of an FP128 is in the high register. Give the CPSDRdd -// operands in R1, R2, R3 order. +// The sign of an FP128 is in the high register. def : Pat<(fcopysign FP64:$src1, FP128:$src2), - (CPSDRdd (EXTRACT_SUBREG FP128:$src2, subreg_high), FP64:$src1)>; + (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>; // fcopysign with an FP128 result. Use "upper" as the high half and leave // the low half as-is. @@ -65,13 +63,12 @@ class CopySign128 : Pat<(fcopysign FP128:$src1, cls:$src2), (INSERT_SUBREG FP128:$src1, upper, subreg_high)>; -// Give the CPSDR* operands in R1, R2, R3 order. -def : CopySign128; -def : CopySign128; -def : CopySign128; +def : CopySign128; +def : CopySign128; +def : CopySign128; //===----------------------------------------------------------------------===// // Load instructions @@ -155,13 +152,13 @@ let Defs = [PSW] in { } // fp_to_sint always rounds towards zero, which is modifier value 5. -def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR FP32:$src, 5)>; -def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR FP64:$src, 5)>; -def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR FP128:$src, 5)>; +def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; +def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; +def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; -def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR FP32:$src, 5)>; -def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR FP64:$src, 5)>; -def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR FP128:$src, 5)>; +def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; +def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; +def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; //===----------------------------------------------------------------------===// // Unary arithmetic @@ -210,9 +207,9 @@ let Defs = [PSW] in { // frint rounds according to the current mode (modifier 0) and detects // inexact conditions. -def : Pat<(frint FP32:$src), (FIEBR FP32:$src, 0)>; -def : Pat<(frint FP64:$src), (FIDBR FP64:$src, 0)>; -def : Pat<(frint FP128:$src), (FIXBR FP128:$src, 0)>; +def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; +def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; +def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; //===----------------------------------------------------------------------===// // Binary arithmetic diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index b32b7eb0fc..b7511d50ff 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -82,19 +82,17 @@ def getDisp20Opcode : InstrMapping { // // Formats are specified using operand field declarations of the form: // -// bits<4> Rn : register input or output for operand n -// bits In : immediate value of width m for operand n -// bits<4> Bn : base register for address operand n -// bits Dn : displacement value of width m for address operand n -// bits<4> Xn : index register for address operand n -// bits<4> Mn : mode value for operand n +// bits<4> Rn : register input or output for operand n +// bits In : immediate value of width m for operand n +// bits<4> BDn : address operand n, which has a base and a displacement +// bits XBDn : address operand n, which has an index, a base and a +// displacement +// bits<4> Xn : index register for address operand n +// bits<4> Mn : mode value for operand n // -// The operand numbers ("n" in the list above) follow the architecture manual, -// but the fields are always declared in assembly order, so there are some -// cases where operand "2" comes after operand "3". For address operands, -// the base register field is declared first, followed by the displacement, -// followed by the index (if any). This matches the bdaddr* and bdxaddr* -// orders. +// The operand numbers ("n" in the list above) follow the architecture manual. +// Assembly operands sometimes have a different order; in particular, R3 often +// is often written between operands 1 and 2. // //===----------------------------------------------------------------------===// @@ -203,15 +201,11 @@ class InstRX op, dag outs, dag ins, string asmstr, list pattern> field bits<32> Inst; bits<4> R1; - bits<4> B2; - bits<12> D2; - bits<4> X2; + bits<20> XBD2; let Inst{31-24} = op; let Inst{23-20} = R1; - let Inst{19-16} = X2; - let Inst{15-12} = B2; - let Inst{11-0} = D2; + let Inst{19-0} = XBD2; let HasIndex = 1; } @@ -221,15 +215,11 @@ class InstRXE op, dag outs, dag ins, string asmstr, list pattern> field bits<48> Inst; bits<4> R1; - bits<4> B2; - bits<12> D2; - bits<4> X2; + bits<20> XBD2; let Inst{47-40} = op{15-8}; let Inst{39-36} = R1; - let Inst{35-32} = X2; - let Inst{31-28} = B2; - let Inst{27-16} = D2; + let Inst{35-16} = XBD2; let Inst{15-8} = 0; let Inst{7-0} = op{7-0}; @@ -242,15 +232,11 @@ class InstRXF op, dag outs, dag ins, string asmstr, list pattern> bits<4> R1; bits<4> R3; - bits<4> B2; - bits<12> D2; - bits<4> X2; + bits<20> XBD2; let Inst{47-40} = op{15-8}; let Inst{39-36} = R3; - let Inst{35-32} = X2; - let Inst{31-28} = B2; - let Inst{27-16} = D2; + let Inst{35-16} = XBD2; let Inst{15-12} = R1; let Inst{11-8} = 0; let Inst{7-0} = op{7-0}; @@ -263,16 +249,11 @@ class InstRXY op, dag outs, dag ins, string asmstr, list pattern> field bits<48> Inst; bits<4> R1; - bits<4> B2; - bits<20> D2; - bits<4> X2; + bits<28> XBD2; let Inst{47-40} = op{15-8}; let Inst{39-36} = R1; - let Inst{35-32} = X2; - let Inst{31-28} = B2; - let Inst{27-16} = D2{11-0}; - let Inst{15-8} = D2{19-12}; + let Inst{35-8} = XBD2; let Inst{7-0} = op{7-0}; let Has20BitOffset = 1; @@ -285,14 +266,12 @@ class InstRS op, dag outs, dag ins, string asmstr, list pattern> bits<4> R1; bits<4> R3; - bits<4> B2; - bits<12> D2; + bits<16> BD2; let Inst{31-24} = op; let Inst{23-20} = R1; let Inst{19-16} = R3; - let Inst{15-12} = B2; - let Inst{11-0} = D2; + let Inst{15-0} = BD2; } class InstRSY op, dag outs, dag ins, string asmstr, list pattern> @@ -301,15 +280,12 @@ class InstRSY op, dag outs, dag ins, string asmstr, list pattern> bits<4> R1; bits<4> R3; - bits<4> B2; - bits<20> D2; + bits<24> BD2; let Inst{47-40} = op{15-8}; let Inst{39-36} = R1; let Inst{35-32} = R3; - let Inst{31-28} = B2; - let Inst{27-16} = D2{11-0}; - let Inst{15-8} = D2{19-12}; + let Inst{31-8} = BD2; let Inst{7-0} = op{7-0}; let Has20BitOffset = 1; @@ -319,27 +295,23 @@ class InstSI op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; - bits<4> B1; - bits<12> D1; + bits<16> BD1; bits<8> I2; let Inst{31-24} = op; let Inst{23-16} = I2; - let Inst{15-12} = B1; - let Inst{11-0} = D1; + let Inst{15-0} = BD1; } class InstSIL op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; - bits<4> B1; - bits<12> D1; + bits<16> BD1; bits<16> I2; let Inst{47-32} = op; - let Inst{31-28} = B1; - let Inst{27-16} = D1; + let Inst{31-16} = BD1; let Inst{15-0} = I2; } @@ -347,15 +319,12 @@ class InstSIY op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; - bits<4> B1; - bits<20> D1; + bits<24> BD1; bits<8> I2; let Inst{47-40} = op{15-8}; let Inst{39-32} = I2; - let Inst{31-28} = B1; - let Inst{27-16} = D1{11-0}; - let Inst{15-8} = D1{19-12}; + let Inst{31-8} = BD1; let Inst{7-0} = op{7-0}; let Has20BitOffset = 1; @@ -432,23 +401,23 @@ class InstSIY op, dag outs, dag ins, string asmstr, list pattern> class InherentRRE opcode, RegisterOperand cls, dag src> - : InstRRE { + : InstRRE { let R2 = 0; } class LoadMultipleRSY opcode, RegisterOperand cls> - : InstRSY { + : InstRSY { let mayLoad = 1; } class StoreRILPC opcode, SDPatternOperator operator, RegisterOperand cls> - : InstRIL { + : InstRIL { let mayStore = 1; // We want PC-relative addresses to be tried ahead of BD and BDX addresses. // However, BDXs have two extra operands and are therefore 6 units more @@ -458,17 +427,17 @@ class StoreRILPC opcode, SDPatternOperator operator, class StoreRX opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode = bdxaddr12only> - : InstRX { + : InstRX { let mayStore = 1; } class StoreRXY opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode = bdxaddr20only> - : InstRXY { + : InstRXY { let mayStore = 1; } @@ -483,32 +452,32 @@ multiclass StoreRXPair rxOpcode, bits<16> rxyOpcode, } class StoreMultipleRSY opcode, RegisterOperand cls> - : InstRSY { + : InstRSY { let mayStore = 1; } class StoreSI opcode, SDPatternOperator operator, Immediate imm, AddressingMode mode = bdaddr12only> - : InstSI { + : InstSI { let mayStore = 1; } class StoreSIY opcode, SDPatternOperator operator, Immediate imm, AddressingMode mode = bdaddr20only> - : InstSIY { + : InstSIY { let mayStore = 1; } class StoreSIL opcode, SDPatternOperator operator, Immediate imm> - : InstSIL { + : InstSIL { let mayStore = 1; } @@ -524,38 +493,38 @@ multiclass StoreSIPair siOpcode, bits<16> siyOpcode, class UnaryRR opcode, SDPatternOperator operator, RegisterOperand cls1, RegisterOperand cls2> - : InstRR; + : InstRR; class UnaryRRE opcode, SDPatternOperator operator, RegisterOperand cls1, RegisterOperand cls2> - : InstRRE; + : InstRRE; class UnaryRRF opcode, RegisterOperand cls1, RegisterOperand cls2> - : InstRRF; + : InstRRF; class UnaryRI opcode, SDPatternOperator operator, RegisterOperand cls, Immediate imm> - : InstRI; + : InstRI; class UnaryRIL opcode, SDPatternOperator operator, RegisterOperand cls, Immediate imm> - : InstRIL; + : InstRIL; class UnaryRILPC opcode, SDPatternOperator operator, RegisterOperand cls> - : InstRIL { + : InstRIL { let mayLoad = 1; // We want PC-relative addresses to be tried ahead of BD and BDX addresses. // However, BDXs have two extra operands and are therefore 6 units more @@ -565,25 +534,25 @@ class UnaryRILPC opcode, SDPatternOperator operator, class UnaryRX opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode = bdxaddr12only> - : InstRX { + : InstRX { let mayLoad = 1; } class UnaryRXE opcode, SDPatternOperator operator, RegisterOperand cls> - : InstRXE { + : InstRXE { let mayLoad = 1; } class UnaryRXY opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode = bdxaddr20only> - : InstRXY { + : InstRXY { let mayLoad = 1; } @@ -599,83 +568,76 @@ multiclass UnaryRXPair rxOpcode, bits<16> rxyOpcode, class BinaryRR opcode, SDPatternOperator operator, RegisterOperand cls1, RegisterOperand cls2> - : InstRR { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRR { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; } class BinaryRRE opcode, SDPatternOperator operator, RegisterOperand cls1, RegisterOperand cls2> - : InstRRE { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRRE { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; } -// Here the assembly and dag operands are in natural order, -// but the first input operand maps to R3 and the second to R2. -// This is used for "CPSDR R1, R3, R2", which is equivalent to -// R1 = copysign (R3, R2). -// -// Direct uses of the instruction must pass operands in encoding order -- -// R1, R2, R3 -- so they must pass the source operands in reverse order. -class BinaryRevRRF opcode, SDPatternOperator operator, - RegisterOperand cls1, RegisterOperand cls2> - : InstRRF; +class BinaryRRF opcode, SDPatternOperator operator, + RegisterOperand cls1, RegisterOperand cls2> + : InstRRF; class BinaryRI opcode, SDPatternOperator operator, RegisterOperand cls, Immediate imm> - : InstRI { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRI { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; } class BinaryRIL opcode, SDPatternOperator operator, RegisterOperand cls, Immediate imm> - : InstRIL { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRIL { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; } class BinaryRX opcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load, AddressingMode mode = bdxaddr12only> - : InstRX { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRX { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; let mayLoad = 1; } class BinaryRXE opcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load> - : InstRXE { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRXE { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; let mayLoad = 1; } class BinaryRXY opcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load, AddressingMode mode = bdxaddr20only> - : InstRXY { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRXY { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; let mayLoad = 1; } @@ -693,18 +655,18 @@ multiclass BinaryRXPair rxOpcode, bits<16> rxyOpcode, class BinarySI opcode, SDPatternOperator operator, Operand imm, AddressingMode mode = bdaddr12only> - : InstSI { + : InstSI { let mayLoad = 1; let mayStore = 1; } class BinarySIY opcode, SDPatternOperator operator, Operand imm, AddressingMode mode = bdaddr20only> - : InstSIY { + : InstSIY { let mayLoad = 1; let mayStore = 1; } @@ -722,49 +684,49 @@ multiclass BinarySIPair siOpcode, class ShiftRS opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode> - : InstRS { + : InstRS { let R3 = 0; - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; } class ShiftRSY opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode> - : InstRSY; + : InstRSY; class CompareRR opcode, SDPatternOperator operator, RegisterOperand cls1, RegisterOperand cls2> - : InstRR; + : InstRR; class CompareRRE opcode, SDPatternOperator operator, RegisterOperand cls1, RegisterOperand cls2> - : InstRRE; + : InstRRE; class CompareRI opcode, SDPatternOperator operator, RegisterOperand cls, Immediate imm> - : InstRI; + : InstRI; class CompareRIL opcode, SDPatternOperator operator, RegisterOperand cls, Immediate imm> - : InstRIL; + : InstRIL; class CompareRILPC opcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load> - : InstRIL { + : InstRIL { let mayLoad = 1; // We want PC-relative addresses to be tried ahead of BD and BDX addresses. // However, BDXs have two extra operands and are therefore 6 units more @@ -775,26 +737,26 @@ class CompareRILPC opcode, SDPatternOperator operator, class CompareRX opcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load, AddressingMode mode = bdxaddr12only> - : InstRX { + : InstRX { let mayLoad = 1; } class CompareRXE opcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load> - : InstRXE { + : InstRXE { let mayLoad = 1; } class CompareRXY opcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load, AddressingMode mode = bdxaddr20only> - : InstRXY { + : InstRXY { let mayLoad = 1; } @@ -814,26 +776,26 @@ multiclass CompareRXPair rxOpcode, bits<16> rxyOpcode, class CompareSI opcode, SDPatternOperator operator, SDPatternOperator load, Immediate imm, AddressingMode mode = bdaddr12only> - : InstSI { + : InstSI { let mayLoad = 1; } class CompareSIL opcode, SDPatternOperator operator, SDPatternOperator load, Immediate imm> - : InstSIL { + : InstSIL { let mayLoad = 1; } class CompareSIY opcode, SDPatternOperator operator, SDPatternOperator load, Immediate imm, AddressingMode mode = bdaddr20only> - : InstSIY { + : InstSIY { let mayLoad = 1; } @@ -851,43 +813,43 @@ multiclass CompareSIPair siOpcode, bits<16> siyOpcode, class TernaryRRD opcode, SDPatternOperator operator, RegisterOperand cls> - : InstRRD { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRRD { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; } class TernaryRXF opcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load> - : InstRXF { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRXF { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; let mayLoad = 1; } class CmpSwapRS opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode = bdaddr12only> - : InstRS { - let Constraints = "$old = $dst"; - let DisableEncoding = "$old"; + : InstRS { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; let mayLoad = 1; let mayStore = 1; } class CmpSwapRSY opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode = bdaddr20only> - : InstRSY { - let Constraints = "$old = $dst"; - let DisableEncoding = "$old"; + : InstRSY { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; let mayLoad = 1; let mayStore = 1; } @@ -904,12 +866,12 @@ multiclass CmpSwapRSPair rsOpcode, bits<16> rsyOpcode, class RotateSelectRIEf opcode, RegisterOperand cls1, RegisterOperand cls2> - : InstRIEf { - let Constraints = "$src1 = $dst"; - let DisableEncoding = "$src1"; + : InstRIEf { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 7ffa382d36..fe29827c07 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -42,20 +42,20 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1, // Unconditional branches. R1 is the condition-code mask (all 1s). let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { let isIndirectBranch = 1 in - def BR : InstRR<0x07, (outs), (ins ADDR64:$dst), - "br\t$dst", [(brind ADDR64:$dst)]>; + def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), + "br\t$R2", [(brind ADDR64:$R2)]>; // An assembler extended mnemonic for BRC. Use a separate instruction for // the asm parser, so that we don't relax Js to external symbols into JGs. let isCodeGenOnly = 1 in - def J : InstRI<0xA74, (outs), (ins brtarget16:$dst), "j\t$dst", []>; + def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", []>; let isAsmParserOnly = 1 in - def AsmJ : InstRI<0xA74, (outs), (ins brtarget16:$dst), "j\t$dst", []>; + def AsmJ : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", []>; // An assembler extended mnemonic for BRCL. (The extension is "G" // rather than "L" because "JL" is "Jump if Less".) - def JG : InstRIL<0xC04, (outs), (ins brtarget32:$dst), - "jg\t$dst", [(br bb:$dst)]>; + def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), + "jg\t$I2", [(br bb:$I2)]>; } // Conditional branches. It's easier for LLVM to handle these branches @@ -64,24 +64,24 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { // JE and JLH when writing out the assembly though. multiclass CondBranches { let isBranch = 1, isTerminator = 1, Uses = [PSW] in { - def "" : InstRI<0xA74, (outs), (ins imm:$cond, brtarget16:$dst), short, []>; - def L : InstRIL<0xC04, (outs), (ins imm:$cond, brtarget32:$dst), long, []>; + def "" : InstRI<0xA74, (outs), (ins imm:$R1, brtarget16:$I2), short, []>; + def L : InstRIL<0xC04, (outs), (ins imm:$R1, brtarget32:$I2), long, []>; } } let isCodeGenOnly = 1 in - defm BRC : CondBranches; + defm BRC : CondBranches; let isAsmParserOnly = 1 in - defm AsmBRC : CondBranches; + defm AsmBRC : CondBranches; def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRCL cond4:$cond, bb:$dst)>; // Define AsmParser mnemonics for each condition code. multiclass CondExtendedMnemonic Cond, string name> { let R1 = Cond in { - def "" : InstRI<0xA74, (outs), (ins brtarget16:$dst), - "j"##name##"\t$dst", []>; - def L : InstRIL<0xC04, (outs), (ins brtarget32:$dst), - "jg"##name##"\t$dst", []>; + def "" : InstRI<0xA74, (outs), (ins brtarget16:$I2), + "j"##name##"\t$I2", []>; + def L : InstRIL<0xC04, (outs), (ins brtarget32:$I2), + "jg"##name##"\t$I2", []>; } } let isAsmParserOnly = 1 in { @@ -112,23 +112,23 @@ def Select64 : SelectWrapper; let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D, F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D], R1 = 14, isCodeGenOnly = 1 in { - def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$dst, variable_ops), - "bras\t%r14, $dst", []>; - def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$dst, variable_ops), - "brasl\t%r14, $dst", [(z_call pcrel32call:$dst)]>; - def BASR : InstRR<0x0D, (outs), (ins ADDR64:$dst, variable_ops), - "basr\t%r14, $dst", [(z_call ADDR64:$dst)]>; + def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops), + "bras\t%r14, $I2", []>; + def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops), + "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>; + def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops), + "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>; } // Define the general form of the call instructions for the asm parser. // These instructions don't hard-code %r14 as the return address register. let isAsmParserOnly = 1 in { - def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$save, brtarget16:$dst), - "bras\t$save, $dst", []>; - def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$save, brtarget32:$dst), - "brasl\t$save, $dst", []>; - def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$save, ADDR64:$dst), - "basr\t$save, $dst", []>; + def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2), + "bras\t$R1, $I2", []>; + def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2), + "brasl\t$R1, $I2", []>; + def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), + "basr\t$R1, $R2", []>; } //===----------------------------------------------------------------------===// @@ -337,21 +337,21 @@ def STRVG : StoreRXY<"strvg", 0xE32F, storeu, GR64>; // Load BDX-style addresses. let neverHasSideEffects = 1, Function = "la" in { let PairType = "12" in - def LA : InstRX<0x41, (outs GR64:$dst), (ins laaddr12pair:$src), - "la\t$dst, $src", - [(set GR64:$dst, laaddr12pair:$src)]>; + def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2), + "la\t$R1, $XBD2", + [(set GR64:$R1, laaddr12pair:$XBD2)]>; let PairType = "20" in - def LAY : InstRXY<0xE371, (outs GR64:$dst), (ins laaddr20pair:$src), - "lay\t$dst, $src", - [(set GR64:$dst, laaddr20pair:$src)]>; + def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2), + "lay\t$R1, $XBD2", + [(set GR64:$R1, laaddr20pair:$XBD2)]>; } // Load a PC-relative address. There's no version of this instruction // with a 16-bit offset, so there's no relaxation. let neverHasSideEffects = 1 in { - def LARL : InstRIL<0xC00, (outs GR64:$dst), (ins pcrel32:$src), - "larl\t$dst, $src", - [(set GR64:$dst, pcrel32:$src)]>; + def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2), + "larl\t$R1, $I2", + [(set GR64:$R1, pcrel32:$I2)]>; } //===----------------------------------------------------------------------===// @@ -903,9 +903,9 @@ let Defs = [PSW] in { // Read a 32-bit access register into a GR32. As with all GR32 operations, // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful // when a 64-bit address is stored in a pair of access registers. -def EAR : InstRRE<0xB24F, (outs GR32:$dst), (ins access_reg:$src), - "ear\t$dst, $src", - [(set GR32:$dst, (z_extract_access access_reg:$src))]>; +def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2), + "ear\t$R1, $R2", + [(set GR32:$R1, (z_extract_access access_reg:$R2))]>; // Find leftmost one, AKA count leading zeros. The instruction actually // returns a pair of GR64s, the first giving the number of leading zeros diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td index 0abc3f7517..829306f373 100644 --- a/lib/Target/SystemZ/SystemZOperands.td +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -45,11 +45,13 @@ class AddressAsmOperand } // Constructs both a DAG pattern and instruction operand for an addressing mode. -// The mode is selected by custom code in selectTYPE...SUFFIX(). The address -// registers have BITSIZE bits and displacements have DISPSIZE bits. NUMOPS is -// the number of operands that make up an address and OPERANDS lists the types -// of those operands using (ops ...). FORMAT is the type of addressing mode, -// which needs to match the names used in AddressAsmOperand. +// The mode is selected by custom code in select() +// and encoded by custom code in getEncoding(). +// The address registers have BITSIZE bits and displacements have +// DISPSIZE bits. NUMOPS is the number of operands that make up an +// address and OPERANDS lists the types of those operands using (ops ...). +// FORMAT is the type of addressing mode, which needs to match the names +// used in AddressAsmOperand. class AddressingMode : ComplexPattern("i"##bitsize), numops, @@ -57,6 +59,7 @@ class AddressingMode, Operand("i"##bitsize)> { let PrintMethod = "print"##format##"Operand"; + let EncoderMethod = "get"##format##dispsize##"Encoding"; let MIOperandInfo = operands; let ParserMatchClass = !cast(format##bitsize##"Disp"##dispsize); -- cgit v1.2.3 From f917bc0406e47866eb1f6c0378de16498018b620 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 14 May 2013 09:36:44 +0000 Subject: [SystemZ] Match operands to fields by name rather than by order The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181771 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp | 84 +++++++--------------- .../SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp | 42 +++++++++++ .../SystemZ/MCTargetDesc/SystemZMCTargetDesc.h | 10 +++ 3 files changed, 79 insertions(+), 57 deletions(-) diff --git a/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp index c7725a1459..d13234cafd 100644 --- a/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ b/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -250,46 +250,6 @@ public: bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); } }; -// Maps of asm register numbers to LLVM register numbers, with 0 indicating -// an invalid register. We don't use register class directly because that -// specifies the allocation order. -static const unsigned GR32Regs[] = { - SystemZ::R0W, SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, - SystemZ::R4W, SystemZ::R5W, SystemZ::R6W, SystemZ::R7W, - SystemZ::R8W, SystemZ::R9W, SystemZ::R10W, SystemZ::R11W, - SystemZ::R12W, SystemZ::R13W, SystemZ::R14W, SystemZ::R15W -}; -static const unsigned GR64Regs[] = { - SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, - SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, - SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, - SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D -}; -static const unsigned GR128Regs[] = { - SystemZ::R0Q, 0, SystemZ::R2Q, 0, - SystemZ::R4Q, 0, SystemZ::R6Q, 0, - SystemZ::R8Q, 0, SystemZ::R10Q, 0, - SystemZ::R12Q, 0, SystemZ::R14Q, 0 -}; -static const unsigned FP32Regs[] = { - SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, - SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, - SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, - SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S -}; -static const unsigned FP64Regs[] = { - SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, - SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, - SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, - SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D -}; -static const unsigned FP128Regs[] = { - SystemZ::F0Q, SystemZ::F1Q, 0, 0, - SystemZ::F4Q, SystemZ::F5Q, 0, 0, - SystemZ::F8Q, SystemZ::F9Q, 0, 0, - SystemZ::F12Q, SystemZ::F13Q, 0, 0 -}; - class SystemZAsmParser : public MCTargetAsmParser { #define GET_ASSEMBLER_HEADER #include "SystemZGenAsmMatcher.inc" @@ -349,25 +309,28 @@ public: // Used by the TableGen code to parse particular operand types. OperandMatchResultTy parseGR32(SmallVectorImpl &Operands) { - return parseRegister(Operands, 'r', GR32Regs, SystemZOperand::GR32Reg); + return parseRegister(Operands, 'r', SystemZMC::GR32Regs, + SystemZOperand::GR32Reg); } OperandMatchResultTy parseGR64(SmallVectorImpl &Operands) { - return parseRegister(Operands, 'r', GR64Regs, SystemZOperand::GR64Reg); + return parseRegister(Operands, 'r', SystemZMC::GR64Regs, + SystemZOperand::GR64Reg); } OperandMatchResultTy parseGR128(SmallVectorImpl &Operands) { - return parseRegister(Operands, 'r', GR128Regs, SystemZOperand::GR128Reg); + return parseRegister(Operands, 'r', SystemZMC::GR128Regs, + SystemZOperand::GR128Reg); } OperandMatchResultTy parseADDR32(SmallVectorImpl &Operands) { - return parseRegister(Operands, 'r', GR32Regs, SystemZOperand::ADDR32Reg, - true); + return parseRegister(Operands, 'r', SystemZMC::GR32Regs, + SystemZOperand::ADDR32Reg, true); } OperandMatchResultTy parseADDR64(SmallVectorImpl &Operands) { - return parseRegister(Operands, 'r', GR64Regs, SystemZOperand::ADDR64Reg, - true); + return parseRegister(Operands, 'r', SystemZMC::GR64Regs, + SystemZOperand::ADDR64Reg, true); } OperandMatchResultTy parseADDR128(SmallVectorImpl &Operands) { @@ -375,27 +338,33 @@ public: } OperandMatchResultTy parseFP32(SmallVectorImpl &Operands) { - return parseRegister(Operands, 'f', FP32Regs, SystemZOperand::FP32Reg); + return parseRegister(Operands, 'f', SystemZMC::FP32Regs, + SystemZOperand::FP32Reg); } OperandMatchResultTy parseFP64(SmallVectorImpl &Operands) { - return parseRegister(Operands, 'f', FP64Regs, SystemZOperand::FP64Reg); + return parseRegister(Operands, 'f', SystemZMC::FP64Regs, + SystemZOperand::FP64Reg); } OperandMatchResultTy parseFP128(SmallVectorImpl &Operands) { - return parseRegister(Operands, 'f', FP128Regs, SystemZOperand::FP128Reg); + return parseRegister(Operands, 'f', SystemZMC::FP128Regs, + SystemZOperand::FP128Reg); } OperandMatchResultTy parseBDAddr32(SmallVectorImpl &Operands) { - return parseAddress(Operands, GR32Regs, SystemZOperand::ADDR32Reg, false); + return parseAddress(Operands, SystemZMC::GR32Regs, + SystemZOperand::ADDR32Reg, false); } OperandMatchResultTy parseBDAddr64(SmallVectorImpl &Operands) { - return parseAddress(Operands, GR64Regs, SystemZOperand::ADDR64Reg, false); + return parseAddress(Operands, SystemZMC::GR64Regs, + SystemZOperand::ADDR64Reg, false); } OperandMatchResultTy parseBDXAddr64(SmallVectorImpl &Operands) { - return parseAddress(Operands, GR64Regs, SystemZOperand::ADDR64Reg, true); + return parseAddress(Operands, SystemZMC::GR64Regs, + SystemZOperand::ADDR64Reg, true); } OperandMatchResultTy parseAccessReg(SmallVectorImpl &Operands); @@ -502,7 +471,8 @@ SystemZAsmParser::parseAddress(SmallVectorImpl &Operands, // Parse the first register. Register Reg; - OperandMatchResultTy Result = parseRegister(Reg, 'r', GR64Regs, true); + OperandMatchResultTy Result = parseRegister(Reg, 'r', SystemZMC::GR64Regs, + true); if (Result != MatchOperand_Success) return Result; @@ -517,7 +487,7 @@ SystemZAsmParser::parseAddress(SmallVectorImpl &Operands, } Index = Reg.Number; - Result = parseRegister(Reg, 'r', GR64Regs, true); + Result = parseRegister(Reg, 'r', SystemZMC::GR64Regs, true); if (Result != MatchOperand_Success) return Result; } @@ -546,9 +516,9 @@ bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, if (parseRegister(Reg)) return Error(Reg.StartLoc, "register expected"); if (Reg.Prefix == 'r' && Reg.Number < 16) - RegNo = GR64Regs[Reg.Number]; + RegNo = SystemZMC::GR64Regs[Reg.Number]; else if (Reg.Prefix == 'f' && Reg.Number < 16) - RegNo = FP64Regs[Reg.Number]; + RegNo = SystemZMC::FP64Regs[Reg.Number]; else return Error(Reg.StartLoc, "invalid register"); StartLoc = Reg.StartLoc; diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index 6fe80610dc..3653192d85 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -27,6 +27,48 @@ using namespace llvm; +const unsigned SystemZMC::GR32Regs[16] = { + SystemZ::R0W, SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, + SystemZ::R4W, SystemZ::R5W, SystemZ::R6W, SystemZ::R7W, + SystemZ::R8W, SystemZ::R9W, SystemZ::R10W, SystemZ::R11W, + SystemZ::R12W, SystemZ::R13W, SystemZ::R14W, SystemZ::R15W +}; + +const unsigned SystemZMC::GR64Regs[16] = { + SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, + SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, + SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, + SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D +}; + +const unsigned SystemZMC::GR128Regs[16] = { + SystemZ::R0Q, 0, SystemZ::R2Q, 0, + SystemZ::R4Q, 0, SystemZ::R6Q, 0, + SystemZ::R8Q, 0, SystemZ::R10Q, 0, + SystemZ::R12Q, 0, SystemZ::R14Q, 0 +}; + +const unsigned SystemZMC::FP32Regs[16] = { + SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, + SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, + SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, + SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S +}; + +const unsigned SystemZMC::FP64Regs[16] = { + SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, + SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, + SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, + SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D +}; + +const unsigned SystemZMC::FP128Regs[16] = { + SystemZ::F0Q, SystemZ::F1Q, 0, 0, + SystemZ::F4Q, SystemZ::F5Q, 0, 0, + SystemZ::F8Q, SystemZ::F9Q, 0, 0, + SystemZ::F12Q, SystemZ::F13Q, 0, 0 +}; + static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { MCAsmInfo *MAI = new SystemZMCAsmInfo(TT); diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h index 229912f161..1f70047db6 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -34,6 +34,16 @@ namespace SystemZMC { // The offset of the DWARF CFA from the incoming stack pointer. const int64_t CFAOffsetFromInitialSP = CallFrameSize; + + // Maps of asm register numbers to LLVM register numbers, with 0 indicating + // an invalid register. We don't use the register classes directly because + // they specify the allocation order. + extern const unsigned GR32Regs[16]; + extern const unsigned GR64Regs[16]; + extern const unsigned GR128Regs[16]; + extern const unsigned FP32Regs[16]; + extern const unsigned FP64Regs[16]; + extern const unsigned FP128Regs[16]; } MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII, -- cgit v1.2.3 From 58b854d7e9e5fb09a60a4e3a66e8049a7e4a01f6 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 14 May 2013 09:38:07 +0000 Subject: [SystemZ] Remove bogus isAsmParserOnly Marking instructions as isAsmParserOnly stops them from being disassembled. However, in cases where separate asm and codegen versions exist, we actually want to disassemble to the asm ones. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181772 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZInstrInfo.td | 50 +++++++++++++++------------------- 1 file changed, 22 insertions(+), 28 deletions(-) diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index fe29827c07..fea2b73579 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -49,8 +49,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { // the asm parser, so that we don't relax Js to external symbols into JGs. let isCodeGenOnly = 1 in def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", []>; - let isAsmParserOnly = 1 in - def AsmJ : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", []>; + def AsmJ : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", []>; // An assembler extended mnemonic for BRCL. (The extension is "G" // rather than "L" because "JL" is "Jump if Less".) @@ -70,8 +69,7 @@ multiclass CondBranches { } let isCodeGenOnly = 1 in defm BRC : CondBranches; -let isAsmParserOnly = 1 in - defm AsmBRC : CondBranches; +defm AsmBRC : CondBranches; def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRCL cond4:$cond, bb:$dst)>; @@ -84,22 +82,20 @@ multiclass CondExtendedMnemonic Cond, string name> { "jg"##name##"\t$I2", []>; } } -let isAsmParserOnly = 1 in { - defm AsmJO : CondExtendedMnemonic<1, "o">; - defm AsmJH : CondExtendedMnemonic<2, "h">; - defm AsmJNLE : CondExtendedMnemonic<3, "nle">; - defm AsmJL : CondExtendedMnemonic<4, "l">; - defm AsmJNHE : CondExtendedMnemonic<5, "nhe">; - defm AsmJLH : CondExtendedMnemonic<6, "lh">; - defm AsmJNE : CondExtendedMnemonic<7, "ne">; - defm AsmJE : CondExtendedMnemonic<8, "e">; - defm AsmJNLH : CondExtendedMnemonic<9, "nlh">; - defm AsmJHE : CondExtendedMnemonic<10, "he">; - defm AsmJNL : CondExtendedMnemonic<11, "nl">; - defm AsmJLE : CondExtendedMnemonic<12, "le">; - defm AsmJNH : CondExtendedMnemonic<13, "nh">; - defm AsmJNO : CondExtendedMnemonic<14, "no">; -} +defm AsmJO : CondExtendedMnemonic<1, "o">; +defm AsmJH : CondExtendedMnemonic<2, "h">; +defm AsmJNLE : CondExtendedMnemonic<3, "nle">; +defm AsmJL : CondExtendedMnemonic<4, "l">; +defm AsmJNHE : CondExtendedMnemonic<5, "nhe">; +defm AsmJLH : CondExtendedMnemonic<6, "lh">; +defm AsmJNE : CondExtendedMnemonic<7, "ne">; +defm AsmJE : CondExtendedMnemonic<8, "e">; +defm AsmJNLH : CondExtendedMnemonic<9, "nlh">; +defm AsmJHE : CondExtendedMnemonic<10, "he">; +defm AsmJNL : CondExtendedMnemonic<11, "nl">; +defm AsmJLE : CondExtendedMnemonic<12, "le">; +defm AsmJNH : CondExtendedMnemonic<13, "nh">; +defm AsmJNO : CondExtendedMnemonic<14, "no">; def Select32 : SelectWrapper; def Select64 : SelectWrapper; @@ -122,14 +118,12 @@ let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D, // Define the general form of the call instructions for the asm parser. // These instructions don't hard-code %r14 as the return address register. -let isAsmParserOnly = 1 in { - def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2), - "bras\t$R1, $I2", []>; - def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2), - "brasl\t$R1, $I2", []>; - def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), - "basr\t$R1, $R2", []>; -} +def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2), + "bras\t$R1, $I2", []>; +def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2), + "brasl\t$R1, $I2", []>; +def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), + "basr\t$R1, $R2", []>; //===----------------------------------------------------------------------===// // Move instructions -- cgit v1.2.3 From b594c4c873bd3e2ee560cc83bd50282ec56b01e9 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 14 May 2013 09:47:26 +0000 Subject: [SystemZ] Rework handling of constant PC-relative operands The GNU assembler treats things like: brasl %r14, 100 in the same way as: brasl %r14, .+100 rather than as a branch to absolute address 100. We implemented this in LLVM by creating an immediate operand rather than the usual expr operand, and by handling immediate operands specially in the code emitter. This was undesirable for (at least) three reasons: - the specialness of immediate operands was exposed to the backend MC code, rather than being limited to the assembler parser. - in disassembly, an immediate operand really is an absolute address. (Note that this means reassembling printed disassembly can't recreate the original code.) - it would interfere with any assembly manipulation that we might try in future. E.g. operations like branch shortening can change the relative position of instructions, but any code that updates sym+offset addresses wouldn't update an immediate "100" operand in the same way as an explicit ".+100" operand. This patch changes the implementation so that the assembler creates a "." label for immediate PC-relative operands, so that the operand to the MCInst is always the absolute address. The patch also adds some error checking of the offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181773 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp | 43 ++++++++++++++++++++++ .../SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp | 24 ++++++------ lib/Target/SystemZ/SystemZOperands.td | 34 +++++++++++++---- test/MC/SystemZ/insn-bras-01.s | 13 +++++++ test/MC/SystemZ/insn-brasl-01.s | 13 +++++++ test/MC/SystemZ/insn-brc-01.s | 13 +++++++ test/MC/SystemZ/insn-brc-02.s | 14 +++++++ test/MC/SystemZ/insn-brcl-01.s | 13 +++++++ test/MC/SystemZ/insn-brcl-02.s | 14 +++++++ test/MC/SystemZ/insn-cgfrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-cghrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-cgrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-chrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-clgfrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-clghrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-clgrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-clhrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-clrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-crl-01.s | 17 ++++++--- test/MC/SystemZ/insn-larl-01.s | 17 ++++++--- test/MC/SystemZ/insn-lgfrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-lghrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-lgrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-lhrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-llgfrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-llghrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-llhrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-lrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-stgrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-sthrl-01.s | 17 ++++++--- test/MC/SystemZ/insn-strl-01.s | 17 ++++++--- 31 files changed, 425 insertions(+), 130 deletions(-) diff --git a/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp index d13234cafd..7f2159f79e 100644 --- a/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ b/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -8,6 +8,7 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/SystemZMCTargetDesc.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" @@ -368,6 +369,17 @@ public: } OperandMatchResultTy parseAccessReg(SmallVectorImpl &Operands); + OperandMatchResultTy + parsePCRel(SmallVectorImpl &Operands, + int64_t MinVal, int64_t MaxVal); + OperandMatchResultTy + parsePCRel16(SmallVectorImpl &Operands) { + return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1); + } + OperandMatchResultTy + parsePCRel32(SmallVectorImpl &Operands) { + return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1); + } }; } @@ -653,6 +665,37 @@ parseAccessReg(SmallVectorImpl &Operands) { return MatchOperand_Success; } +SystemZAsmParser::OperandMatchResultTy SystemZAsmParser:: +parsePCRel(SmallVectorImpl &Operands, + int64_t MinVal, int64_t MaxVal) { + MCContext &Ctx = getContext(); + MCStreamer &Out = getStreamer(); + const MCExpr *Expr; + SMLoc StartLoc = Parser.getTok().getLoc(); + if (getParser().parseExpression(Expr)) + return MatchOperand_NoMatch; + + // For consistency with the GNU assembler, treat immediates as offsets + // from ".". + if (const MCConstantExpr *CE = dyn_cast(Expr)) { + int64_t Value = CE->getValue(); + if ((Value & 1) || Value < MinVal || Value > MaxVal) { + Error(StartLoc, "offset out of range"); + return MatchOperand_ParseFail; + } + MCSymbol *Sym = Ctx.CreateTempSymbol(); + Out.EmitLabel(Sym); + const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, + Ctx); + Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx); + } + + SMLoc EndLoc = + SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); + return MatchOperand_Success; +} + // Force static initialization. extern "C" void LLVMInitializeSystemZAsmParser() { RegisterMCAsmParser X(TheSystemZTarget); diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp index 70a3eb9420..7721b1ffab 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp @@ -162,19 +162,19 @@ SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups, unsigned Kind, int64_t Offset) const { const MCOperand &MO = MI.getOperand(OpNum); - // For compatibility with the GNU assembler, treat constant operands as - // unadjusted PC-relative offsets. + const MCExpr *Expr; if (MO.isImm()) - return MO.getImm() / 2; - - const MCExpr *Expr = MO.getExpr(); - if (Offset) { - // The operand value is relative to the start of MI, but the fixup - // is relative to the operand field itself, which is Offset bytes - // into MI. Add Offset to the relocation value to cancel out - // this difference. - const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx); - Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx); + Expr = MCConstantExpr::Create(MO.getImm() + Offset, Ctx); + else { + Expr = MO.getExpr(); + if (Offset) { + // The operand value is relative to the start of MI, but the fixup + // is relative to the operand field itself, which is Offset bytes + // into MI. Add Offset to the relocation value to cancel out + // this difference. + const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx); + Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx); + } } Fixups.push_back(MCFixup::Create(Offset, Expr, (MCFixupKind)Kind)); return 0; diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td index 829306f373..770b7f5eec 100644 --- a/lib/Target/SystemZ/SystemZOperands.td +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -27,11 +27,25 @@ class Immediate let ParserMatchClass = !cast(asmop); } +// Constructs an asm operand for a PC-relative address. SIZE says how +// many bits there are. +class PCRelAsmOperand : ImmediateAsmOperand<"PCRel"##size> { + let PredicateMethod = "isImm"; + let ParserMethod = "parsePCRel"##size; +} + +// Constructs an operand for a PC-relative address with address type VT. +// ASMOP is the associated asm operand. +class PCRelOperand : Operand { + let ParserMatchClass = asmop; +} + // Constructs both a DAG pattern and instruction operand for a PC-relative -// address with address size VT. SELF is the name of the operand. -class PCRelAddress +// address with address size VT. SELF is the name of the operand and +// ASMOP is the associated asm operand. +class PCRelAddress : ComplexPattern, - Operand { + PCRelOperand { let MIOperandInfo = (ops !cast(self)); } @@ -337,28 +351,32 @@ def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; // Symbolic address operands //===----------------------------------------------------------------------===// +// PC-relative asm operands. +def PCRel16 : PCRelAsmOperand<"16">; +def PCRel32 : PCRelAsmOperand<"32">; + // PC-relative offsets of a basic block. The offset is sign-extended // and multiplied by 2. -def brtarget16 : Operand { +def brtarget16 : PCRelOperand { let EncoderMethod = "getPC16DBLEncoding"; } -def brtarget32 : Operand { +def brtarget32 : PCRelOperand { let EncoderMethod = "getPC32DBLEncoding"; } // A PC-relative offset of a global value. The offset is sign-extended // and multiplied by 2. -def pcrel32 : PCRelAddress { +def pcrel32 : PCRelAddress { let EncoderMethod = "getPC32DBLEncoding"; } // A PC-relative offset of a global value when the value is used as a // call target. The offset is sign-extended and multiplied by 2. -def pcrel16call : PCRelAddress { +def pcrel16call : PCRelAddress { let PrintMethod = "printCallOperand"; let EncoderMethod = "getPLT16DBLEncoding"; } -def pcrel32call : PCRelAddress { +def pcrel32call : PCRelAddress { let PrintMethod = "printCallOperand"; let EncoderMethod = "getPLT32DBLEncoding"; } diff --git a/test/MC/SystemZ/insn-bras-01.s b/test/MC/SystemZ/insn-bras-01.s index 89f7f77477..d023da6c1e 100644 --- a/test/MC/SystemZ/insn-bras-01.s +++ b/test/MC/SystemZ/insn-bras-01.s @@ -1,5 +1,18 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s +#CHECK: bras %r0, .[[LAB:L.*]]-65536 # encoding: [0xa7,0x05,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL + bras %r0, -0x10000 +#CHECK: bras %r0, .[[LAB:L.*]]-2 # encoding: [0xa7,0x05,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL + bras %r0, -2 +#CHECK: bras %r0, .[[LAB:L.*]] # encoding: [0xa7,0x05,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL + bras %r0, 0 +#CHECK: bras %r0, .[[LAB:L.*]]+65534 # encoding: [0xa7,0x05,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL + bras %r0, 0xfffe + #CHECK: bras %r0, foo # encoding: [0xa7,0x05,A,A] #CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL #CHECK: bras %r14, foo # encoding: [0xa7,0xe5,A,A] diff --git a/test/MC/SystemZ/insn-brasl-01.s b/test/MC/SystemZ/insn-brasl-01.s index 86d0ced9b3..24a19ad2cc 100644 --- a/test/MC/SystemZ/insn-brasl-01.s +++ b/test/MC/SystemZ/insn-brasl-01.s @@ -1,5 +1,18 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s +#CHECK: brasl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc0,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + brasl %r0, -0x100000000 +#CHECK: brasl %r0, .[[LAB:L.*]]-2 # encoding: [0xc0,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + brasl %r0, -2 +#CHECK: brasl %r0, .[[LAB:L.*]] # encoding: [0xc0,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + brasl %r0, 0 +#CHECK: brasl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc0,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + brasl %r0, 0xfffffffe + #CHECK: brasl %r0, foo # encoding: [0xc0,0x05,A,A,A,A] #CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL #CHECK: brasl %r14, foo # encoding: [0xc0,0xe5,A,A,A,A] diff --git a/test/MC/SystemZ/insn-brc-01.s b/test/MC/SystemZ/insn-brc-01.s index a92ea45ecf..870f1c632e 100644 --- a/test/MC/SystemZ/insn-brc-01.s +++ b/test/MC/SystemZ/insn-brc-01.s @@ -1,5 +1,18 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s +#CHECK: brc 0, .[[LAB:L.*]]-65536 # encoding: [0xa7,0x04,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL + brc 0, -0x10000 +#CHECK: brc 0, .[[LAB:L.*]]-2 # encoding: [0xa7,0x04,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL + brc 0, -2 +#CHECK: brc 0, .[[LAB:L.*]] # encoding: [0xa7,0x04,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL + brc 0, 0 +#CHECK: brc 0, .[[LAB:L.*]]+65534 # encoding: [0xa7,0x04,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL + brc 0, 0xfffe + #CHECK: brc 0, foo # encoding: [0xa7,0x04,A,A] #CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL brc 0, foo diff --git a/test/MC/SystemZ/insn-brc-02.s b/test/MC/SystemZ/insn-brc-02.s index 941cc459f3..e0af3b3687 100644 --- a/test/MC/SystemZ/insn-brc-02.s +++ b/test/MC/SystemZ/insn-brc-02.s @@ -1,6 +1,20 @@ # RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t # RUN: FileCheck < %t %s +#CHECK: error: offset out of range +#CHECK: brc 0, -0x100002 +#CHECK: error: offset out of range +#CHECK: brc 0, -1 +#CHECK: error: offset out of range +#CHECK: brc 0, 1 +#CHECK: error: offset out of range +#CHECK: brc 0, 0x10000 + + brc 0, -0x100002 + brc 0, -1 + brc 0, 1 + brc 0, 0x10000 + #CHECK: error: invalid operand #CHECK: brc foo, bar #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-brcl-01.s b/test/MC/SystemZ/insn-brcl-01.s index f7138bf5be..f38341addf 100644 --- a/test/MC/SystemZ/insn-brcl-01.s +++ b/test/MC/SystemZ/insn-brcl-01.s @@ -1,5 +1,18 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s +#CHECK: brcl 0, .[[LAB:L.*]]-4294967296 # encoding: [0xc0,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + brcl 0, -0x100000000 +#CHECK: brcl 0, .[[LAB:L.*]]-2 # encoding: [0xc0,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + brcl 0, -2 +#CHECK: brcl 0, .[[LAB:L.*]] # encoding: [0xc0,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + brcl 0, 0 +#CHECK: brcl 0, .[[LAB:L.*]]+4294967294 # encoding: [0xc0,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + brcl 0, 0xfffffffe + #CHECK: brcl 0, foo # encoding: [0xc0,0x04,A,A,A,A] #CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL brcl 0, foo diff --git a/test/MC/SystemZ/insn-brcl-02.s b/test/MC/SystemZ/insn-brcl-02.s index ded5f7e4a6..81e2fdc7f0 100644 --- a/test/MC/SystemZ/insn-brcl-02.s +++ b/test/MC/SystemZ/insn-brcl-02.s @@ -1,6 +1,20 @@ # RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t # RUN: FileCheck < %t %s +#CHECK: error: offset out of range +#CHECK: brcl 0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: brcl 0, -1 +#CHECK: error: offset out of range +#CHECK: brcl 0, 1 +#CHECK: error: offset out of range +#CHECK: brcl 0, 0x100000000 + + brcl 0, -0x1000000002 + brcl 0, -1 + brcl 0, 1 + brcl 0, 0x100000000 + #CHECK: error: invalid operand #CHECK: brcl foo, bar #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-cgfrl-01.s b/test/MC/SystemZ/insn-cgfrl-01.s index 2792fb4a93..6526bf52b4 100644 --- a/test/MC/SystemZ/insn-cgfrl-01.s +++ b/test/MC/SystemZ/insn-cgfrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: cgfrl %r0, 2864434397 # encoding: [0xc6,0x0c,0x55,0x5d,0xe6,0x6e] -#CHECK: cgfrl %r15, 2864434397 # encoding: [0xc6,0xfc,0x55,0x5d,0xe6,0x6e] - - cgfrl %r0,0xaabbccdd - cgfrl %r15,0xaabbccdd +#CHECK: cgfrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x0c,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + cgfrl %r0, -0x100000000 +#CHECK: cgfrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x0c,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + cgfrl %r0, -2 +#CHECK: cgfrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x0c,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + cgfrl %r0, 0 +#CHECK: cgfrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x0c,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + cgfrl %r0, 0xfffffffe #CHECK: cgfrl %r0, foo # encoding: [0xc6,0x0c,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-cghrl-01.s b/test/MC/SystemZ/insn-cghrl-01.s index c48c5ec3ef..26b63bd2b7 100644 --- a/test/MC/SystemZ/insn-cghrl-01.s +++ b/test/MC/SystemZ/insn-cghrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: cghrl %r0, 2864434397 # encoding: [0xc6,0x04,0x55,0x5d,0xe6,0x6e] -#CHECK: cghrl %r15, 2864434397 # encoding: [0xc6,0xf4,0x55,0x5d,0xe6,0x6e] - - cghrl %r0,0xaabbccdd - cghrl %r15,0xaabbccdd +#CHECK: cghrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + cghrl %r0, -0x100000000 +#CHECK: cghrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + cghrl %r0, -2 +#CHECK: cghrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + cghrl %r0, 0 +#CHECK: cghrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + cghrl %r0, 0xfffffffe #CHECK: cghrl %r0, foo # encoding: [0xc6,0x04,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-cgrl-01.s b/test/MC/SystemZ/insn-cgrl-01.s index af878cbf45..b6e61c86f1 100644 --- a/test/MC/SystemZ/insn-cgrl-01.s +++ b/test/MC/SystemZ/insn-cgrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: cgrl %r0, 2864434397 # encoding: [0xc6,0x08,0x55,0x5d,0xe6,0x6e] -#CHECK: cgrl %r15, 2864434397 # encoding: [0xc6,0xf8,0x55,0x5d,0xe6,0x6e] - - cgrl %r0,0xaabbccdd - cgrl %r15,0xaabbccdd +#CHECK: cgrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x08,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + cgrl %r0, -0x100000000 +#CHECK: cgrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x08,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + cgrl %r0, -2 +#CHECK: cgrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x08,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + cgrl %r0, 0 +#CHECK: cgrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x08,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + cgrl %r0, 0xfffffffe #CHECK: cgrl %r0, foo # encoding: [0xc6,0x08,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-chrl-01.s b/test/MC/SystemZ/insn-chrl-01.s index c133a326d2..2c89d909db 100644 --- a/test/MC/SystemZ/insn-chrl-01.s +++ b/test/MC/SystemZ/insn-chrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: chrl %r0, 2864434397 # encoding: [0xc6,0x05,0x55,0x5d,0xe6,0x6e] -#CHECK: chrl %r15, 2864434397 # encoding: [0xc6,0xf5,0x55,0x5d,0xe6,0x6e] - - chrl %r0,0xaabbccdd - chrl %r15,0xaabbccdd +#CHECK: chrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + chrl %r0, -0x100000000 +#CHECK: chrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + chrl %r0, -2 +#CHECK: chrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + chrl %r0, 0 +#CHECK: chrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + chrl %r0, 0xfffffffe #CHECK: chrl %r0, foo # encoding: [0xc6,0x05,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-clgfrl-01.s b/test/MC/SystemZ/insn-clgfrl-01.s index 6fc6d5eb3b..1959b195fd 100644 --- a/test/MC/SystemZ/insn-clgfrl-01.s +++ b/test/MC/SystemZ/insn-clgfrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: clgfrl %r0, 2864434397 # encoding: [0xc6,0x0e,0x55,0x5d,0xe6,0x6e] -#CHECK: clgfrl %r15, 2864434397 # encoding: [0xc6,0xfe,0x55,0x5d,0xe6,0x6e] - - clgfrl %r0,0xaabbccdd - clgfrl %r15,0xaabbccdd +#CHECK: clgfrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x0e,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + clgfrl %r0, -0x100000000 +#CHECK: clgfrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x0e,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + clgfrl %r0, -2 +#CHECK: clgfrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x0e,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + clgfrl %r0, 0 +#CHECK: clgfrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x0e,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + clgfrl %r0, 0xfffffffe #CHECK: clgfrl %r0, foo # encoding: [0xc6,0x0e,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-clghrl-01.s b/test/MC/SystemZ/insn-clghrl-01.s index 41c2580abd..049511afd5 100644 --- a/test/MC/SystemZ/insn-clghrl-01.s +++ b/test/MC/SystemZ/insn-clghrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: clghrl %r0, 2864434397 # encoding: [0xc6,0x06,0x55,0x5d,0xe6,0x6e] -#CHECK: clghrl %r15, 2864434397 # encoding: [0xc6,0xf6,0x55,0x5d,0xe6,0x6e] - - clghrl %r0,0xaabbccdd - clghrl %r15,0xaabbccdd +#CHECK: clghrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x06,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + clghrl %r0, -0x100000000 +#CHECK: clghrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x06,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + clghrl %r0, -2 +#CHECK: clghrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x06,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + clghrl %r0, 0 +#CHECK: clghrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x06,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + clghrl %r0, 0xfffffffe #CHECK: clghrl %r0, foo # encoding: [0xc6,0x06,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-clgrl-01.s b/test/MC/SystemZ/insn-clgrl-01.s index 439bcd94ff..2464577736 100644 --- a/test/MC/SystemZ/insn-clgrl-01.s +++ b/test/MC/SystemZ/insn-clgrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: clgrl %r0, 2864434397 # encoding: [0xc6,0x0a,0x55,0x5d,0xe6,0x6e] -#CHECK: clgrl %r15, 2864434397 # encoding: [0xc6,0xfa,0x55,0x5d,0xe6,0x6e] - - clgrl %r0,0xaabbccdd - clgrl %r15,0xaabbccdd +#CHECK: clgrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x0a,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + clgrl %r0, -0x100000000 +#CHECK: clgrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x0a,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + clgrl %r0, -2 +#CHECK: clgrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x0a,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + clgrl %r0, 0 +#CHECK: clgrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x0a,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + clgrl %r0, 0xfffffffe #CHECK: clgrl %r0, foo # encoding: [0xc6,0x0a,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-clhrl-01.s b/test/MC/SystemZ/insn-clhrl-01.s index b424de8f66..72c9dfaf1f 100644 --- a/test/MC/SystemZ/insn-clhrl-01.s +++ b/test/MC/SystemZ/insn-clhrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: clhrl %r0, 2864434397 # encoding: [0xc6,0x07,0x55,0x5d,0xe6,0x6e] -#CHECK: clhrl %r15, 2864434397 # encoding: [0xc6,0xf7,0x55,0x5d,0xe6,0x6e] - - clhrl %r0,0xaabbccdd - clhrl %r15,0xaabbccdd +#CHECK: clhrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x07,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + clhrl %r0, -0x100000000 +#CHECK: clhrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x07,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + clhrl %r0, -2 +#CHECK: clhrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x07,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + clhrl %r0, 0 +#CHECK: clhrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x07,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + clhrl %r0, 0xfffffffe #CHECK: clhrl %r0, foo # encoding: [0xc6,0x07,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-clrl-01.s b/test/MC/SystemZ/insn-clrl-01.s index 4c6e649b43..c89c16b7e0 100644 --- a/test/MC/SystemZ/insn-clrl-01.s +++ b/test/MC/SystemZ/insn-clrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: clrl %r0, 2864434397 # encoding: [0xc6,0x0f,0x55,0x5d,0xe6,0x6e] -#CHECK: clrl %r15, 2864434397 # encoding: [0xc6,0xff,0x55,0x5d,0xe6,0x6e] - - clrl %r0,0xaabbccdd - clrl %r15,0xaabbccdd +#CHECK: clrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x0f,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + clrl %r0, -0x100000000 +#CHECK: clrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x0f,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + clrl %r0, -2 +#CHECK: clrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x0f,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + clrl %r0, 0 +#CHECK: clrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x0f,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + clrl %r0, 0xfffffffe #CHECK: clrl %r0, foo # encoding: [0xc6,0x0f,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-crl-01.s b/test/MC/SystemZ/insn-crl-01.s index 2451b4c9f8..53f5f895e0 100644 --- a/test/MC/SystemZ/insn-crl-01.s +++ b/test/MC/SystemZ/insn-crl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: crl %r0, 2864434397 # encoding: [0xc6,0x0d,0x55,0x5d,0xe6,0x6e] -#CHECK: crl %r15, 2864434397 # encoding: [0xc6,0xfd,0x55,0x5d,0xe6,0x6e] - - crl %r0,0xaabbccdd - crl %r15,0xaabbccdd +#CHECK: crl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x0d,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + crl %r0, -0x100000000 +#CHECK: crl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x0d,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + crl %r0, -2 +#CHECK: crl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x0d,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + crl %r0, 0 +#CHECK: crl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc6,0x0d,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + crl %r0, 0xfffffffe #CHECK: crl %r0, foo # encoding: [0xc6,0x0d,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-larl-01.s b/test/MC/SystemZ/insn-larl-01.s index 3d0f98f562..842f2ff28e 100644 --- a/test/MC/SystemZ/insn-larl-01.s +++ b/test/MC/SystemZ/insn-larl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: larl %r0, 2864434397 # encoding: [0xc0,0x00,0x55,0x5d,0xe6,0x6e] -#CHECK: larl %r15, 2864434397 # encoding: [0xc0,0xf0,0x55,0x5d,0xe6,0x6e] - - larl %r0,0xaabbccdd - larl %r15,0xaabbccdd +#CHECK: larl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc0,0x00,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + larl %r0, -0x100000000 +#CHECK: larl %r0, .[[LAB:L.*]]-2 # encoding: [0xc0,0x00,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + larl %r0, -2 +#CHECK: larl %r0, .[[LAB:L.*]] # encoding: [0xc0,0x00,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + larl %r0, 0 +#CHECK: larl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc0,0x00,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + larl %r0, 0xfffffffe #CHECK: larl %r0, foo # encoding: [0xc0,0x00,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-lgfrl-01.s b/test/MC/SystemZ/insn-lgfrl-01.s index 85c9ea764c..a016036be7 100644 --- a/test/MC/SystemZ/insn-lgfrl-01.s +++ b/test/MC/SystemZ/insn-lgfrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: lgfrl %r0, 2864434397 # encoding: [0xc4,0x0c,0x55,0x5d,0xe6,0x6e] -#CHECK: lgfrl %r15, 2864434397 # encoding: [0xc4,0xfc,0x55,0x5d,0xe6,0x6e] - - lgfrl %r0,0xaabbccdd - lgfrl %r15,0xaabbccdd +#CHECK: lgfrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0c,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + lgfrl %r0, -0x100000000 +#CHECK: lgfrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x0c,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + lgfrl %r0, -2 +#CHECK: lgfrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x0c,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + lgfrl %r0, 0 +#CHECK: lgfrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x0c,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + lgfrl %r0, 0xfffffffe #CHECK: lgfrl %r0, foo # encoding: [0xc4,0x0c,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-lghrl-01.s b/test/MC/SystemZ/insn-lghrl-01.s index 34992e6ff2..1acb848858 100644 --- a/test/MC/SystemZ/insn-lghrl-01.s +++ b/test/MC/SystemZ/insn-lghrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: lghrl %r0, 2864434397 # encoding: [0xc4,0x04,0x55,0x5d,0xe6,0x6e] -#CHECK: lghrl %r15, 2864434397 # encoding: [0xc4,0xf4,0x55,0x5d,0xe6,0x6e] - - lghrl %r0,0xaabbccdd - lghrl %r15,0xaabbccdd +#CHECK: lghrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + lghrl %r0, -0x100000000 +#CHECK: lghrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + lghrl %r0, -2 +#CHECK: lghrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + lghrl %r0, 0 +#CHECK: lghrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + lghrl %r0, 0xfffffffe #CHECK: lghrl %r0, foo # encoding: [0xc4,0x04,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-lgrl-01.s b/test/MC/SystemZ/insn-lgrl-01.s index 7a18908f9a..fc71919080 100644 --- a/test/MC/SystemZ/insn-lgrl-01.s +++ b/test/MC/SystemZ/insn-lgrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: lgrl %r0, 2864434397 # encoding: [0xc4,0x08,0x55,0x5d,0xe6,0x6e] -#CHECK: lgrl %r15, 2864434397 # encoding: [0xc4,0xf8,0x55,0x5d,0xe6,0x6e] - - lgrl %r0,0xaabbccdd - lgrl %r15,0xaabbccdd +#CHECK: lgrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x08,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + lgrl %r0, -0x100000000 +#CHECK: lgrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x08,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + lgrl %r0, -2 +#CHECK: lgrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x08,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + lgrl %r0, 0 +#CHECK: lgrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x08,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + lgrl %r0, 0xfffffffe #CHECK: lgrl %r0, foo # encoding: [0xc4,0x08,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-lhrl-01.s b/test/MC/SystemZ/insn-lhrl-01.s index 87925fe098..04fb41a08a 100644 --- a/test/MC/SystemZ/insn-lhrl-01.s +++ b/test/MC/SystemZ/insn-lhrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: lhrl %r0, 2864434397 # encoding: [0xc4,0x05,0x55,0x5d,0xe6,0x6e] -#CHECK: lhrl %r15, 2864434397 # encoding: [0xc4,0xf5,0x55,0x5d,0xe6,0x6e] - - lhrl %r0,0xaabbccdd - lhrl %r15,0xaabbccdd +#CHECK: lhrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + lhrl %r0, -0x100000000 +#CHECK: lhrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + lhrl %r0, -2 +#CHECK: lhrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + lhrl %r0, 0 +#CHECK: lhrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + lhrl %r0, 0xfffffffe #CHECK: lhrl %r0, foo # encoding: [0xc4,0x05,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-llgfrl-01.s b/test/MC/SystemZ/insn-llgfrl-01.s index 85fc9f4b3c..785dfa6330 100644 --- a/test/MC/SystemZ/insn-llgfrl-01.s +++ b/test/MC/SystemZ/insn-llgfrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: llgfrl %r0, 2864434397 # encoding: [0xc4,0x0e,0x55,0x5d,0xe6,0x6e] -#CHECK: llgfrl %r15, 2864434397 # encoding: [0xc4,0xfe,0x55,0x5d,0xe6,0x6e] - - llgfrl %r0,0xaabbccdd - llgfrl %r15,0xaabbccdd +#CHECK: llgfrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0e,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + llgfrl %r0, -0x100000000 +#CHECK: llgfrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x0e,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + llgfrl %r0, -2 +#CHECK: llgfrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x0e,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + llgfrl %r0, 0 +#CHECK: llgfrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x0e,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + llgfrl %r0, 0xfffffffe #CHECK: llgfrl %r0, foo # encoding: [0xc4,0x0e,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-llghrl-01.s b/test/MC/SystemZ/insn-llghrl-01.s index af3fa8b9d7..d9b0d01125 100644 --- a/test/MC/SystemZ/insn-llghrl-01.s +++ b/test/MC/SystemZ/insn-llghrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: llghrl %r0, 2864434397 # encoding: [0xc4,0x06,0x55,0x5d,0xe6,0x6e] -#CHECK: llghrl %r15, 2864434397 # encoding: [0xc4,0xf6,0x55,0x5d,0xe6,0x6e] - - llghrl %r0,0xaabbccdd - llghrl %r15,0xaabbccdd +#CHECK: llghrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x06,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + llghrl %r0, -0x100000000 +#CHECK: llghrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x06,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + llghrl %r0, -2 +#CHECK: llghrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x06,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + llghrl %r0, 0 +#CHECK: llghrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x06,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + llghrl %r0, 0xfffffffe #CHECK: llghrl %r0, foo # encoding: [0xc4,0x06,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-llhrl-01.s b/test/MC/SystemZ/insn-llhrl-01.s index 30ed4f9056..d6bf8b9813 100644 --- a/test/MC/SystemZ/insn-llhrl-01.s +++ b/test/MC/SystemZ/insn-llhrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: llhrl %r0, 2864434397 # encoding: [0xc4,0x02,0x55,0x5d,0xe6,0x6e] -#CHECK: llhrl %r15, 2864434397 # encoding: [0xc4,0xf2,0x55,0x5d,0xe6,0x6e] - - llhrl %r0,0xaabbccdd - llhrl %r15,0xaabbccdd +#CHECK: llhrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x02,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + llhrl %r0, -0x100000000 +#CHECK: llhrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x02,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + llhrl %r0, -2 +#CHECK: llhrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x02,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + llhrl %r0, 0 +#CHECK: llhrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x02,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + llhrl %r0, 0xfffffffe #CHECK: llhrl %r0, foo # encoding: [0xc4,0x02,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-lrl-01.s b/test/MC/SystemZ/insn-lrl-01.s index 32d0eeb2b8..afe862c778 100644 --- a/test/MC/SystemZ/insn-lrl-01.s +++ b/test/MC/SystemZ/insn-lrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: lrl %r0, 2864434397 # encoding: [0xc4,0x0d,0x55,0x5d,0xe6,0x6e] -#CHECK: lrl %r15, 2864434397 # encoding: [0xc4,0xfd,0x55,0x5d,0xe6,0x6e] - - lrl %r0,0xaabbccdd - lrl %r15,0xaabbccdd +#CHECK: lrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0d,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + lrl %r0, -0x100000000 +#CHECK: lrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x0d,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + lrl %r0, -2 +#CHECK: lrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x0d,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + lrl %r0, 0 +#CHECK: lrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x0d,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + lrl %r0, 0xfffffffe #CHECK: lrl %r0, foo # encoding: [0xc4,0x0d,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-stgrl-01.s b/test/MC/SystemZ/insn-stgrl-01.s index 729b01dc11..dc31a49788 100644 --- a/test/MC/SystemZ/insn-stgrl-01.s +++ b/test/MC/SystemZ/insn-stgrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: stgrl %r0, 2864434397 # encoding: [0xc4,0x0b,0x55,0x5d,0xe6,0x6e] -#CHECK: stgrl %r15, 2864434397 # encoding: [0xc4,0xfb,0x55,0x5d,0xe6,0x6e] - - stgrl %r0,0xaabbccdd - stgrl %r15,0xaabbccdd +#CHECK: stgrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0b,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + stgrl %r0, -0x100000000 +#CHECK: stgrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x0b,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + stgrl %r0, -2 +#CHECK: stgrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x0b,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + stgrl %r0, 0 +#CHECK: stgrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x0b,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + stgrl %r0, 0xfffffffe #CHECK: stgrl %r0, foo # encoding: [0xc4,0x0b,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-sthrl-01.s b/test/MC/SystemZ/insn-sthrl-01.s index 0bcdbd4bc8..b0a6194558 100644 --- a/test/MC/SystemZ/insn-sthrl-01.s +++ b/test/MC/SystemZ/insn-sthrl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: sthrl %r0, 2864434397 # encoding: [0xc4,0x07,0x55,0x5d,0xe6,0x6e] -#CHECK: sthrl %r15, 2864434397 # encoding: [0xc4,0xf7,0x55,0x5d,0xe6,0x6e] - - sthrl %r0,0xaabbccdd - sthrl %r15,0xaabbccdd +#CHECK: sthrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x07,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + sthrl %r0, -0x100000000 +#CHECK: sthrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x07,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + sthrl %r0, -2 +#CHECK: sthrl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x07,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + sthrl %r0, 0 +#CHECK: sthrl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x07,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + sthrl %r0, 0xfffffffe #CHECK: sthrl %r0, foo # encoding: [0xc4,0x07,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL diff --git a/test/MC/SystemZ/insn-strl-01.s b/test/MC/SystemZ/insn-strl-01.s index 84bd41f4c0..a7d7245530 100644 --- a/test/MC/SystemZ/insn-strl-01.s +++ b/test/MC/SystemZ/insn-strl-01.s @@ -1,10 +1,17 @@ # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s -#CHECK: strl %r0, 2864434397 # encoding: [0xc4,0x0f,0x55,0x5d,0xe6,0x6e] -#CHECK: strl %r15, 2864434397 # encoding: [0xc4,0xff,0x55,0x5d,0xe6,0x6e] - - strl %r0,0xaabbccdd - strl %r15,0xaabbccdd +#CHECK: strl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0f,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL + strl %r0, -0x100000000 +#CHECK: strl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x0f,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL + strl %r0, -2 +#CHECK: strl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x0f,A,A,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL + strl %r0, 0 +#CHECK: strl %r0, .[[LAB:L.*]]+4294967294 # encoding: [0xc4,0x0f,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL + strl %r0, 0xfffffffe #CHECK: strl %r0, foo # encoding: [0xc4,0x0f,A,A,A,A] # fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL -- cgit v1.2.3 From 847cb575a1533777f45239a8136446e02c202763 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 14 May 2013 09:49:11 +0000 Subject: [SystemZ] Add extra testscases for r181773 Forgot to svn add these... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181774 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/SystemZ/insn-bras-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-brasl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-cgfrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-cghrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-cgrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-chrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-clgfrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-clghrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-clgrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-clhrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-clrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-crl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-larl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-lgfrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-lghrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-lgrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-lhrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-llgfrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-llghrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-llhrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-lrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-stgrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-sthrl-02.s | 16 ++++++++++++++++ test/MC/SystemZ/insn-strl-02.s | 16 ++++++++++++++++ 24 files changed, 384 insertions(+) create mode 100644 test/MC/SystemZ/insn-bras-02.s create mode 100644 test/MC/SystemZ/insn-brasl-02.s create mode 100644 test/MC/SystemZ/insn-cgfrl-02.s create mode 100644 test/MC/SystemZ/insn-cghrl-02.s create mode 100644 test/MC/SystemZ/insn-cgrl-02.s create mode 100644 test/MC/SystemZ/insn-chrl-02.s create mode 100644 test/MC/SystemZ/insn-clgfrl-02.s create mode 100644 test/MC/SystemZ/insn-clghrl-02.s create mode 100644 test/MC/SystemZ/insn-clgrl-02.s create mode 100644 test/MC/SystemZ/insn-clhrl-02.s create mode 100644 test/MC/SystemZ/insn-clrl-02.s create mode 100644 test/MC/SystemZ/insn-crl-02.s create mode 100644 test/MC/SystemZ/insn-larl-02.s create mode 100644 test/MC/SystemZ/insn-lgfrl-02.s create mode 100644 test/MC/SystemZ/insn-lghrl-02.s create mode 100644 test/MC/SystemZ/insn-lgrl-02.s create mode 100644 test/MC/SystemZ/insn-lhrl-02.s create mode 100644 test/MC/SystemZ/insn-llgfrl-02.s create mode 100644 test/MC/SystemZ/insn-llghrl-02.s create mode 100644 test/MC/SystemZ/insn-llhrl-02.s create mode 100644 test/MC/SystemZ/insn-lrl-02.s create mode 100644 test/MC/SystemZ/insn-stgrl-02.s create mode 100644 test/MC/SystemZ/insn-sthrl-02.s create mode 100644 test/MC/SystemZ/insn-strl-02.s diff --git a/test/MC/SystemZ/insn-bras-02.s b/test/MC/SystemZ/insn-bras-02.s new file mode 100644 index 0000000000..77210e1949 --- /dev/null +++ b/test/MC/SystemZ/insn-bras-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: bras %r0, -0x100002 +#CHECK: error: offset out of range +#CHECK: bras %r0, -1 +#CHECK: error: offset out of range +#CHECK: bras %r0, 1 +#CHECK: error: offset out of range +#CHECK: bras %r0, 0x10000 + + bras %r0, -0x100002 + bras %r0, -1 + bras %r0, 1 + bras %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-brasl-02.s b/test/MC/SystemZ/insn-brasl-02.s new file mode 100644 index 0000000000..783bc83a9a --- /dev/null +++ b/test/MC/SystemZ/insn-brasl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: brasl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: brasl %r0, -1 +#CHECK: error: offset out of range +#CHECK: brasl %r0, 1 +#CHECK: error: offset out of range +#CHECK: brasl %r0, 0x100000000 + + brasl %r0, -0x1000000002 + brasl %r0, -1 + brasl %r0, 1 + brasl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-cgfrl-02.s b/test/MC/SystemZ/insn-cgfrl-02.s new file mode 100644 index 0000000000..6cc42571d3 --- /dev/null +++ b/test/MC/SystemZ/insn-cgfrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: cgfrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: cgfrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: cgfrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: cgfrl %r0, 0x100000000 + + cgfrl %r0, -0x1000000002 + cgfrl %r0, -1 + cgfrl %r0, 1 + cgfrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-cghrl-02.s b/test/MC/SystemZ/insn-cghrl-02.s new file mode 100644 index 0000000000..100a7ab982 --- /dev/null +++ b/test/MC/SystemZ/insn-cghrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: cghrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: cghrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: cghrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: cghrl %r0, 0x100000000 + + cghrl %r0, -0x1000000002 + cghrl %r0, -1 + cghrl %r0, 1 + cghrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-cgrl-02.s b/test/MC/SystemZ/insn-cgrl-02.s new file mode 100644 index 0000000000..ecf734eb41 --- /dev/null +++ b/test/MC/SystemZ/insn-cgrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: cgrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: cgrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: cgrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: cgrl %r0, 0x100000000 + + cgrl %r0, -0x1000000002 + cgrl %r0, -1 + cgrl %r0, 1 + cgrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-chrl-02.s b/test/MC/SystemZ/insn-chrl-02.s new file mode 100644 index 0000000000..8128a568da --- /dev/null +++ b/test/MC/SystemZ/insn-chrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: chrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: chrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: chrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: chrl %r0, 0x100000000 + + chrl %r0, -0x1000000002 + chrl %r0, -1 + chrl %r0, 1 + chrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-clgfrl-02.s b/test/MC/SystemZ/insn-clgfrl-02.s new file mode 100644 index 0000000000..5afa5dc6a1 --- /dev/null +++ b/test/MC/SystemZ/insn-clgfrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: clgfrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: clgfrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: clgfrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: clgfrl %r0, 0x100000000 + + clgfrl %r0, -0x1000000002 + clgfrl %r0, -1 + clgfrl %r0, 1 + clgfrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-clghrl-02.s b/test/MC/SystemZ/insn-clghrl-02.s new file mode 100644 index 0000000000..a37a625458 --- /dev/null +++ b/test/MC/SystemZ/insn-clghrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: clghrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: clghrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: clghrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: clghrl %r0, 0x100000000 + + clghrl %r0, -0x1000000002 + clghrl %r0, -1 + clghrl %r0, 1 + clghrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-clgrl-02.s b/test/MC/SystemZ/insn-clgrl-02.s new file mode 100644 index 0000000000..b0889a8249 --- /dev/null +++ b/test/MC/SystemZ/insn-clgrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: clgrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: clgrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: clgrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: clgrl %r0, 0x100000000 + + clgrl %r0, -0x1000000002 + clgrl %r0, -1 + clgrl %r0, 1 + clgrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-clhrl-02.s b/test/MC/SystemZ/insn-clhrl-02.s new file mode 100644 index 0000000000..90fecd2b9c --- /dev/null +++ b/test/MC/SystemZ/insn-clhrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: clhrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: clhrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: clhrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: clhrl %r0, 0x100000000 + + clhrl %r0, -0x1000000002 + clhrl %r0, -1 + clhrl %r0, 1 + clhrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-clrl-02.s b/test/MC/SystemZ/insn-clrl-02.s new file mode 100644 index 0000000000..bc4c19b3b2 --- /dev/null +++ b/test/MC/SystemZ/insn-clrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: clrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: clrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: clrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: clrl %r0, 0x100000000 + + clrl %r0, -0x1000000002 + clrl %r0, -1 + clrl %r0, 1 + clrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-crl-02.s b/test/MC/SystemZ/insn-crl-02.s new file mode 100644 index 0000000000..fc988f76b9 --- /dev/null +++ b/test/MC/SystemZ/insn-crl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: crl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: crl %r0, -1 +#CHECK: error: offset out of range +#CHECK: crl %r0, 1 +#CHECK: error: offset out of range +#CHECK: crl %r0, 0x100000000 + + crl %r0, -0x1000000002 + crl %r0, -1 + crl %r0, 1 + crl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-larl-02.s b/test/MC/SystemZ/insn-larl-02.s new file mode 100644 index 0000000000..67c2a60b56 --- /dev/null +++ b/test/MC/SystemZ/insn-larl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: larl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: larl %r0, -1 +#CHECK: error: offset out of range +#CHECK: larl %r0, 1 +#CHECK: error: offset out of range +#CHECK: larl %r0, 0x100000000 + + larl %r0, -0x1000000002 + larl %r0, -1 + larl %r0, 1 + larl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-lgfrl-02.s b/test/MC/SystemZ/insn-lgfrl-02.s new file mode 100644 index 0000000000..ab475b4625 --- /dev/null +++ b/test/MC/SystemZ/insn-lgfrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: lgfrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: lgfrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: lgfrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: lgfrl %r0, 0x100000000 + + lgfrl %r0, -0x1000000002 + lgfrl %r0, -1 + lgfrl %r0, 1 + lgfrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-lghrl-02.s b/test/MC/SystemZ/insn-lghrl-02.s new file mode 100644 index 0000000000..6f57b2b6ec --- /dev/null +++ b/test/MC/SystemZ/insn-lghrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: lghrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: lghrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: lghrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: lghrl %r0, 0x100000000 + + lghrl %r0, -0x1000000002 + lghrl %r0, -1 + lghrl %r0, 1 + lghrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-lgrl-02.s b/test/MC/SystemZ/insn-lgrl-02.s new file mode 100644 index 0000000000..5a21b00ade --- /dev/null +++ b/test/MC/SystemZ/insn-lgrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: lgrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: lgrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: lgrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: lgrl %r0, 0x100000000 + + lgrl %r0, -0x1000000002 + lgrl %r0, -1 + lgrl %r0, 1 + lgrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-lhrl-02.s b/test/MC/SystemZ/insn-lhrl-02.s new file mode 100644 index 0000000000..cca348ccb4 --- /dev/null +++ b/test/MC/SystemZ/insn-lhrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: lhrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: lhrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: lhrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: lhrl %r0, 0x100000000 + + lhrl %r0, -0x1000000002 + lhrl %r0, -1 + lhrl %r0, 1 + lhrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-llgfrl-02.s b/test/MC/SystemZ/insn-llgfrl-02.s new file mode 100644 index 0000000000..f65585cf4f --- /dev/null +++ b/test/MC/SystemZ/insn-llgfrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: llgfrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: llgfrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: llgfrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: llgfrl %r0, 0x100000000 + + llgfrl %r0, -0x1000000002 + llgfrl %r0, -1 + llgfrl %r0, 1 + llgfrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-llghrl-02.s b/test/MC/SystemZ/insn-llghrl-02.s new file mode 100644 index 0000000000..b6bf592eee --- /dev/null +++ b/test/MC/SystemZ/insn-llghrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: llghrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: llghrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: llghrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: llghrl %r0, 0x100000000 + + llghrl %r0, -0x1000000002 + llghrl %r0, -1 + llghrl %r0, 1 + llghrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-llhrl-02.s b/test/MC/SystemZ/insn-llhrl-02.s new file mode 100644 index 0000000000..083301263a --- /dev/null +++ b/test/MC/SystemZ/insn-llhrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: llhrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: llhrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: llhrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: llhrl %r0, 0x100000000 + + llhrl %r0, -0x1000000002 + llhrl %r0, -1 + llhrl %r0, 1 + llhrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-lrl-02.s b/test/MC/SystemZ/insn-lrl-02.s new file mode 100644 index 0000000000..ab2603314a --- /dev/null +++ b/test/MC/SystemZ/insn-lrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: lrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: lrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: lrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: lrl %r0, 0x100000000 + + lrl %r0, -0x1000000002 + lrl %r0, -1 + lrl %r0, 1 + lrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-stgrl-02.s b/test/MC/SystemZ/insn-stgrl-02.s new file mode 100644 index 0000000000..778368d66c --- /dev/null +++ b/test/MC/SystemZ/insn-stgrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: stgrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: stgrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: stgrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: stgrl %r0, 0x100000000 + + stgrl %r0, -0x1000000002 + stgrl %r0, -1 + stgrl %r0, 1 + stgrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-sthrl-02.s b/test/MC/SystemZ/insn-sthrl-02.s new file mode 100644 index 0000000000..432345fa2f --- /dev/null +++ b/test/MC/SystemZ/insn-sthrl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: sthrl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: sthrl %r0, -1 +#CHECK: error: offset out of range +#CHECK: sthrl %r0, 1 +#CHECK: error: offset out of range +#CHECK: sthrl %r0, 0x100000000 + + sthrl %r0, -0x1000000002 + sthrl %r0, -1 + sthrl %r0, 1 + sthrl %r0, 0x100000000 diff --git a/test/MC/SystemZ/insn-strl-02.s b/test/MC/SystemZ/insn-strl-02.s new file mode 100644 index 0000000000..11d5e26896 --- /dev/null +++ b/test/MC/SystemZ/insn-strl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: offset out of range +#CHECK: strl %r0, -0x1000000002 +#CHECK: error: offset out of range +#CHECK: strl %r0, -1 +#CHECK: error: offset out of range +#CHECK: strl %r0, 1 +#CHECK: error: offset out of range +#CHECK: strl %r0, 0x100000000 + + strl %r0, -0x1000000002 + strl %r0, -1 + strl %r0, 1 + strl %r0, 0x100000000 -- cgit v1.2.3 From 5096dc74ae0df903d54085af3a57fa66b382493c Mon Sep 17 00:00:00 2001 From: Michel Danzer Date: Tue, 14 May 2013 09:53:30 +0000 Subject: R600/SI: Add lit test coverage for the remaining patterns added recently MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181775 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/R600/llvm.AMDGPU.imax.ll | 21 +++++++++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.imin.ll | 21 +++++++++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.trunc.ll | 22 +++++++++++----------- test/CodeGen/R600/llvm.AMDGPU.umax.ll | 21 +++++++++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.umin.ll | 21 +++++++++++++++++++++ test/CodeGen/R600/uitofp.ll | 16 ++++++++++++++++ 6 files changed, 111 insertions(+), 11 deletions(-) create mode 100644 test/CodeGen/R600/llvm.AMDGPU.imax.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.imin.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.umax.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.umin.ll create mode 100644 test/CodeGen/R600/uitofp.ll diff --git a/test/CodeGen/R600/llvm.AMDGPU.imax.ll b/test/CodeGen/R600/llvm.AMDGPU.imax.ll new file mode 100644 index 0000000000..3e854c840f --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.imax.ll @@ -0,0 +1,21 @@ +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s + +;CHECK: V_MAX_I32_e32 + +define void @main(i32 %p0, i32 %p1) #0 { +main_body: + %0 = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %p1) + %1 = bitcast i32 %0 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1) + ret void +} + +; Function Attrs: readnone +declare i32 @llvm.AMDGPU.imax(i32, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/llvm.AMDGPU.imin.ll b/test/CodeGen/R600/llvm.AMDGPU.imin.ll new file mode 100644 index 0000000000..e227bf8d55 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.imin.ll @@ -0,0 +1,21 @@ +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s + +;CHECK: V_MIN_I32_e32 + +define void @main(i32 %p0, i32 %p1) #0 { +main_body: + %0 = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %p1) + %1 = bitcast i32 %0 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1) + ret void +} + +; Function Attrs: readnone +declare i32 @llvm.AMDGPU.imin(i32, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll index ff22a69196..cdc03f8a41 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll @@ -1,16 +1,16 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s -;CHECK: TRUNC * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: @amdgpu_trunc +; R600-CHECK: TRUNC * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; SI-CHECK: @amdgpu_trunc +; SI-CHECK: V_TRUNC_F32 -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.AMDGPU.trunc( float %r0) - call void @llvm.AMDGPU.store.output(float %r1, i32 0) - ret void +define void @amdgpu_trunc(float addrspace(1)* %out, float %x) { +entry: + %0 = call float @llvm.AMDGPU.trunc(float %x) + store float %0, float addrspace(1)* %out + ret void } -declare float @llvm.R600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) - declare float @llvm.AMDGPU.trunc(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.umax.ll b/test/CodeGen/R600/llvm.AMDGPU.umax.ll new file mode 100644 index 0000000000..7699c04c36 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.umax.ll @@ -0,0 +1,21 @@ +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s + +;CHECK: V_MAX_U32_e32 + +define void @main(i32 %p0, i32 %p1) #0 { +main_body: + %0 = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1) + %1 = bitcast i32 %0 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1) + ret void +} + +; Function Attrs: readnone +declare i32 @llvm.AMDGPU.umax(i32, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/llvm.AMDGPU.umin.ll b/test/CodeGen/R600/llvm.AMDGPU.umin.ll new file mode 100644 index 0000000000..a911ad9bb3 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.umin.ll @@ -0,0 +1,21 @@ +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s + +;CHECK: V_MIN_U32_e32 + +define void @main(i32 %p0, i32 %p1) #0 { +main_body: + %0 = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1) + %1 = bitcast i32 %0 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1) + ret void +} + +; Function Attrs: readnone +declare i32 @llvm.AMDGPU.umin(i32, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/uitofp.ll b/test/CodeGen/R600/uitofp.ll new file mode 100644 index 0000000000..6cf9e6a225 --- /dev/null +++ b/test/CodeGen/R600/uitofp.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s + +;CHECK: V_CVT_F32_U32_e32 + +define void @main(i32 %p) #0 { +main_body: + %0 = uitofp i32 %p to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %0, float %0, float %0, float %0) + ret void +} + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } + +!0 = metadata !{metadata !"const", null, i32 1} -- cgit v1.2.3 From c3b20c260ee17a66c6306f81293c75681d8ea0aa Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 14 May 2013 10:17:52 +0000 Subject: [SystemZ] Add disassembler support git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181777 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/CodeGenerator.rst | 2 +- lib/Target/SystemZ/CMakeLists.txt | 2 + lib/Target/SystemZ/Disassembler/CMakeLists.txt | 7 + lib/Target/SystemZ/Disassembler/LLVMBuild.txt | 23 ++ lib/Target/SystemZ/Disassembler/Makefile | 16 ++ .../SystemZ/Disassembler/SystemZDisassembler.cpp | 301 +++++++++++++++++++++ .../SystemZ/InstPrinter/SystemZInstPrinter.cpp | 20 +- .../SystemZ/InstPrinter/SystemZInstPrinter.h | 1 + lib/Target/SystemZ/LLVMBuild.txt | 3 +- lib/Target/SystemZ/Makefile | 3 +- lib/Target/SystemZ/SystemZInstrFormats.td | 16 ++ lib/Target/SystemZ/SystemZOperands.td | 13 +- test/MC/Disassembler/SystemZ/insn-a.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-adb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-adbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-aeb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-aebr.txt | 12 + test/MC/Disassembler/SystemZ/insn-afi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-ag.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-agf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-agfi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-agfr.txt | 12 + test/MC/Disassembler/SystemZ/insn-aghi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-agr.txt | 12 + test/MC/Disassembler/SystemZ/insn-agsi.txt | 39 +++ test/MC/Disassembler/SystemZ/insn-ah.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-ahi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-ahy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-al.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-alc.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-alcg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-alcgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-alcr.txt | 12 + test/MC/Disassembler/SystemZ/insn-alfi.txt | 9 + test/MC/Disassembler/SystemZ/insn-alg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-algf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-algfi.txt | 9 + test/MC/Disassembler/SystemZ/insn-algfr.txt | 12 + test/MC/Disassembler/SystemZ/insn-algr.txt | 12 + test/MC/Disassembler/SystemZ/insn-alr.txt | 12 + test/MC/Disassembler/SystemZ/insn-aly.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-ar.txt | 12 + test/MC/Disassembler/SystemZ/insn-asi.txt | 39 +++ test/MC/Disassembler/SystemZ/insn-axbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-ay.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-basr.txt | 12 + test/MC/Disassembler/SystemZ/insn-br.txt | 9 + test/MC/Disassembler/SystemZ/insn-bras.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-brasl.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-brc.txt | 66 +++++ test/MC/Disassembler/SystemZ/insn-brcl.txt | 66 +++++ test/MC/Disassembler/SystemZ/insn-c.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-cdb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-cdbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-cdfbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cdgbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-ceb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-cebr.txt | 12 + test/MC/Disassembler/SystemZ/insn-cefbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cegbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cfdbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cfebr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cfi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-cfxbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-cgdbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cgebr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cgf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-cgfi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-cgfr.txt | 12 + test/MC/Disassembler/SystemZ/insn-cgfrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-cgh.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-cghi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-cghrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-cghsi.txt | 33 +++ test/MC/Disassembler/SystemZ/insn-cgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-cgrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-cgxbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-ch.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-chhsi.txt | 33 +++ test/MC/Disassembler/SystemZ/insn-chi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-chrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-chsi.txt | 33 +++ test/MC/Disassembler/SystemZ/insn-chy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-cl.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-clfhsi.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-clfi.txt | 9 + test/MC/Disassembler/SystemZ/insn-clg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-clgf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-clgfi.txt | 9 + test/MC/Disassembler/SystemZ/insn-clgfr.txt | 12 + test/MC/Disassembler/SystemZ/insn-clgfrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-clghrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-clghsi.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-clgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-clgrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-clhhsi.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-clhrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-cli.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-cliy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-clr.txt | 12 + test/MC/Disassembler/SystemZ/insn-clrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-cly.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-cpsdr.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-cr.txt | 12 + test/MC/Disassembler/SystemZ/insn-crl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-cs.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-csg.txt | 33 +++ test/MC/Disassembler/SystemZ/insn-csy.txt | 33 +++ test/MC/Disassembler/SystemZ/insn-cxbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-cxfbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cxgbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-cy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-ddb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-ddbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-deb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-debr.txt | 12 + test/MC/Disassembler/SystemZ/insn-dl.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-dlg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-dlgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-dlr.txt | 12 + test/MC/Disassembler/SystemZ/insn-dsg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-dsgf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-dsgfr.txt | 12 + test/MC/Disassembler/SystemZ/insn-dsgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-dxbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-ear.txt | 15 + test/MC/Disassembler/SystemZ/insn-fidbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-fiebr.txt | 15 + test/MC/Disassembler/SystemZ/insn-fixbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-flogr.txt | 12 + test/MC/Disassembler/SystemZ/insn-ic.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-icy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-iihf.txt | 9 + test/MC/Disassembler/SystemZ/insn-iihh.txt | 12 + test/MC/Disassembler/SystemZ/insn-iihl.txt | 12 + test/MC/Disassembler/SystemZ/insn-iilf.txt | 9 + test/MC/Disassembler/SystemZ/insn-iilh.txt | 12 + test/MC/Disassembler/SystemZ/insn-iill.txt | 12 + test/MC/Disassembler/SystemZ/insn-l.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-la.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-larl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-lay.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lb.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lbr.txt | 9 + test/MC/Disassembler/SystemZ/insn-lcdbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lcebr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lcgfr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lcgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lcr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lcxbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-ld.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-ldeb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-ldebr.txt | 9 + test/MC/Disassembler/SystemZ/insn-ldgr.txt | 15 + test/MC/Disassembler/SystemZ/insn-ldr.txt | 12 + test/MC/Disassembler/SystemZ/insn-ldxbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-ldy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-le.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-ledbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-ler.txt | 12 + test/MC/Disassembler/SystemZ/insn-lexbr.txt | 15 + test/MC/Disassembler/SystemZ/insn-ley.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lgb.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lgbr.txt | 9 + test/MC/Disassembler/SystemZ/insn-lgdr.txt | 15 + test/MC/Disassembler/SystemZ/insn-lgf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lgfi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-lgfr.txt | 9 + test/MC/Disassembler/SystemZ/insn-lgfrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-lgh.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lghi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-lghr.txt | 9 + test/MC/Disassembler/SystemZ/insn-lghrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-lgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lgrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-lh.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-lhi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-lhr.txt | 9 + test/MC/Disassembler/SystemZ/insn-lhrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-lhy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-llc.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-llcr.txt | 9 + test/MC/Disassembler/SystemZ/insn-llgc.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-llgcr.txt | 9 + test/MC/Disassembler/SystemZ/insn-llgf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-llgfr.txt | 9 + test/MC/Disassembler/SystemZ/insn-llgfrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-llgh.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-llghr.txt | 9 + test/MC/Disassembler/SystemZ/insn-llghrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-llh.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-llhr.txt | 9 + test/MC/Disassembler/SystemZ/insn-llhrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-llihf.txt | 9 + test/MC/Disassembler/SystemZ/insn-llihh.txt | 12 + test/MC/Disassembler/SystemZ/insn-llihl.txt | 12 + test/MC/Disassembler/SystemZ/insn-llilf.txt | 9 + test/MC/Disassembler/SystemZ/insn-llilh.txt | 12 + test/MC/Disassembler/SystemZ/insn-llill.txt | 12 + test/MC/Disassembler/SystemZ/insn-lmg.txt | 39 +++ test/MC/Disassembler/SystemZ/insn-lndbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lnebr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lnxbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lpdbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lpebr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lpxbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lr.txt | 12 + test/MC/Disassembler/SystemZ/insn-lrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-lrv.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lrvg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lrvgr.txt | 15 + test/MC/Disassembler/SystemZ/insn-lrvr.txt | 15 + test/MC/Disassembler/SystemZ/insn-lxr.txt | 12 + test/MC/Disassembler/SystemZ/insn-ly.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-lzdr.txt | 9 + test/MC/Disassembler/SystemZ/insn-lzer.txt | 9 + test/MC/Disassembler/SystemZ/insn-lzxr.txt | 9 + test/MC/Disassembler/SystemZ/insn-madb.txt | 27 ++ test/MC/Disassembler/SystemZ/insn-madbr.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-maeb.txt | 27 ++ test/MC/Disassembler/SystemZ/insn-maebr.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-mdb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-mdbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-mdeb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-mdebr.txt | 12 + test/MC/Disassembler/SystemZ/insn-meeb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-meebr.txt | 12 + test/MC/Disassembler/SystemZ/insn-mghi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-mh.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-mhi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-mhy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-mlg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-mlgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-ms.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-msdb.txt | 27 ++ test/MC/Disassembler/SystemZ/insn-msdbr.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-mseb.txt | 27 ++ test/MC/Disassembler/SystemZ/insn-msebr.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-msfi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-msg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-msgf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-msgfi.txt | 18 ++ test/MC/Disassembler/SystemZ/insn-msgfr.txt | 12 + test/MC/Disassembler/SystemZ/insn-msgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-msr.txt | 12 + test/MC/Disassembler/SystemZ/insn-msy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-mvghi.txt | 33 +++ test/MC/Disassembler/SystemZ/insn-mvhhi.txt | 33 +++ test/MC/Disassembler/SystemZ/insn-mvhi.txt | 33 +++ test/MC/Disassembler/SystemZ/insn-mvi.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-mviy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-mxbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-mxdb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-mxdbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-n.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-ng.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-ngr.txt | 12 + test/MC/Disassembler/SystemZ/insn-ni.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-nihf.txt | 9 + test/MC/Disassembler/SystemZ/insn-nihh.txt | 12 + test/MC/Disassembler/SystemZ/insn-nihl.txt | 12 + test/MC/Disassembler/SystemZ/insn-nilf.txt | 9 + test/MC/Disassembler/SystemZ/insn-nilh.txt | 12 + test/MC/Disassembler/SystemZ/insn-nill.txt | 12 + test/MC/Disassembler/SystemZ/insn-niy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-nr.txt | 12 + test/MC/Disassembler/SystemZ/insn-ny.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-o.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-og.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-ogr.txt | 12 + test/MC/Disassembler/SystemZ/insn-oi.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-oihf.txt | 9 + test/MC/Disassembler/SystemZ/insn-oihh.txt | 12 + test/MC/Disassembler/SystemZ/insn-oihl.txt | 12 + test/MC/Disassembler/SystemZ/insn-oilf.txt | 9 + test/MC/Disassembler/SystemZ/insn-oilh.txt | 12 + test/MC/Disassembler/SystemZ/insn-oill.txt | 12 + test/MC/Disassembler/SystemZ/insn-oiy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-or.txt | 12 + test/MC/Disassembler/SystemZ/insn-oy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-risbg.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-rll.txt | 36 +++ test/MC/Disassembler/SystemZ/insn-rllg.txt | 36 +++ test/MC/Disassembler/SystemZ/insn-s.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-sdb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-sdbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-seb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-sebr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-sgf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-sgfr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sl.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-slb.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-slbg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-slbgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-slbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-slfi.txt | 9 + test/MC/Disassembler/SystemZ/insn-slg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-slgf.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-slgfi.txt | 9 + test/MC/Disassembler/SystemZ/insn-slgfr.txt | 12 + test/MC/Disassembler/SystemZ/insn-slgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sll.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-sllg.txt | 36 +++ test/MC/Disassembler/SystemZ/insn-slr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sly.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-sqdb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-sqdbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sqeb.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-sqebr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sqxbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sra.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-srag.txt | 36 +++ test/MC/Disassembler/SystemZ/insn-srl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-srlg.txt | 36 +++ test/MC/Disassembler/SystemZ/insn-st.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-stc.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-stcy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-std.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-stdy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-ste.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-stey.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-stg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-stgrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-sth.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-sthrl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-sthy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-stmg.txt | 39 +++ test/MC/Disassembler/SystemZ/insn-strl.txt | 24 ++ test/MC/Disassembler/SystemZ/insn-strv.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-strvg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-sty.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-sxbr.txt | 12 + test/MC/Disassembler/SystemZ/insn-sy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-x.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-xg.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-xgr.txt | 12 + test/MC/Disassembler/SystemZ/insn-xi.txt | 21 ++ test/MC/Disassembler/SystemZ/insn-xihf.txt | 9 + test/MC/Disassembler/SystemZ/insn-xilf.txt | 9 + test/MC/Disassembler/SystemZ/insn-xiy.txt | 30 ++ test/MC/Disassembler/SystemZ/insn-xr.txt | 12 + test/MC/Disassembler/SystemZ/insn-xy.txt | 30 ++ test/MC/Disassembler/SystemZ/invalid-regs-01.txt | 22 ++ test/MC/Disassembler/SystemZ/lit.local.cfg | 6 + test/MC/Disassembler/SystemZ/trunc-01.txt | 5 + test/MC/Disassembler/SystemZ/trunc-02.txt | 5 + test/MC/Disassembler/SystemZ/trunc-03.txt | 5 + test/MC/Disassembler/SystemZ/unmapped-01.txt | 32 +++ 353 files changed, 7189 insertions(+), 7 deletions(-) create mode 100644 lib/Target/SystemZ/Disassembler/CMakeLists.txt create mode 100644 lib/Target/SystemZ/Disassembler/LLVMBuild.txt create mode 100644 lib/Target/SystemZ/Disassembler/Makefile create mode 100644 lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp create mode 100644 test/MC/Disassembler/SystemZ/insn-a.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-adb.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-adbr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-aeb.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-aebr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-afi.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-ag.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-agf.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-agfi.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-agfr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-aghi.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-agr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-agsi.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-ah.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-ahi.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-ahy.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-al.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-alc.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-alcg.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-alcgr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-alcr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-alfi.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-alg.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-algf.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-algfi.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-algfr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-algr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-alr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-aly.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-ar.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-asi.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-axbr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-ay.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-basr.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-br.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-bras.txt create mode 100644 test/MC/Disassembler/SystemZ/insn-brasl.txt create mode 100644 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b/docs/CodeGenerator.rst index 10ca307b78..d54df0f6f4 100644 --- a/docs/CodeGenerator.rst +++ b/docs/CodeGenerator.rst @@ -1838,7 +1838,7 @@ Here is the table: :raw-html:` ` :raw-html:` ` :raw-html:` ` -:raw-html:` ` +:raw-html:` ` :raw-html:` ` :raw-html:` ` :raw-html:` ` diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt index 67b17fcc59..757d5a8898 100644 --- a/lib/Target/SystemZ/CMakeLists.txt +++ b/lib/Target/SystemZ/CMakeLists.txt @@ -4,6 +4,7 @@ tablegen(LLVM SystemZGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM SystemZGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv) tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel) +tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter -mc-emitter) tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info) tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info) @@ -27,6 +28,7 @@ add_llvm_target(SystemZCodeGen add_dependencies(LLVMSystemZCodeGen intrinsics_gen) add_subdirectory(AsmParser) +add_subdirectory(Disassembler) add_subdirectory(InstPrinter) add_subdirectory(TargetInfo) add_subdirectory(MCTargetDesc) diff --git a/lib/Target/SystemZ/Disassembler/CMakeLists.txt b/lib/Target/SystemZ/Disassembler/CMakeLists.txt new file mode 100644 index 0000000000..5bc1859816 --- /dev/null +++ b/lib/Target/SystemZ/Disassembler/CMakeLists.txt @@ -0,0 +1,7 @@ +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) + +add_llvm_library(LLVMSystemZDisassembler + SystemZDisassembler.cpp + ) + +add_dependencies(LLVMSystemZDisassembler SystemZCommonTableGen) diff --git a/lib/Target/SystemZ/Disassembler/LLVMBuild.txt b/lib/Target/SystemZ/Disassembler/LLVMBuild.txt new file mode 100644 index 0000000000..c3081f5447 --- /dev/null +++ b/lib/Target/SystemZ/Disassembler/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===-- ./lib/Target/SystemZ/Disassembler/LLVMBuild.txt ---------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = SystemZDisassembler +parent = SystemZ +required_libraries = MC Support SystemZDesc SystemZInfo +add_to_library_groups = SystemZ diff --git a/lib/Target/SystemZ/Disassembler/Makefile b/lib/Target/SystemZ/Disassembler/Makefile new file mode 100644 index 0000000000..efc4cc8e9c --- /dev/null +++ b/lib/Target/SystemZ/Disassembler/Makefile @@ -0,0 +1,16 @@ +##===-- lib/Target/SystemZ/Disassembler/Makefile -----------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMSystemZDisassembler + +# Hack: we need to include 'main' x86 target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp new file mode 100644 index 0000000000..9a9de78224 --- /dev/null +++ b/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -0,0 +1,301 @@ +//===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "SystemZ.h" +#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/MemoryObject.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +typedef MCDisassembler::DecodeStatus DecodeStatus; + +namespace { +class SystemZDisassembler : public MCDisassembler { +public: + SystemZDisassembler(const MCSubtargetInfo &STI) + : MCDisassembler(STI) {} + virtual ~SystemZDisassembler() {} + + // Override MCDisassembler. + virtual DecodeStatus getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const LLVM_OVERRIDE; +}; +} // end anonymous namespace + +static MCDisassembler *createSystemZDisassembler(const Target &T, + const MCSubtargetInfo &STI) { + return new SystemZDisassembler(STI); +} + +extern "C" void LLVMInitializeSystemZDisassembler() { + // Register the disassembler. + TargetRegistry::RegisterMCDisassembler(TheSystemZTarget, + createSystemZDisassembler); +} + +static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, + const unsigned *Regs, + bool isAddress = false) { + assert(RegNo < 16 && "Invalid register"); + if (!isAddress || RegNo) { + RegNo = Regs[RegNo]; + if (RegNo == 0) + return MCDisassembler::Fail; + } + Inst.addOperand(MCOperand::CreateReg(RegNo)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs); +} + +static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs); +} + +static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs); +} + +static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, true); +} + +static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs); +} + +static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs); +} + +static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs); +} + +template +static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { + assert(isUInt(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::CreateImm(Imm)); + return MCDisassembler::Success; +} + +template +static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { + assert(isUInt(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::CreateImm(SignExtend64(Imm))); + return MCDisassembler::Success; +} + +static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) { + return decodeUImmOperand<4>(Inst, Imm); +} + +static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeUImmOperand<4>(Inst, Imm); +} + +static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeUImmOperand<6>(Inst, Imm); +} + +static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeUImmOperand<8>(Inst, Imm); +} + +static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeUImmOperand<16>(Inst, Imm); +} + +static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeUImmOperand<32>(Inst, Imm); +} + +static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeSImmOperand<8>(Inst, Imm); +} + +static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeSImmOperand<16>(Inst, Imm); +} + +static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeSImmOperand<32>(Inst, Imm); +} + +template +static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address) { + assert(isUInt(Imm) && "Invalid PC-relative offset"); + Inst.addOperand(MCOperand::CreateImm(SignExtend64(Imm) * 2 + Address)); + return MCDisassembler::Success; +} + +static DecodeStatus decodePC16DBLOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) { + return decodePCDBLOperand<16>(Inst, Imm, Address); +} + +static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) { + return decodePCDBLOperand<32>(Inst, Imm, Address); +} + +static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Base = Field >> 12; + uint64_t Disp = Field & 0xfff; + assert(Base < 16 && "Invalid BDAddr12"); + Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); + Inst.addOperand(MCOperand::CreateImm(Disp)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Base = Field >> 20; + uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); + assert(Base < 16 && "Invalid BDAddr20"); + Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); + Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp))); + return MCDisassembler::Success; +} + +static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Index = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + assert(Index < 16 && "Invalid BDXAddr12"); + Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); + Inst.addOperand(MCOperand::CreateImm(Disp)); + Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); + return MCDisassembler::Success; +} + +static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Index = Field >> 24; + uint64_t Base = (Field >> 20) & 0xf; + uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); + assert(Index < 16 && "Invalid BDXAddr20"); + Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); + Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp))); + Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); + return MCDisassembler::Success; +} + +static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, + uint64_t Address, + const void *Decoder) { + return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs); +} + +static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field, + uint64_t Address, + const void *Decoder) { + return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs); +} + +static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field, + uint64_t Address, + const void *Decoder) { + return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs); +} + +static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field, + uint64_t Address, + const void *Decoder) { + return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs); +} + +static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, + uint64_t Address, + const void *Decoder) { + return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs); +} + +static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, + uint64_t Address, + const void *Decoder) { + return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs); +} + +#include "SystemZGenDisassemblerTables.inc" + +DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &os, + raw_ostream &cs) const { + // Get the first two bytes of the instruction. + uint8_t Bytes[6]; + Size = 0; + if (Region.readBytes(Address, 2, Bytes, 0) == -1) + return MCDisassembler::Fail; + + // The top 2 bits of the first byte specify the size. + const uint8_t *Table; + if (Bytes[0] < 0x40) { + Size = 2; + Table = DecoderTable16; + } else if (Bytes[0] < 0xc0) { + Size = 4; + Table = DecoderTable32; + } else { + Size = 6; + Table = DecoderTable48; + } + + // Read any remaining bytes. + if (Size > 2 && Region.readBytes(Address + 2, Size - 2, Bytes + 2, 0) == -1) + return MCDisassembler::Fail; + + // Construct the instruction. + uint64_t Inst = 0; + for (uint64_t I = 0; I < Size; ++I) + Inst = (Inst << 8) | Bytes[I]; + + return decodeInstruction(Table, MI, Inst, Address, this, STI); +} diff --git a/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp b/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp index d73cf49808..369802b2b8 100644 --- a/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp +++ b/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp @@ -114,10 +114,26 @@ void SystemZInstPrinter::printAccessRegOperand(const MCInst *MI, int OpNum, O << "%a" << (unsigned int)Value; } +void SystemZInstPrinter::printPCRelOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNum); + if (MO.isImm()) { + O << "0x"; + O.write_hex(MO.getImm()); + } else + O << *MO.getExpr(); +} + void SystemZInstPrinter::printCallOperand(const MCInst *MI, int OpNum, raw_ostream &O) { - printOperand(MI, OpNum, O); - O << "@PLT"; + const MCOperand &MO = MI->getOperand(OpNum); + if (MO.isImm()) { + O << "0x"; + O.write_hex(MO.getImm()); + } else { + O << *MO.getExpr(); + O << "@PLT"; + } } void SystemZInstPrinter::printOperand(const MCInst *MI, int OpNum, diff --git a/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h b/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h index b82e79d93c..f77282efcb 100644 --- a/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h +++ b/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h @@ -56,6 +56,7 @@ private: void printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printPCRelOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printCallOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printAccessRegOperand(const MCInst *MI, int OpNum, raw_ostream &O); diff --git a/lib/Target/SystemZ/LLVMBuild.txt b/lib/Target/SystemZ/LLVMBuild.txt index aba0de27ac..95e657f7bd 100644 --- a/lib/Target/SystemZ/LLVMBuild.txt +++ b/lib/Target/SystemZ/LLVMBuild.txt @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -24,6 +24,7 @@ name = SystemZ parent = Target has_asmparser = 1 has_asmprinter = 1 +has_disassembler = 1 has_jit = 1 [component_1] diff --git a/lib/Target/SystemZ/Makefile b/lib/Target/SystemZ/Makefile index c992584af9..445725bd1e 100644 --- a/lib/Target/SystemZ/Makefile +++ b/lib/Target/SystemZ/Makefile @@ -16,13 +16,14 @@ BUILT_SOURCES = SystemZGenRegisterInfo.inc \ SystemZGenAsmWriter.inc \ SystemZGenAsmMatcher.inc \ SystemZGenCodeEmitter.inc \ + SystemZGenDisassemblerTables.inc \ SystemZGenInstrInfo.inc \ SystemZGenDAGISel.inc \ SystemZGenSubtargetInfo.inc \ SystemZGenCallingConv.inc \ SystemZGenMCCodeEmitter.inc -DIRS = InstPrinter AsmParser TargetInfo MCTargetDesc +DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index b7511d50ff..bf5aa8dbeb 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -99,6 +99,7 @@ def getDisp20Opcode : InstrMapping { class InstRI op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; + field bits<32> SoftFail = 0; bits<4> R1; bits<16> I2; @@ -112,6 +113,7 @@ class InstRI op, dag outs, dag ins, string asmstr, list pattern> class InstRIEf op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; + field bits<48> SoftFail = 0; bits<4> R1; bits<4> R2; @@ -131,6 +133,7 @@ class InstRIEf op, dag outs, dag ins, string asmstr, list pattern> class InstRIL op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; + field bits<48> SoftFail = 0; bits<4> R1; bits<32> I2; @@ -144,6 +147,7 @@ class InstRIL op, dag outs, dag ins, string asmstr, list pattern> class InstRR op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<2, outs, ins, asmstr, pattern> { field bits<16> Inst; + field bits<16> SoftFail = 0; bits<4> R1; bits<4> R2; @@ -156,6 +160,7 @@ class InstRR op, dag outs, dag ins, string asmstr, list pattern> class InstRRD op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; + field bits<32> SoftFail = 0; bits<4> R1; bits<4> R3; @@ -171,6 +176,7 @@ class InstRRD op, dag outs, dag ins, string asmstr, list pattern> class InstRRE op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; + field bits<32> SoftFail = 0; bits<4> R1; bits<4> R2; @@ -184,6 +190,7 @@ class InstRRE op, dag outs, dag ins, string asmstr, list pattern> class InstRRF op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; + field bits<32> SoftFail = 0; bits<4> R1; bits<4> R2; @@ -199,6 +206,7 @@ class InstRRF op, dag outs, dag ins, string asmstr, list pattern> class InstRX op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; + field bits<32> SoftFail = 0; bits<4> R1; bits<20> XBD2; @@ -213,6 +221,7 @@ class InstRX op, dag outs, dag ins, string asmstr, list pattern> class InstRXE op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; + field bits<48> SoftFail = 0; bits<4> R1; bits<20> XBD2; @@ -229,6 +238,7 @@ class InstRXE op, dag outs, dag ins, string asmstr, list pattern> class InstRXF op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; + field bits<48> SoftFail = 0; bits<4> R1; bits<4> R3; @@ -247,6 +257,7 @@ class InstRXF op, dag outs, dag ins, string asmstr, list pattern> class InstRXY op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; + field bits<48> SoftFail = 0; bits<4> R1; bits<28> XBD2; @@ -263,6 +274,7 @@ class InstRXY op, dag outs, dag ins, string asmstr, list pattern> class InstRS op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; + field bits<32> SoftFail = 0; bits<4> R1; bits<4> R3; @@ -277,6 +289,7 @@ class InstRS op, dag outs, dag ins, string asmstr, list pattern> class InstRSY op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; + field bits<48> SoftFail = 0; bits<4> R1; bits<4> R3; @@ -294,6 +307,7 @@ class InstRSY op, dag outs, dag ins, string asmstr, list pattern> class InstSI op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; + field bits<32> SoftFail = 0; bits<16> BD1; bits<8> I2; @@ -306,6 +320,7 @@ class InstSI op, dag outs, dag ins, string asmstr, list pattern> class InstSIL op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; + field bits<48> SoftFail = 0; bits<16> BD1; bits<16> I2; @@ -318,6 +333,7 @@ class InstSIL op, dag outs, dag ins, string asmstr, list pattern> class InstSIY op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; + field bits<48> SoftFail = 0; bits<24> BD1; bits<8> I2; diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td index 770b7f5eec..66d9c5fceb 100644 --- a/lib/Target/SystemZ/SystemZOperands.td +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -24,6 +24,7 @@ class ImmediateAsmOperand class Immediate : PatLeaf<(vt imm), pred, xform>, Operand { let PrintMethod = "print"##asmop##"Operand"; + let DecoderMethod = "decode"##asmop##"Operand"; let ParserMatchClass = !cast(asmop); } @@ -37,6 +38,7 @@ class PCRelAsmOperand : ImmediateAsmOperand<"PCRel"##size> { // Constructs an operand for a PC-relative address with address type VT. // ASMOP is the associated asm operand. class PCRelOperand : Operand { + let PrintMethod = "printPCRelOperand"; let ParserMatchClass = asmop; } @@ -59,8 +61,9 @@ class AddressAsmOperand } // Constructs both a DAG pattern and instruction operand for an addressing mode. -// The mode is selected by custom code in select() -// and encoded by custom code in getEncoding(). +// The mode is selected by custom code in select(), +// encoded by custom code in getEncoding() and decoded +// by custom code in decodeDispOperand(). // The address registers have BITSIZE bits and displacements have // DISPSIZE bits. NUMOPS is the number of operands that make up an // address and OPERANDS lists the types of those operands using (ops ...). @@ -74,6 +77,7 @@ class AddressingMode("i"##bitsize)> { let PrintMethod = "print"##format##"Operand"; let EncoderMethod = "get"##format##dispsize##"Encoding"; + let DecoderMethod = "decode"##format##bitsize##"Disp"##dispsize##"Operand"; let MIOperandInfo = operands; let ParserMatchClass = !cast(format##bitsize##"Disp"##dispsize); @@ -359,15 +363,18 @@ def PCRel32 : PCRelAsmOperand<"32">; // and multiplied by 2. def brtarget16 : PCRelOperand { let EncoderMethod = "getPC16DBLEncoding"; + let DecoderMethod = "decodePC16DBLOperand"; } def brtarget32 : PCRelOperand { let EncoderMethod = "getPC32DBLEncoding"; + let DecoderMethod = "decodePC32DBLOperand"; } // A PC-relative offset of a global value. The offset is sign-extended // and multiplied by 2. def pcrel32 : PCRelAddress { let EncoderMethod = "getPC32DBLEncoding"; + let DecoderMethod = "decodePC32DBLOperand"; } // A PC-relative offset of a global value when the value is used as a @@ -375,10 +382,12 @@ def pcrel32 : PCRelAddress { def pcrel16call : PCRelAddress { let PrintMethod = "printCallOperand"; let EncoderMethod = "getPLT16DBLEncoding"; + let DecoderMethod = "decodePC16DBLOperand"; } def pcrel32call : PCRelAddress { let PrintMethod = "printCallOperand"; let EncoderMethod = "getPLT32DBLEncoding"; + let DecoderMethod = "decodePC32DBLOperand"; } //===----------------------------------------------------------------------===// diff --git a/test/MC/Disassembler/SystemZ/insn-a.txt b/test/MC/Disassembler/SystemZ/insn-a.txt new file mode 100644 index 0000000000..5ce2021bbb --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-a.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: a %r0, 0 +0x5a 0x00 0x00 0x00 + +# CHECK: a %r0, 4095 +0x5a 0x00 0x0f 0xff + +# CHECK: a %r0, 0(%r1) +0x5a 0x00 0x10 0x00 + +# CHECK: a %r0, 0(%r15) +0x5a 0x00 0xf0 0x00 + +# CHECK: a %r0, 4095(%r1,%r15) +0x5a 0x01 0xff 0xff + +# CHECK: a %r0, 4095(%r15,%r1) +0x5a 0x0f 0x1f 0xff + +# CHECK: a %r15, 0 +0x5a 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-adb.txt b/test/MC/Disassembler/SystemZ/insn-adb.txt new file mode 100644 index 0000000000..3cdf6ef21d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-adb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: adb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x1a + +# CHECK: adb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x1a + +# CHECK: adb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x1a + +# CHECK: adb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x1a + +# CHECK: adb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x1a + +# CHECK: adb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x1a + +# CHECK: adb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x1a diff --git a/test/MC/Disassembler/SystemZ/insn-adbr.txt b/test/MC/Disassembler/SystemZ/insn-adbr.txt new file mode 100644 index 0000000000..6c5f18b138 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-adbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: adbr %f0, %f0 +0xb3 0x1a 0x00 0x00 + +# CHECK: adbr %f0, %f15 +0xb3 0x1a 0x00 0x0f + +# CHECK: adbr %f7, %f8 +0xb3 0x1a 0x00 0x78 + +# CHECK: adbr %f15, %f0 +0xb3 0x1a 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-aeb.txt b/test/MC/Disassembler/SystemZ/insn-aeb.txt new file mode 100644 index 0000000000..5d28f89835 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-aeb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: aeb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x0a + +# CHECK: aeb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x0a + +# CHECK: aeb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x0a + +# CHECK: aeb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x0a + +# CHECK: aeb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x0a + +# CHECK: aeb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x0a + +# CHECK: aeb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x0a diff --git a/test/MC/Disassembler/SystemZ/insn-aebr.txt b/test/MC/Disassembler/SystemZ/insn-aebr.txt new file mode 100644 index 0000000000..e4d00f700d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-aebr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: aebr %f0, %f0 +0xb3 0x0a 0x00 0x00 + +# CHECK: aebr %f0, %f15 +0xb3 0x0a 0x00 0x0f + +# CHECK: aebr %f7, %f8 +0xb3 0x0a 0x00 0x78 + +# CHECK: aebr %f15, %f0 +0xb3 0x0a 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-afi.txt b/test/MC/Disassembler/SystemZ/insn-afi.txt new file mode 100644 index 0000000000..c679a0d205 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-afi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: afi %r0, -2147483648 +0xc2 0x09 0x80 0x00 0x00 0x00 + +# CHECK: afi %r0, -1 +0xc2 0x09 0xff 0xff 0xff 0xff + +# CHECK: afi %r0, 0 +0xc2 0x09 0x00 0x00 0x00 0x00 + +# CHECK: afi %r0, 1 +0xc2 0x09 0x00 0x00 0x00 0x01 + +# CHECK: afi %r0, 2147483647 +0xc2 0x09 0x7f 0xff 0xff 0xff + +# CHECK: afi %r15, 0 +0xc2 0xf9 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-ag.txt b/test/MC/Disassembler/SystemZ/insn-ag.txt new file mode 100644 index 0000000000..62242fb365 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ag.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ag %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x08 + +# CHECK: ag %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x08 + +# CHECK: ag %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x08 + +# CHECK: ag %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x08 + +# CHECK: ag %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x08 + +# CHECK: ag %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x08 + +# CHECK: ag %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x08 + +# CHECK: ag %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x08 + +# CHECK: ag %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x08 + +# CHECK: ag %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x08 diff --git a/test/MC/Disassembler/SystemZ/insn-agf.txt b/test/MC/Disassembler/SystemZ/insn-agf.txt new file mode 100644 index 0000000000..95eb31351e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-agf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: agf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x18 + +# CHECK: agf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x18 + +# CHECK: agf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x18 + +# CHECK: agf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x18 + +# CHECK: agf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x18 + +# CHECK: agf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x18 + +# CHECK: agf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x18 + +# CHECK: agf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x18 + +# CHECK: agf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x18 + +# CHECK: agf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x18 diff --git a/test/MC/Disassembler/SystemZ/insn-agfi.txt b/test/MC/Disassembler/SystemZ/insn-agfi.txt new file mode 100644 index 0000000000..3ff21b4e81 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-agfi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: agfi %r0, -2147483648 +0xc2 0x08 0x80 0x00 0x00 0x00 + +# CHECK: agfi %r0, -1 +0xc2 0x08 0xff 0xff 0xff 0xff + +# CHECK: agfi %r0, 0 +0xc2 0x08 0x00 0x00 0x00 0x00 + +# CHECK: agfi %r0, 1 +0xc2 0x08 0x00 0x00 0x00 0x01 + +# CHECK: agfi %r0, 2147483647 +0xc2 0x08 0x7f 0xff 0xff 0xff + +# CHECK: agfi %r15, 0 +0xc2 0xf8 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-agfr.txt b/test/MC/Disassembler/SystemZ/insn-agfr.txt new file mode 100644 index 0000000000..13e40cda4d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-agfr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: agfr %r0, %r0 +0xb9 0x18 0x00 0x00 + +# CHECK: agfr %r0, %r15 +0xb9 0x18 0x00 0x0f + +# CHECK: agfr %r15, %r0 +0xb9 0x18 0x00 0xf0 + +# CHECK: agfr %r7, %r8 +0xb9 0x18 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-aghi.txt b/test/MC/Disassembler/SystemZ/insn-aghi.txt new file mode 100644 index 0000000000..d7fe2726be --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-aghi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: aghi %r0, -32768 +0xa7 0x0b 0x80 0x00 + +# CHECK: aghi %r0, -1 +0xa7 0x0b 0xff 0xff + +# CHECK: aghi %r0, 0 +0xa7 0x0b 0x00 0x00 + +# CHECK: aghi %r0, 1 +0xa7 0x0b 0x00 0x01 + +# CHECK: aghi %r0, 32767 +0xa7 0x0b 0x7f 0xff + +# CHECK: aghi %r15, 0 +0xa7 0xfb 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-agr.txt b/test/MC/Disassembler/SystemZ/insn-agr.txt new file mode 100644 index 0000000000..4061f3a303 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-agr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: agr %r0, %r0 +0xb9 0x08 0x00 0x00 + +# CHECK: agr %r0, %r15 +0xb9 0x08 0x00 0x0f + +# CHECK: agr %r15, %r0 +0xb9 0x08 0x00 0xf0 + +# CHECK: agr %r7, %r8 +0xb9 0x08 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-agsi.txt b/test/MC/Disassembler/SystemZ/insn-agsi.txt new file mode 100644 index 0000000000..448306f42e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-agsi.txt @@ -0,0 +1,39 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: agsi -524288, 0 +0xeb 0x00 0x00 0x00 0x80 0x7a + +# CHECK: agsi -1, 0 +0xeb 0x00 0x0f 0xff 0xff 0x7a + +# CHECK: agsi 0, 0 +0xeb 0x00 0x00 0x00 0x00 0x7a + +# CHECK: agsi 1, 0 +0xeb 0x00 0x00 0x01 0x00 0x7a + +# CHECK: agsi 524287, 0 +0xeb 0x00 0x0f 0xff 0x7f 0x7a + +# CHECK: agsi 0, -128 +0xeb 0x80 0x00 0x00 0x00 0x7a + +# CHECK: agsi 0, -1 +0xeb 0xff 0x00 0x00 0x00 0x7a + +# CHECK: agsi 0, 1 +0xeb 0x01 0x00 0x00 0x00 0x7a + +# CHECK: agsi 0, 127 +0xeb 0x7f 0x00 0x00 0x00 0x7a + +# CHECK: agsi 0(%r1), 42 +0xeb 0x2a 0x10 0x00 0x00 0x7a + +# CHECK: agsi 0(%r15), 42 +0xeb 0x2a 0xf0 0x00 0x00 0x7a + +# CHECK: agsi 524287(%r1), 42 +0xeb 0x2a 0x1f 0xff 0x7f 0x7a + +# CHECK: agsi 524287(%r15), 42 +0xeb 0x2a 0xff 0xff 0x7f 0x7a diff --git a/test/MC/Disassembler/SystemZ/insn-ah.txt b/test/MC/Disassembler/SystemZ/insn-ah.txt new file mode 100644 index 0000000000..c05d17790a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ah.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ah %r0, 0 +0x4a 0x00 0x00 0x00 + +# CHECK: ah %r0, 4095 +0x4a 0x00 0x0f 0xff + +# CHECK: ah %r0, 0(%r1) +0x4a 0x00 0x10 0x00 + +# CHECK: ah %r0, 0(%r15) +0x4a 0x00 0xf0 0x00 + +# CHECK: ah %r0, 4095(%r1,%r15) +0x4a 0x01 0xff 0xff + +# CHECK: ah %r0, 4095(%r15,%r1) +0x4a 0x0f 0x1f 0xff + +# CHECK: ah %r15, 0 +0x4a 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-ahi.txt b/test/MC/Disassembler/SystemZ/insn-ahi.txt new file mode 100644 index 0000000000..fb16c7232b --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ahi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ahi %r0, -32768 +0xa7 0x0a 0x80 0x00 + +# CHECK: ahi %r0, -1 +0xa7 0x0a 0xff 0xff + +# CHECK: ahi %r0, 0 +0xa7 0x0a 0x00 0x00 + +# CHECK: ahi %r0, 1 +0xa7 0x0a 0x00 0x01 + +# CHECK: ahi %r0, 32767 +0xa7 0x0a 0x7f 0xff + +# CHECK: ahi %r15, 0 +0xa7 0xfa 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-ahy.txt b/test/MC/Disassembler/SystemZ/insn-ahy.txt new file mode 100644 index 0000000000..511c01b4f8 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ahy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ahy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x7a + +# CHECK: ahy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x7a + +# CHECK: ahy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x7a + +# CHECK: ahy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x7a + +# CHECK: ahy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x7a + +# CHECK: ahy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x7a + +# CHECK: ahy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x7a + +# CHECK: ahy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x7a + +# CHECK: ahy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x7a + +# CHECK: ahy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x7a diff --git a/test/MC/Disassembler/SystemZ/insn-al.txt b/test/MC/Disassembler/SystemZ/insn-al.txt new file mode 100644 index 0000000000..18f4e6f994 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-al.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: al %r0, 0 +0x5e 0x00 0x00 0x00 + +# CHECK: al %r0, 4095 +0x5e 0x00 0x0f 0xff + +# CHECK: al %r0, 0(%r1) +0x5e 0x00 0x10 0x00 + +# CHECK: al %r0, 0(%r15) +0x5e 0x00 0xf0 0x00 + +# CHECK: al %r0, 4095(%r1,%r15) +0x5e 0x01 0xff 0xff + +# CHECK: al %r0, 4095(%r15,%r1) +0x5e 0x0f 0x1f 0xff + +# CHECK: al %r15, 0 +0x5e 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-alc.txt b/test/MC/Disassembler/SystemZ/insn-alc.txt new file mode 100644 index 0000000000..de1ee015bf --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-alc.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: alc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x98 + +# CHECK: alc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x98 + +# CHECK: alc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x98 + +# CHECK: alc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x98 + +# CHECK: alc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x98 + +# CHECK: alc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x98 + +# CHECK: alc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x98 + +# CHECK: alc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x98 + +# CHECK: alc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x98 + +# CHECK: alc %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x98 diff --git a/test/MC/Disassembler/SystemZ/insn-alcg.txt b/test/MC/Disassembler/SystemZ/insn-alcg.txt new file mode 100644 index 0000000000..db450f7dba --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-alcg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: alcg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x88 + +# CHECK: alcg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x88 + +# CHECK: alcg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x88 + +# CHECK: alcg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x88 + +# CHECK: alcg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x88 + +# CHECK: alcg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x88 + +# CHECK: alcg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x88 + +# CHECK: alcg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x88 + +# CHECK: alcg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x88 + +# CHECK: alcg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x88 diff --git a/test/MC/Disassembler/SystemZ/insn-alcgr.txt b/test/MC/Disassembler/SystemZ/insn-alcgr.txt new file mode 100644 index 0000000000..5a7db13548 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-alcgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: alcgr %r0, %r0 +0xb9 0x88 0x00 0x00 + +# CHECK: alcgr %r0, %r15 +0xb9 0x88 0x00 0x0f + +# CHECK: alcgr %r15, %r0 +0xb9 0x88 0x00 0xf0 + +# CHECK: alcgr %r7, %r8 +0xb9 0x88 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-alcr.txt b/test/MC/Disassembler/SystemZ/insn-alcr.txt new file mode 100644 index 0000000000..3f108797d7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-alcr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: alcr %r0, %r0 +0xb9 0x98 0x00 0x00 + +# CHECK: alcr %r0, %r15 +0xb9 0x98 0x00 0x0f + +# CHECK: alcr %r15, %r0 +0xb9 0x98 0x00 0xf0 + +# CHECK: alcr %r7, %r8 +0xb9 0x98 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-alfi.txt b/test/MC/Disassembler/SystemZ/insn-alfi.txt new file mode 100644 index 0000000000..29aec98635 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-alfi.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: alfi %r0, 0 +0xc2 0x0b 0x00 0x00 0x00 0x00 + +# CHECK: alfi %r0, 4294967295 +0xc2 0x0b 0xff 0xff 0xff 0xff + +# CHECK: alfi %r15, 0 +0xc2 0xfb 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-alg.txt b/test/MC/Disassembler/SystemZ/insn-alg.txt new file mode 100644 index 0000000000..e02e892429 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-alg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: alg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x0a + +# CHECK: alg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x0a + +# CHECK: alg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x0a + +# CHECK: alg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x0a + +# CHECK: alg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x0a + +# CHECK: alg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x0a + +# CHECK: alg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x0a + +# CHECK: alg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x0a + +# CHECK: alg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x0a + +# CHECK: alg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x0a diff --git a/test/MC/Disassembler/SystemZ/insn-algf.txt b/test/MC/Disassembler/SystemZ/insn-algf.txt new file mode 100644 index 0000000000..748df29ca5 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-algf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: algf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x1a + +# CHECK: algf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x1a + +# CHECK: algf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x1a + +# CHECK: algf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x1a + +# CHECK: algf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x1a + +# CHECK: algf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x1a + +# CHECK: algf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x1a + +# CHECK: algf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x1a + +# CHECK: algf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x1a + +# CHECK: algf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x1a diff --git a/test/MC/Disassembler/SystemZ/insn-algfi.txt b/test/MC/Disassembler/SystemZ/insn-algfi.txt new file mode 100644 index 0000000000..0a1d2f2e2e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-algfi.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: algfi %r0, 0 +0xc2 0x0a 0x00 0x00 0x00 0x00 + +# CHECK: algfi %r0, 4294967295 +0xc2 0x0a 0xff 0xff 0xff 0xff + +# CHECK: algfi %r15, 0 +0xc2 0xfa 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-algfr.txt b/test/MC/Disassembler/SystemZ/insn-algfr.txt new file mode 100644 index 0000000000..47cddbe13b --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-algfr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: algfr %r0, %r0 +0xb9 0x1a 0x00 0x00 + +# CHECK: algfr %r0, %r15 +0xb9 0x1a 0x00 0x0f + +# CHECK: algfr %r15, %r0 +0xb9 0x1a 0x00 0xf0 + +# CHECK: algfr %r7, %r8 +0xb9 0x1a 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-algr.txt b/test/MC/Disassembler/SystemZ/insn-algr.txt new file mode 100644 index 0000000000..b5847d2d59 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-algr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: algr %r0, %r0 +0xb9 0x0a 0x00 0x00 + +# CHECK: algr %r0, %r15 +0xb9 0x0a 0x00 0x0f + +# CHECK: algr %r15, %r0 +0xb9 0x0a 0x00 0xf0 + +# CHECK: algr %r7, %r8 +0xb9 0x0a 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-alr.txt b/test/MC/Disassembler/SystemZ/insn-alr.txt new file mode 100644 index 0000000000..7b46ce3283 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-alr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: alr %r0, %r0 +0x1e 0x00 + +# CHECK: alr %r0, %r15 +0x1e 0x0f + +# CHECK: alr %r15, %r0 +0x1e 0xf0 + +# CHECK: alr %r7, %r8 +0x1e 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-aly.txt b/test/MC/Disassembler/SystemZ/insn-aly.txt new file mode 100644 index 0000000000..4ef5cc2614 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-aly.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: aly %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x5e + +# CHECK: aly %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x5e + +# CHECK: aly %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x5e + +# CHECK: aly %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x5e + +# CHECK: aly %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x5e + +# CHECK: aly %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x5e + +# CHECK: aly %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x5e + +# CHECK: aly %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x5e + +# CHECK: aly %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x5e + +# CHECK: aly %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x5e diff --git a/test/MC/Disassembler/SystemZ/insn-ar.txt b/test/MC/Disassembler/SystemZ/insn-ar.txt new file mode 100644 index 0000000000..9443590e09 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ar.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ar %r0, %r0 +0x1a 0x00 + +# CHECK: ar %r0, %r15 +0x1a 0x0f + +# CHECK: ar %r15, %r0 +0x1a 0xf0 + +# CHECK: ar %r7, %r8 +0x1a 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-asi.txt b/test/MC/Disassembler/SystemZ/insn-asi.txt new file mode 100644 index 0000000000..af9b7a6144 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-asi.txt @@ -0,0 +1,39 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: asi -524288, 0 +0xeb 0x00 0x00 0x00 0x80 0x6a + +# CHECK: asi -1, 0 +0xeb 0x00 0x0f 0xff 0xff 0x6a + +# CHECK: asi 0, 0 +0xeb 0x00 0x00 0x00 0x00 0x6a + +# CHECK: asi 1, 0 +0xeb 0x00 0x00 0x01 0x00 0x6a + +# CHECK: asi 524287, 0 +0xeb 0x00 0x0f 0xff 0x7f 0x6a + +# CHECK: asi 0, -128 +0xeb 0x80 0x00 0x00 0x00 0x6a + +# CHECK: asi 0, -1 +0xeb 0xff 0x00 0x00 0x00 0x6a + +# CHECK: asi 0, 1 +0xeb 0x01 0x00 0x00 0x00 0x6a + +# CHECK: asi 0, 127 +0xeb 0x7f 0x00 0x00 0x00 0x6a + +# CHECK: asi 0(%r1), 42 +0xeb 0x2a 0x10 0x00 0x00 0x6a + +# CHECK: asi 0(%r15), 42 +0xeb 0x2a 0xf0 0x00 0x00 0x6a + +# CHECK: asi 524287(%r1), 42 +0xeb 0x2a 0x1f 0xff 0x7f 0x6a + +# CHECK: asi 524287(%r15), 42 +0xeb 0x2a 0xff 0xff 0x7f 0x6a diff --git a/test/MC/Disassembler/SystemZ/insn-axbr.txt b/test/MC/Disassembler/SystemZ/insn-axbr.txt new file mode 100644 index 0000000000..e78ff8e404 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-axbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: axbr %f0, %f0 +0xb3 0x4a 0x00 0x00 + +# CHECK: axbr %f0, %f13 +0xb3 0x4a 0x00 0x0d + +# CHECK: axbr %f8, %f8 +0xb3 0x4a 0x00 0x88 + +# CHECK: axbr %f13, %f0 +0xb3 0x4a 0x00 0xd0 diff --git a/test/MC/Disassembler/SystemZ/insn-ay.txt b/test/MC/Disassembler/SystemZ/insn-ay.txt new file mode 100644 index 0000000000..bd81f8cafe --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ay.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ay %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x5a + +# CHECK: ay %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x5a + +# CHECK: ay %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x5a + +# CHECK: ay %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x5a + +# CHECK: ay %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x5a + +# CHECK: ay %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x5a + +# CHECK: ay %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x5a + +# CHECK: ay %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x5a + +# CHECK: ay %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x5a + +# CHECK: ay %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x5a diff --git a/test/MC/Disassembler/SystemZ/insn-basr.txt b/test/MC/Disassembler/SystemZ/insn-basr.txt new file mode 100644 index 0000000000..6540bf4b25 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-basr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: basr %r0, %r1 +0x0d 0x01 + +# CHECK: basr %r0, %r15 +0x0d 0x0f + +# CHECK: basr %r14, %r9 +0x0d 0xe9 + +# CHECK: basr %r15, %r1 +0x0d 0xf1 diff --git a/test/MC/Disassembler/SystemZ/insn-br.txt b/test/MC/Disassembler/SystemZ/insn-br.txt new file mode 100644 index 0000000000..7643a0e8fe --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-br.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: br %r1 +0x07 0xf1 + +# CHECK: br %r14 +0x07 0xfe + +# CHECK: br %r15 +0x07 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-bras.txt b/test/MC/Disassembler/SystemZ/insn-bras.txt new file mode 100644 index 0000000000..c02f1d010a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-bras.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: bras %r0, 0x0 +0xa7 0x05 0x00 0x00 + +# CHECK: bras %r14, 0x4 +0xa7 0xe5 0x00 0x00 + +# CHECK: bras %r15, 0x8 +0xa7 0xf5 0x00 0x00 + +# CHECK: bras %r0, 0xa +0xa7 0x05 0xff 0xff + +# CHECK: bras %r14, 0xffffffffffff0010 +0xa7 0xe5 0x80 0x00 + +# CHECK: bras %r15, 0x10012 +0xa7 0xf5 0x7f 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-brasl.txt b/test/MC/Disassembler/SystemZ/insn-brasl.txt new file mode 100644 index 0000000000..73718d051c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-brasl.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: brasl %r0, 0x0 +0xc0 0x05 0x00 0x00 0x00 0x00 + +# CHECK: brasl %r14, 0x6 +0xc0 0xe5 0x00 0x00 0x00 0x00 + +# CHECK: brasl %r15, 0xc +0xc0 0xf5 0x00 0x00 0x00 0x00 + +# CHECK: brasl %r0, 0x10 +0xc0 0x05 0xff 0xff 0xff 0xff + +# CHECK: brasl %r14, 0xffffffff00000018 +0xc0 0xe5 0x80 0x00 0x00 0x00 + +# CHECK: brasl %r15, 0x10000001c +0xc0 0xf5 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-brc.txt b/test/MC/Disassembler/SystemZ/insn-brc.txt new file mode 100644 index 0000000000..c23e878b17 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-brc.txt @@ -0,0 +1,66 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: brc 0, 0x0 +0xa7 0x04 0x00 0x00 + +# CHECK: jo 0x4 +0xa7 0x14 0x00 0x00 + +# CHECK: jh 0x8 +0xa7 0x24 0x00 0x00 + +# CHECK: jnle 0xc +0xa7 0x34 0x00 0x00 + +# CHECK: jl 0x10 +0xa7 0x44 0x00 0x00 + +# CHECK: jnhe 0x14 +0xa7 0x54 0x00 0x00 + +# CHECK: jlh 0x18 +0xa7 0x64 0x00 0x00 + +# CHECK: jne 0x1c +0xa7 0x74 0x00 0x00 + +# CHECK: je 0x20 +0xa7 0x84 0x00 0x00 + +# CHECK: jnlh 0x24 +0xa7 0x94 0x00 0x00 + +# CHECK: jhe 0x28 +0xa7 0xa4 0x00 0x00 + +# CHECK: jnl 0x2c +0xa7 0xb4 0x00 0x00 + +# CHECK: jle 0x30 +0xa7 0xc4 0x00 0x00 + +# CHECK: jnh 0x34 +0xa7 0xd4 0x00 0x00 + +# CHECK: jno 0x38 +0xa7 0xe4 0x00 0x00 + +# CHECK: j 0x3c +0xa7 0xf4 0x00 0x00 + +# CHECK: brc 0, 0x3e +0xa7 0x04 0xff 0xff + +# CHECK: brc 0, 0xffffffffffff0044 +0xa7 0x04 0x80 0x00 + +# CHECK: brc 0, 0x10046 +0xa7 0x04 0x7f 0xff + +# CHECK: j 0x4a +0xa7 0xf4 0xff 0xff + +# CHECK: j 0xffffffffffff0050 +0xa7 0xf4 0x80 0x00 + +# CHECK: j 0x10052 +0xa7 0xf4 0x7f 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-brcl.txt b/test/MC/Disassembler/SystemZ/insn-brcl.txt new file mode 100644 index 0000000000..e3a6cb01e9 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-brcl.txt @@ -0,0 +1,66 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: brcl 0, 0x0 +0xc0 0x04 0x00 0x00 0x00 0x00 + +# CHECK: jgo 0x6 +0xc0 0x14 0x00 0x00 0x00 0x00 + +# CHECK: jgh 0xc +0xc0 0x24 0x00 0x00 0x00 0x00 + +# CHECK: jgnle 0x12 +0xc0 0x34 0x00 0x00 0x00 0x00 + +# CHECK: jgl 0x18 +0xc0 0x44 0x00 0x00 0x00 0x00 + +# CHECK: jgnhe 0x1e +0xc0 0x54 0x00 0x00 0x00 0x00 + +# CHECK: jglh 0x24 +0xc0 0x64 0x00 0x00 0x00 0x00 + +# CHECK: jgne 0x2a +0xc0 0x74 0x00 0x00 0x00 0x00 + +# CHECK: jge 0x30 +0xc0 0x84 0x00 0x00 0x00 0x00 + +# CHECK: jgnlh 0x36 +0xc0 0x94 0x00 0x00 0x00 0x00 + +# CHECK: jghe 0x3c +0xc0 0xa4 0x00 0x00 0x00 0x00 + +# CHECK: jgnl 0x42 +0xc0 0xb4 0x00 0x00 0x00 0x00 + +# CHECK: jgle 0x48 +0xc0 0xc4 0x00 0x00 0x00 0x00 + +# CHECK: jgnh 0x4e +0xc0 0xd4 0x00 0x00 0x00 0x00 + +# CHECK: jgno 0x54 +0xc0 0xe4 0x00 0x00 0x00 0x00 + +# CHECK: jg 0x5a +0xc0 0xf4 0x00 0x00 0x00 0x00 + +# CHECK: brcl 0, 0x5e +0xc0 0x04 0xff 0xff 0xff 0xff + +# CHECK: brcl 0, 0xffffffff00000066 +0xc0 0x04 0x80 0x00 0x00 0x00 + +# CHECK: brcl 0, 0x10000006a +0xc0 0x04 0x7f 0xff 0xff 0xff + +# CHECK: jg 0x70 +0xc0 0xf4 0xff 0xff 0xff 0xff + +# CHECK: jg 0xffffffff00000078 +0xc0 0xf4 0x80 0x00 0x00 0x00 + +# CHECK: jg 0x10000007c +0xc0 0xf4 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-c.txt b/test/MC/Disassembler/SystemZ/insn-c.txt new file mode 100644 index 0000000000..1dbd6366ab --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-c.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: c %r0, 0 +0x59 0x00 0x00 0x00 + +# CHECK: c %r0, 4095 +0x59 0x00 0x0f 0xff + +# CHECK: c %r0, 0(%r1) +0x59 0x00 0x10 0x00 + +# CHECK: c %r0, 0(%r15) +0x59 0x00 0xf0 0x00 + +# CHECK: c %r0, 4095(%r1,%r15) +0x59 0x01 0xff 0xff + +# CHECK: c %r0, 4095(%r15,%r1) +0x59 0x0f 0x1f 0xff + +# CHECK: c %r15, 0 +0x59 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-cdb.txt b/test/MC/Disassembler/SystemZ/insn-cdb.txt new file mode 100644 index 0000000000..fcccf34a6a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cdb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cdb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x19 + +# CHECK: cdb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x19 + +# CHECK: cdb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x19 + +# CHECK: cdb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x19 + +# CHECK: cdb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x19 + +# CHECK: cdb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x19 + +# CHECK: cdb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x19 diff --git a/test/MC/Disassembler/SystemZ/insn-cdbr.txt b/test/MC/Disassembler/SystemZ/insn-cdbr.txt new file mode 100644 index 0000000000..579c6f73f1 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cdbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cdbr %f0, %f0 +0xb3 0x19 0x00 0x00 + +# CHECK: cdbr %f0, %f15 +0xb3 0x19 0x00 0x0f + +# CHECK: cdbr %f7, %f8 +0xb3 0x19 0x00 0x78 + +# CHECK: cdbr %f15, %f0 +0xb3 0x19 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-cdfbr.txt b/test/MC/Disassembler/SystemZ/insn-cdfbr.txt new file mode 100644 index 0000000000..04004ed6e3 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cdfbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cdfbr %f0, %r0 +0xb3 0x95 0x00 0x00 + +# CHECK: cdfbr %f0, %r15 +0xb3 0x95 0x00 0x0f + +# CHECK: cdfbr %f15, %r0 +0xb3 0x95 0x00 0xf0 + +# CHECK: cdfbr %f7, %r8 +0xb3 0x95 0x00 0x78 + +# CHECK: cdfbr %f15, %r15 +0xb3 0x95 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cdgbr.txt b/test/MC/Disassembler/SystemZ/insn-cdgbr.txt new file mode 100644 index 0000000000..8105eb2f99 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cdgbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cdgbr %f0, %r0 +0xb3 0xa5 0x00 0x00 + +# CHECK: cdgbr %f0, %r15 +0xb3 0xa5 0x00 0x0f + +# CHECK: cdgbr %f15, %r0 +0xb3 0xa5 0x00 0xf0 + +# CHECK: cdgbr %f7, %r8 +0xb3 0xa5 0x00 0x78 + +# CHECK: cdgbr %f15, %r15 +0xb3 0xa5 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-ceb.txt b/test/MC/Disassembler/SystemZ/insn-ceb.txt new file mode 100644 index 0000000000..51424e8319 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ceb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ceb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x09 + +# CHECK: ceb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x09 + +# CHECK: ceb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x09 + +# CHECK: ceb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x09 + +# CHECK: ceb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x09 + +# CHECK: ceb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x09 + +# CHECK: ceb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x09 diff --git a/test/MC/Disassembler/SystemZ/insn-cebr.txt b/test/MC/Disassembler/SystemZ/insn-cebr.txt new file mode 100644 index 0000000000..7d2e380fcd --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cebr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cebr %f0, %f0 +0xb3 0x09 0x00 0x00 + +# CHECK: cebr %f0, %f15 +0xb3 0x09 0x00 0x0f + +# CHECK: cebr %f7, %f8 +0xb3 0x09 0x00 0x78 + +# CHECK: cebr %f15, %f0 +0xb3 0x09 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-cefbr.txt b/test/MC/Disassembler/SystemZ/insn-cefbr.txt new file mode 100644 index 0000000000..edc1aa9a17 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cefbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cefbr %f0, %r0 +0xb3 0x94 0x00 0x00 + +# CHECK: cefbr %f0, %r15 +0xb3 0x94 0x00 0x0f + +# CHECK: cefbr %f15, %r0 +0xb3 0x94 0x00 0xf0 + +# CHECK: cefbr %f7, %r8 +0xb3 0x94 0x00 0x78 + +# CHECK: cefbr %f15, %r15 +0xb3 0x94 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cegbr.txt b/test/MC/Disassembler/SystemZ/insn-cegbr.txt new file mode 100644 index 0000000000..4cd4b5b6b6 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cegbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cegbr %f0, %r0 +0xb3 0xa4 0x00 0x00 + +# CHECK: cegbr %f0, %r15 +0xb3 0xa4 0x00 0x0f + +# CHECK: cegbr %f15, %r0 +0xb3 0xa4 0x00 0xf0 + +# CHECK: cegbr %f7, %r8 +0xb3 0xa4 0x00 0x78 + +# CHECK: cegbr %f15, %r15 +0xb3 0xa4 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cfdbr.txt b/test/MC/Disassembler/SystemZ/insn-cfdbr.txt new file mode 100644 index 0000000000..feceb689ed --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cfdbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cfdbr %r0, 0, %f0 +0xb3 0x99 0x00 0x00 + +# CHECK: cfdbr %r0, 0, %f15 +0xb3 0x99 0x00 0x0f + +# CHECK: cfdbr %r0, 15, %f0 +0xb3 0x99 0xf0 0x00 + +# CHECK: cfdbr %r4, 5, %f6 +0xb3 0x99 0x50 0x46 + +# CHECK: cfdbr %r15, 0, %f0 +0xb3 0x99 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-cfebr.txt b/test/MC/Disassembler/SystemZ/insn-cfebr.txt new file mode 100644 index 0000000000..07f7ad2d42 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cfebr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cfebr %r0, 0, %f0 +0xb3 0x98 0x00 0x00 + +# CHECK: cfebr %r0, 0, %f15 +0xb3 0x98 0x00 0x0f + +# CHECK: cfebr %r0, 15, %f0 +0xb3 0x98 0xf0 0x00 + +# CHECK: cfebr %r4, 5, %f6 +0xb3 0x98 0x50 0x46 + +# CHECK: cfebr %r15, 0, %f0 +0xb3 0x98 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-cfi.txt b/test/MC/Disassembler/SystemZ/insn-cfi.txt new file mode 100644 index 0000000000..ffc38b5946 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cfi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cfi %r0, -2147483648 +0xc2 0x0d 0x80 0x00 0x00 0x00 + +# CHECK: cfi %r0, -1 +0xc2 0x0d 0xff 0xff 0xff 0xff + +# CHECK: cfi %r0, 0 +0xc2 0x0d 0x00 0x00 0x00 0x00 + +# CHECK: cfi %r0, 1 +0xc2 0x0d 0x00 0x00 0x00 0x01 + +# CHECK: cfi %r0, 2147483647 +0xc2 0x0d 0x7f 0xff 0xff 0xff + +# CHECK: cfi %r15, 0 +0xc2 0xfd 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-cfxbr.txt b/test/MC/Disassembler/SystemZ/insn-cfxbr.txt new file mode 100644 index 0000000000..5202f59f44 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cfxbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cfxbr %r0, 0, %f0 +0xb3 0x9a 0x00 0x00 + +# CHECK: cfxbr %r0, 0, %f13 +0xb3 0x9a 0x00 0x0d + +# CHECK: cfxbr %r0, 15, %f0 +0xb3 0x9a 0xf0 0x00 + +# CHECK: cfxbr %r4, 5, %f8 +0xb3 0x9a 0x50 0x48 + +# CHECK: cfxbr %r15, 0, %f0 +0xb3 0x9a 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-cg.txt b/test/MC/Disassembler/SystemZ/insn-cg.txt new file mode 100644 index 0000000000..f314902f17 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x20 + +# CHECK: cg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x20 + +# CHECK: cg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x20 + +# CHECK: cg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x20 + +# CHECK: cg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x20 + +# CHECK: cg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x20 + +# CHECK: cg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x20 + +# CHECK: cg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x20 + +# CHECK: cg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x20 + +# CHECK: cg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x20 diff --git a/test/MC/Disassembler/SystemZ/insn-cgdbr.txt b/test/MC/Disassembler/SystemZ/insn-cgdbr.txt new file mode 100644 index 0000000000..16a771ab27 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgdbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgdbr %r0, 0, %f0 +0xb3 0xa9 0x00 0x00 + +# CHECK: cgdbr %r0, 0, %f15 +0xb3 0xa9 0x00 0x0f + +# CHECK: cgdbr %r0, 15, %f0 +0xb3 0xa9 0xf0 0x00 + +# CHECK: cgdbr %r4, 5, %f6 +0xb3 0xa9 0x50 0x46 + +# CHECK: cgdbr %r15, 0, %f0 +0xb3 0xa9 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-cgebr.txt b/test/MC/Disassembler/SystemZ/insn-cgebr.txt new file mode 100644 index 0000000000..2f224cca36 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgebr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgebr %r0, 0, %f0 +0xb3 0xa8 0x00 0x00 + +# CHECK: cgebr %r0, 0, %f15 +0xb3 0xa8 0x00 0x0f + +# CHECK: cgebr %r0, 15, %f0 +0xb3 0xa8 0xf0 0x00 + +# CHECK: cgebr %r4, 5, %f6 +0xb3 0xa8 0x50 0x46 + +# CHECK: cgebr %r15, 0, %f0 +0xb3 0xa8 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-cgf.txt b/test/MC/Disassembler/SystemZ/insn-cgf.txt new file mode 100644 index 0000000000..cc20d978ef --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x30 + +# CHECK: cgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x30 + +# CHECK: cgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x30 + +# CHECK: cgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x30 + +# CHECK: cgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x30 + +# CHECK: cgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x30 + +# CHECK: cgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x30 + +# CHECK: cgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x30 + +# CHECK: cgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x30 + +# CHECK: cgf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x30 diff --git a/test/MC/Disassembler/SystemZ/insn-cgfi.txt b/test/MC/Disassembler/SystemZ/insn-cgfi.txt new file mode 100644 index 0000000000..05fb61231a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgfi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgfi %r0, -2147483648 +0xc2 0x0c 0x80 0x00 0x00 0x00 + +# CHECK: cgfi %r0, -1 +0xc2 0x0c 0xff 0xff 0xff 0xff + +# CHECK: cgfi %r0, 0 +0xc2 0x0c 0x00 0x00 0x00 0x00 + +# CHECK: cgfi %r0, 1 +0xc2 0x0c 0x00 0x00 0x00 0x01 + +# CHECK: cgfi %r0, 2147483647 +0xc2 0x0c 0x7f 0xff 0xff 0xff + +# CHECK: cgfi %r15, 0 +0xc2 0xfc 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-cgfr.txt b/test/MC/Disassembler/SystemZ/insn-cgfr.txt new file mode 100644 index 0000000000..272e5f8de0 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgfr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgfr %r0, %r0 +0xb9 0x30 0x00 0x00 + +# CHECK: cgfr %r0, %r15 +0xb9 0x30 0x00 0x0f + +# CHECK: cgfr %r15, %r0 +0xb9 0x30 0x00 0xf0 + +# CHECK: cgfr %r7, %r8 +0xb9 0x30 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-cgfrl.txt b/test/MC/Disassembler/SystemZ/insn-cgfrl.txt new file mode 100644 index 0000000000..5ad5c7d267 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgfrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgfrl %r0, 0x0 +0xc6 0x0c 0x00 0x00 0x00 0x00 + +# CHECK: cgfrl %r15, 0x6 +0xc6 0xfc 0x00 0x00 0x00 0x00 + +# CHECK: cgfrl %r0, 0xa +0xc6 0x0c 0xff 0xff 0xff 0xff + +# CHECK: cgfrl %r15, 0x10 +0xc6 0xfc 0xff 0xff 0xff 0xff + +# CHECK: cgfrl %r0, 0xffffffff00000018 +0xc6 0x0c 0x80 0x00 0x00 0x00 + +# CHECK: cgfrl %r15, 0xffffffff0000001e +0xc6 0xfc 0x80 0x00 0x00 0x00 + +# CHECK: cgfrl %r0, 0x100000022 +0xc6 0x0c 0x7f 0xff 0xff 0xff + +# CHECK: cgfrl %r15, 0x100000028 +0xc6 0xfc 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cgh.txt b/test/MC/Disassembler/SystemZ/insn-cgh.txt new file mode 100644 index 0000000000..2a6b74b667 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgh.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x34 + +# CHECK: cgh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x34 + +# CHECK: cgh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x34 + +# CHECK: cgh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x34 + +# CHECK: cgh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x34 + +# CHECK: cgh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x34 + +# CHECK: cgh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x34 + +# CHECK: cgh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x34 + +# CHECK: cgh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x34 + +# CHECK: cgh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x34 diff --git a/test/MC/Disassembler/SystemZ/insn-cghi.txt b/test/MC/Disassembler/SystemZ/insn-cghi.txt new file mode 100644 index 0000000000..481e469a19 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cghi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cghi %r0, -32768 +0xa7 0x0f 0x80 0x00 + +# CHECK: cghi %r0, -1 +0xa7 0x0f 0xff 0xff + +# CHECK: cghi %r0, 0 +0xa7 0x0f 0x00 0x00 + +# CHECK: cghi %r0, 1 +0xa7 0x0f 0x00 0x01 + +# CHECK: cghi %r0, 32767 +0xa7 0x0f 0x7f 0xff + +# CHECK: cghi %r15, 0 +0xa7 0xff 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-cghrl.txt b/test/MC/Disassembler/SystemZ/insn-cghrl.txt new file mode 100644 index 0000000000..1d2eac720a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cghrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cghrl %r0, 0x0 +0xc6 0x04 0x00 0x00 0x00 0x00 + +# CHECK: cghrl %r15, 0x6 +0xc6 0xf4 0x00 0x00 0x00 0x00 + +# CHECK: cghrl %r0, 0xa +0xc6 0x04 0xff 0xff 0xff 0xff + +# CHECK: cghrl %r15, 0x10 +0xc6 0xf4 0xff 0xff 0xff 0xff + +# CHECK: cghrl %r0, 0xffffffff00000018 +0xc6 0x04 0x80 0x00 0x00 0x00 + +# CHECK: cghrl %r15, 0xffffffff0000001e +0xc6 0xf4 0x80 0x00 0x00 0x00 + +# CHECK: cghrl %r0, 0x100000022 +0xc6 0x04 0x7f 0xff 0xff 0xff + +# CHECK: cghrl %r15, 0x100000028 +0xc6 0xf4 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cghsi.txt b/test/MC/Disassembler/SystemZ/insn-cghsi.txt new file mode 100644 index 0000000000..49ad3fd7eb --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cghsi.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cghsi 0, 0 +0xe5 0x58 0x00 0x00 0x00 0x00 + +# CHECK: cghsi 4095, 0 +0xe5 0x58 0x0f 0xff 0x00 0x00 + +# CHECK: cghsi 0, -32768 +0xe5 0x58 0x00 0x00 0x80 0x00 + +# CHECK: cghsi 0, -1 +0xe5 0x58 0x00 0x00 0xff 0xff + +# CHECK: cghsi 0, 0 +0xe5 0x58 0x00 0x00 0x00 0x00 + +# CHECK: cghsi 0, 1 +0xe5 0x58 0x00 0x00 0x00 0x01 + +# CHECK: cghsi 0, 32767 +0xe5 0x58 0x00 0x00 0x7f 0xff + +# CHECK: cghsi 0(%r1), 42 +0xe5 0x58 0x10 0x00 0x00 0x2a + +# CHECK: cghsi 0(%r15), 42 +0xe5 0x58 0xf0 0x00 0x00 0x2a + +# CHECK: cghsi 4095(%r1), 42 +0xe5 0x58 0x1f 0xff 0x00 0x2a + +# CHECK: cghsi 4095(%r15), 42 +0xe5 0x58 0xff 0xff 0x00 0x2a diff --git a/test/MC/Disassembler/SystemZ/insn-cgr.txt b/test/MC/Disassembler/SystemZ/insn-cgr.txt new file mode 100644 index 0000000000..75cc159fd1 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgr %r0, %r0 +0xb9 0x20 0x00 0x00 + +# CHECK: cgr %r0, %r15 +0xb9 0x20 0x00 0x0f + +# CHECK: cgr %r15, %r0 +0xb9 0x20 0x00 0xf0 + +# CHECK: cgr %r7, %r8 +0xb9 0x20 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-cgrl.txt b/test/MC/Disassembler/SystemZ/insn-cgrl.txt new file mode 100644 index 0000000000..7f4faac2a9 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgrl %r0, 0x0 +0xc6 0x08 0x00 0x00 0x00 0x00 + +# CHECK: cgrl %r15, 0x6 +0xc6 0xf8 0x00 0x00 0x00 0x00 + +# CHECK: cgrl %r0, 0xa +0xc6 0x08 0xff 0xff 0xff 0xff + +# CHECK: cgrl %r15, 0x10 +0xc6 0xf8 0xff 0xff 0xff 0xff + +# CHECK: cgrl %r0, 0xffffffff00000018 +0xc6 0x08 0x80 0x00 0x00 0x00 + +# CHECK: cgrl %r15, 0xffffffff0000001e +0xc6 0xf8 0x80 0x00 0x00 0x00 + +# CHECK: cgrl %r0, 0x100000022 +0xc6 0x08 0x7f 0xff 0xff 0xff + +# CHECK: cgrl %r15, 0x100000028 +0xc6 0xf8 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cgxbr.txt b/test/MC/Disassembler/SystemZ/insn-cgxbr.txt new file mode 100644 index 0000000000..d97a1ca984 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cgxbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cgxbr %r0, 0, %f0 +0xb3 0xaa 0x00 0x00 + +# CHECK: cgxbr %r0, 0, %f13 +0xb3 0xaa 0x00 0x0d + +# CHECK: cgxbr %r0, 15, %f0 +0xb3 0xaa 0xf0 0x00 + +# CHECK: cgxbr %r4, 5, %f8 +0xb3 0xaa 0x50 0x48 + +# CHECK: cgxbr %r15, 0, %f0 +0xb3 0xaa 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-ch.txt b/test/MC/Disassembler/SystemZ/insn-ch.txt new file mode 100644 index 0000000000..8501626563 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ch.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ch %r0, 0 +0x49 0x00 0x00 0x00 + +# CHECK: ch %r0, 4095 +0x49 0x00 0x0f 0xff + +# CHECK: ch %r0, 0(%r1) +0x49 0x00 0x10 0x00 + +# CHECK: ch %r0, 0(%r15) +0x49 0x00 0xf0 0x00 + +# CHECK: ch %r0, 4095(%r1,%r15) +0x49 0x01 0xff 0xff + +# CHECK: ch %r0, 4095(%r15,%r1) +0x49 0x0f 0x1f 0xff + +# CHECK: ch %r15, 0 +0x49 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-chhsi.txt b/test/MC/Disassembler/SystemZ/insn-chhsi.txt new file mode 100644 index 0000000000..6952f481cc --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-chhsi.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: chhsi 0, 0 +0xe5 0x54 0x00 0x00 0x00 0x00 + +# CHECK: chhsi 4095, 0 +0xe5 0x54 0x0f 0xff 0x00 0x00 + +# CHECK: chhsi 0, -32768 +0xe5 0x54 0x00 0x00 0x80 0x00 + +# CHECK: chhsi 0, -1 +0xe5 0x54 0x00 0x00 0xff 0xff + +# CHECK: chhsi 0, 0 +0xe5 0x54 0x00 0x00 0x00 0x00 + +# CHECK: chhsi 0, 1 +0xe5 0x54 0x00 0x00 0x00 0x01 + +# CHECK: chhsi 0, 32767 +0xe5 0x54 0x00 0x00 0x7f 0xff + +# CHECK: chhsi 0(%r1), 42 +0xe5 0x54 0x10 0x00 0x00 0x2a + +# CHECK: chhsi 0(%r15), 42 +0xe5 0x54 0xf0 0x00 0x00 0x2a + +# CHECK: chhsi 4095(%r1), 42 +0xe5 0x54 0x1f 0xff 0x00 0x2a + +# CHECK: chhsi 4095(%r15), 42 +0xe5 0x54 0xff 0xff 0x00 0x2a diff --git a/test/MC/Disassembler/SystemZ/insn-chi.txt b/test/MC/Disassembler/SystemZ/insn-chi.txt new file mode 100644 index 0000000000..a334582f3e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-chi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: chi %r0, -32768 +0xa7 0x0e 0x80 0x00 + +# CHECK: chi %r0, -1 +0xa7 0x0e 0xff 0xff + +# CHECK: chi %r0, 0 +0xa7 0x0e 0x00 0x00 + +# CHECK: chi %r0, 1 +0xa7 0x0e 0x00 0x01 + +# CHECK: chi %r0, 32767 +0xa7 0x0e 0x7f 0xff + +# CHECK: chi %r15, 0 +0xa7 0xfe 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-chrl.txt b/test/MC/Disassembler/SystemZ/insn-chrl.txt new file mode 100644 index 0000000000..1724329e8c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-chrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: chrl %r0, 0x0 +0xc6 0x05 0x00 0x00 0x00 0x00 + +# CHECK: chrl %r15, 0x6 +0xc6 0xf5 0x00 0x00 0x00 0x00 + +# CHECK: chrl %r0, 0xa +0xc6 0x05 0xff 0xff 0xff 0xff + +# CHECK: chrl %r15, 0x10 +0xc6 0xf5 0xff 0xff 0xff 0xff + +# CHECK: chrl %r0, 0xffffffff00000018 +0xc6 0x05 0x80 0x00 0x00 0x00 + +# CHECK: chrl %r15, 0xffffffff0000001e +0xc6 0xf5 0x80 0x00 0x00 0x00 + +# CHECK: chrl %r0, 0x100000022 +0xc6 0x05 0x7f 0xff 0xff 0xff + +# CHECK: chrl %r15, 0x100000028 +0xc6 0xf5 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-chsi.txt b/test/MC/Disassembler/SystemZ/insn-chsi.txt new file mode 100644 index 0000000000..09f658dc6d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-chsi.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: chsi 0, 0 +0xe5 0x5c 0x00 0x00 0x00 0x00 + +# CHECK: chsi 4095, 0 +0xe5 0x5c 0x0f 0xff 0x00 0x00 + +# CHECK: chsi 0, -32768 +0xe5 0x5c 0x00 0x00 0x80 0x00 + +# CHECK: chsi 0, -1 +0xe5 0x5c 0x00 0x00 0xff 0xff + +# CHECK: chsi 0, 0 +0xe5 0x5c 0x00 0x00 0x00 0x00 + +# CHECK: chsi 0, 1 +0xe5 0x5c 0x00 0x00 0x00 0x01 + +# CHECK: chsi 0, 32767 +0xe5 0x5c 0x00 0x00 0x7f 0xff + +# CHECK: chsi 0(%r1), 42 +0xe5 0x5c 0x10 0x00 0x00 0x2a + +# CHECK: chsi 0(%r15), 42 +0xe5 0x5c 0xf0 0x00 0x00 0x2a + +# CHECK: chsi 4095(%r1), 42 +0xe5 0x5c 0x1f 0xff 0x00 0x2a + +# CHECK: chsi 4095(%r15), 42 +0xe5 0x5c 0xff 0xff 0x00 0x2a diff --git a/test/MC/Disassembler/SystemZ/insn-chy.txt b/test/MC/Disassembler/SystemZ/insn-chy.txt new file mode 100644 index 0000000000..dc5308d362 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-chy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: chy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x79 + +# CHECK: chy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x79 + +# CHECK: chy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x79 + +# CHECK: chy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x79 + +# CHECK: chy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x79 + +# CHECK: chy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x79 + +# CHECK: chy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x79 + +# CHECK: chy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x79 + +# CHECK: chy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x79 + +# CHECK: chy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x79 diff --git a/test/MC/Disassembler/SystemZ/insn-cl.txt b/test/MC/Disassembler/SystemZ/insn-cl.txt new file mode 100644 index 0000000000..fd2364d150 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cl.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cl %r0, 0 +0x55 0x00 0x00 0x00 + +# CHECK: cl %r0, 4095 +0x55 0x00 0x0f 0xff + +# CHECK: cl %r0, 0(%r1) +0x55 0x00 0x10 0x00 + +# CHECK: cl %r0, 0(%r15) +0x55 0x00 0xf0 0x00 + +# CHECK: cl %r0, 4095(%r1,%r15) +0x55 0x01 0xff 0xff + +# CHECK: cl %r0, 4095(%r15,%r1) +0x55 0x0f 0x1f 0xff + +# CHECK: cl %r15, 0 +0x55 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-clfhsi.txt b/test/MC/Disassembler/SystemZ/insn-clfhsi.txt new file mode 100644 index 0000000000..e2457169fd --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clfhsi.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clfhsi 0, 0 +0xe5 0x5d 0x00 0x00 0x00 0x00 + +# CHECK: clfhsi 4095, 0 +0xe5 0x5d 0x0f 0xff 0x00 0x00 + +# CHECK: clfhsi 0, 65535 +0xe5 0x5d 0x00 0x00 0xff 0xff + +# CHECK: clfhsi 0(%r1), 42 +0xe5 0x5d 0x10 0x00 0x00 0x2a + +# CHECK: clfhsi 0(%r15), 42 +0xe5 0x5d 0xf0 0x00 0x00 0x2a + +# CHECK: clfhsi 4095(%r1), 42 +0xe5 0x5d 0x1f 0xff 0x00 0x2a + +# CHECK: clfhsi 4095(%r15), 42 +0xe5 0x5d 0xff 0xff 0x00 0x2a diff --git a/test/MC/Disassembler/SystemZ/insn-clfi.txt b/test/MC/Disassembler/SystemZ/insn-clfi.txt new file mode 100644 index 0000000000..24fe22801d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clfi.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clfi %r0, 0 +0xc2 0x0f 0x00 0x00 0x00 0x00 + +# CHECK: clfi %r0, 4294967295 +0xc2 0x0f 0xff 0xff 0xff 0xff + +# CHECK: clfi %r15, 0 +0xc2 0xff 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-clg.txt b/test/MC/Disassembler/SystemZ/insn-clg.txt new file mode 100644 index 0000000000..cf579c815c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x21 + +# CHECK: clg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x21 + +# CHECK: clg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x21 + +# CHECK: clg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x21 + +# CHECK: clg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x21 + +# CHECK: clg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x21 + +# CHECK: clg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x21 + +# CHECK: clg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x21 + +# CHECK: clg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x21 + +# CHECK: clg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x21 diff --git a/test/MC/Disassembler/SystemZ/insn-clgf.txt b/test/MC/Disassembler/SystemZ/insn-clgf.txt new file mode 100644 index 0000000000..61b701e2fb --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clgf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x31 + +# CHECK: clgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x31 + +# CHECK: clgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x31 + +# CHECK: clgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x31 + +# CHECK: clgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x31 + +# CHECK: clgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x31 + +# CHECK: clgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x31 + +# CHECK: clgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x31 + +# CHECK: clgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x31 + +# CHECK: clgf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x31 diff --git a/test/MC/Disassembler/SystemZ/insn-clgfi.txt b/test/MC/Disassembler/SystemZ/insn-clgfi.txt new file mode 100644 index 0000000000..5972e5e636 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clgfi.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clgfi %r0, 0 +0xc2 0x0e 0x00 0x00 0x00 0x00 + +# CHECK: clgfi %r0, 4294967295 +0xc2 0x0e 0xff 0xff 0xff 0xff + +# CHECK: clgfi %r15, 0 +0xc2 0xfe 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-clgfr.txt b/test/MC/Disassembler/SystemZ/insn-clgfr.txt new file mode 100644 index 0000000000..81cf51c93a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clgfr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clgfr %r0, %r0 +0xb9 0x31 0x00 0x00 + +# CHECK: clgfr %r0, %r15 +0xb9 0x31 0x00 0x0f + +# CHECK: clgfr %r15, %r0 +0xb9 0x31 0x00 0xf0 + +# CHECK: clgfr %r7, %r8 +0xb9 0x31 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-clgfrl.txt b/test/MC/Disassembler/SystemZ/insn-clgfrl.txt new file mode 100644 index 0000000000..108472be5a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clgfrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clgfrl %r0, 0x0 +0xc6 0x0e 0x00 0x00 0x00 0x00 + +# CHECK: clgfrl %r15, 0x6 +0xc6 0xfe 0x00 0x00 0x00 0x00 + +# CHECK: clgfrl %r0, 0xa +0xc6 0x0e 0xff 0xff 0xff 0xff + +# CHECK: clgfrl %r15, 0x10 +0xc6 0xfe 0xff 0xff 0xff 0xff + +# CHECK: clgfrl %r0, 0xffffffff00000018 +0xc6 0x0e 0x80 0x00 0x00 0x00 + +# CHECK: clgfrl %r15, 0xffffffff0000001e +0xc6 0xfe 0x80 0x00 0x00 0x00 + +# CHECK: clgfrl %r0, 0x100000022 +0xc6 0x0e 0x7f 0xff 0xff 0xff + +# CHECK: clgfrl %r15, 0x100000028 +0xc6 0xfe 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-clghrl.txt b/test/MC/Disassembler/SystemZ/insn-clghrl.txt new file mode 100644 index 0000000000..23048fe3f4 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clghrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clghrl %r0, 0x0 +0xc6 0x06 0x00 0x00 0x00 0x00 + +# CHECK: clghrl %r15, 0x6 +0xc6 0xf6 0x00 0x00 0x00 0x00 + +# CHECK: clghrl %r0, 0xa +0xc6 0x06 0xff 0xff 0xff 0xff + +# CHECK: clghrl %r15, 0x10 +0xc6 0xf6 0xff 0xff 0xff 0xff + +# CHECK: clghrl %r0, 0xffffffff00000018 +0xc6 0x06 0x80 0x00 0x00 0x00 + +# CHECK: clghrl %r15, 0xffffffff0000001e +0xc6 0xf6 0x80 0x00 0x00 0x00 + +# CHECK: clghrl %r0, 0x100000022 +0xc6 0x06 0x7f 0xff 0xff 0xff + +# CHECK: clghrl %r15, 0x100000028 +0xc6 0xf6 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-clghsi.txt b/test/MC/Disassembler/SystemZ/insn-clghsi.txt new file mode 100644 index 0000000000..64259ffcf5 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clghsi.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clghsi 0, 0 +0xe5 0x59 0x00 0x00 0x00 0x00 + +# CHECK: clghsi 4095, 0 +0xe5 0x59 0x0f 0xff 0x00 0x00 + +# CHECK: clghsi 0, 65535 +0xe5 0x59 0x00 0x00 0xff 0xff + +# CHECK: clghsi 0(%r1), 42 +0xe5 0x59 0x10 0x00 0x00 0x2a + +# CHECK: clghsi 0(%r15), 42 +0xe5 0x59 0xf0 0x00 0x00 0x2a + +# CHECK: clghsi 4095(%r1), 42 +0xe5 0x59 0x1f 0xff 0x00 0x2a + +# CHECK: clghsi 4095(%r15), 42 +0xe5 0x59 0xff 0xff 0x00 0x2a diff --git a/test/MC/Disassembler/SystemZ/insn-clgr.txt b/test/MC/Disassembler/SystemZ/insn-clgr.txt new file mode 100644 index 0000000000..70e3f5f033 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clgr %r0, %r0 +0xb9 0x21 0x00 0x00 + +# CHECK: clgr %r0, %r15 +0xb9 0x21 0x00 0x0f + +# CHECK: clgr %r15, %r0 +0xb9 0x21 0x00 0xf0 + +# CHECK: clgr %r7, %r8 +0xb9 0x21 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-clgrl.txt b/test/MC/Disassembler/SystemZ/insn-clgrl.txt new file mode 100644 index 0000000000..cad4c7849d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clgrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clgrl %r0, 0x0 +0xc6 0x0a 0x00 0x00 0x00 0x00 + +# CHECK: clgrl %r15, 0x6 +0xc6 0xfa 0x00 0x00 0x00 0x00 + +# CHECK: clgrl %r0, 0xa +0xc6 0x0a 0xff 0xff 0xff 0xff + +# CHECK: clgrl %r15, 0x10 +0xc6 0xfa 0xff 0xff 0xff 0xff + +# CHECK: clgrl %r0, 0xffffffff00000018 +0xc6 0x0a 0x80 0x00 0x00 0x00 + +# CHECK: clgrl %r15, 0xffffffff0000001e +0xc6 0xfa 0x80 0x00 0x00 0x00 + +# CHECK: clgrl %r0, 0x100000022 +0xc6 0x0a 0x7f 0xff 0xff 0xff + +# CHECK: clgrl %r15, 0x100000028 +0xc6 0xfa 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-clhhsi.txt b/test/MC/Disassembler/SystemZ/insn-clhhsi.txt new file mode 100644 index 0000000000..8da079b273 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clhhsi.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clhhsi 0, 0 +0xe5 0x55 0x00 0x00 0x00 0x00 + +# CHECK: clhhsi 4095, 0 +0xe5 0x55 0x0f 0xff 0x00 0x00 + +# CHECK: clhhsi 0, 65535 +0xe5 0x55 0x00 0x00 0xff 0xff + +# CHECK: clhhsi 0(%r1), 42 +0xe5 0x55 0x10 0x00 0x00 0x2a + +# CHECK: clhhsi 0(%r15), 42 +0xe5 0x55 0xf0 0x00 0x00 0x2a + +# CHECK: clhhsi 4095(%r1), 42 +0xe5 0x55 0x1f 0xff 0x00 0x2a + +# CHECK: clhhsi 4095(%r15), 42 +0xe5 0x55 0xff 0xff 0x00 0x2a diff --git a/test/MC/Disassembler/SystemZ/insn-clhrl.txt b/test/MC/Disassembler/SystemZ/insn-clhrl.txt new file mode 100644 index 0000000000..6fdd9e23df --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clhrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clhrl %r0, 0xaabbccdc +0xc6 0x07 0x55 0x5d 0xe6 0x6e + +# CHECK: clhrl %r15, 0xaabbcce2 +0xc6 0xf7 0x55 0x5d 0xe6 0x6e + +# CHECK: clhrl %r0, 0xc +0xc6 0x07 0x00 0x00 0x00 0x00 + +# CHECK: clhrl %r15, 0x12 +0xc6 0xf7 0x00 0x00 0x00 0x00 + +# CHECK: clhrl %r3, 0x18 +0xc6 0x37 0x00 0x00 0x00 0x00 + +# CHECK: clhrl %r4, 0x1e +0xc6 0x47 0x00 0x00 0x00 0x00 + +# CHECK: clhrl %r7, 0x24 +0xc6 0x77 0x00 0x00 0x00 0x00 + +# CHECK: clhrl %r8, 0x2a +0xc6 0x87 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-cli.txt b/test/MC/Disassembler/SystemZ/insn-cli.txt new file mode 100644 index 0000000000..5c730e23b6 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cli.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cli 0, 0 +0x95 0x00 0x00 0x00 + +# CHECK: cli 4095, 0 +0x95 0x00 0x0f 0xff + +# CHECK: cli 0, 255 +0x95 0xff 0x00 0x00 + +# CHECK: cli 0(%r1), 42 +0x95 0x2a 0x10 0x00 + +# CHECK: cli 0(%r15), 42 +0x95 0x2a 0xf0 0x00 + +# CHECK: cli 4095(%r1), 42 +0x95 0x2a 0x1f 0xff + +# CHECK: cli 4095(%r15), 42 +0x95 0x2a 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cliy.txt b/test/MC/Disassembler/SystemZ/insn-cliy.txt new file mode 100644 index 0000000000..6faa1244ce --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cliy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cliy -524288, 0 +0xeb 0x00 0x00 0x00 0x80 0x55 + +# CHECK: cliy -1, 0 +0xeb 0x00 0x0f 0xff 0xff 0x55 + +# CHECK: cliy 0, 0 +0xeb 0x00 0x00 0x00 0x00 0x55 + +# CHECK: cliy 1, 0 +0xeb 0x00 0x00 0x01 0x00 0x55 + +# CHECK: cliy 524287, 0 +0xeb 0x00 0x0f 0xff 0x7f 0x55 + +# CHECK: cliy 0, 255 +0xeb 0xff 0x00 0x00 0x00 0x55 + +# CHECK: cliy 0(%r1), 42 +0xeb 0x2a 0x10 0x00 0x00 0x55 + +# CHECK: cliy 0(%r15), 42 +0xeb 0x2a 0xf0 0x00 0x00 0x55 + +# CHECK: cliy 524287(%r1), 42 +0xeb 0x2a 0x1f 0xff 0x7f 0x55 + +# CHECK: cliy 524287(%r15), 42 +0xeb 0x2a 0xff 0xff 0x7f 0x55 diff --git a/test/MC/Disassembler/SystemZ/insn-clr.txt b/test/MC/Disassembler/SystemZ/insn-clr.txt new file mode 100644 index 0000000000..81a1734d06 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clr %r0, %r0 +0x15 0x00 + +# CHECK: clr %r0, %r15 +0x15 0x0f + +# CHECK: clr %r15, %r0 +0x15 0xf0 + +# CHECK: clr %r7, %r8 +0x15 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-clrl.txt b/test/MC/Disassembler/SystemZ/insn-clrl.txt new file mode 100644 index 0000000000..72d0a46239 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-clrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: clrl %r0, 0x0 +0xc6 0x0f 0x00 0x00 0x00 0x00 + +# CHECK: clrl %r15, 0x6 +0xc6 0xff 0x00 0x00 0x00 0x00 + +# CHECK: clrl %r0, 0xa +0xc6 0x0f 0xff 0xff 0xff 0xff + +# CHECK: clrl %r15, 0x10 +0xc6 0xff 0xff 0xff 0xff 0xff + +# CHECK: clrl %r0, 0xffffffff00000018 +0xc6 0x0f 0x80 0x00 0x00 0x00 + +# CHECK: clrl %r15, 0xffffffff0000001e +0xc6 0xff 0x80 0x00 0x00 0x00 + +# CHECK: clrl %r0, 0x100000022 +0xc6 0x0f 0x7f 0xff 0xff 0xff + +# CHECK: clrl %r15, 0x100000028 +0xc6 0xff 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cly.txt b/test/MC/Disassembler/SystemZ/insn-cly.txt new file mode 100644 index 0000000000..70878f09f7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cly.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cly %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x55 + +# CHECK: cly %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x55 + +# CHECK: cly %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x55 + +# CHECK: cly %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x55 + +# CHECK: cly %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x55 + +# CHECK: cly %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x55 + +# CHECK: cly %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x55 + +# CHECK: cly %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x55 + +# CHECK: cly %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x55 + +# CHECK: cly %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x55 diff --git a/test/MC/Disassembler/SystemZ/insn-cpsdr.txt b/test/MC/Disassembler/SystemZ/insn-cpsdr.txt new file mode 100644 index 0000000000..d61686e2e1 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cpsdr.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cpsdr %f0, %f0, %f0 +0xb3 0x72 0x00 0x00 + +# CHECK: cpsdr %f0, %f0, %f15 +0xb3 0x72 0x00 0x0f + +# CHECK: cpsdr %f0, %f15, %f0 +0xb3 0x72 0xf0 0x00 + +# CHECK: cpsdr %f15, %f0, %f0 +0xb3 0x72 0x00 0xf0 + +# CHECK: cpsdr %f1, %f2, %f3 +0xb3 0x72 0x20 0x13 + +# CHECK: cpsdr %f15, %f15, %f15 +0xb3 0x72 0xf0 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cr.txt b/test/MC/Disassembler/SystemZ/insn-cr.txt new file mode 100644 index 0000000000..3072773178 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cr %r0, %r0 +0x19 0x00 + +# CHECK: cr %r0, %r15 +0x19 0x0f + +# CHECK: cr %r15, %r0 +0x19 0xf0 + +# CHECK: cr %r7, %r8 +0x19 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-crl.txt b/test/MC/Disassembler/SystemZ/insn-crl.txt new file mode 100644 index 0000000000..e2d98a9257 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-crl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: crl %r0, 0x0 +0xc6 0x0d 0x00 0x00 0x00 0x00 + +# CHECK: crl %r15, 0x6 +0xc6 0xfd 0x00 0x00 0x00 0x00 + +# CHECK: crl %r0, 0xa +0xc6 0x0d 0xff 0xff 0xff 0xff + +# CHECK: crl %r15, 0x10 +0xc6 0xfd 0xff 0xff 0xff 0xff + +# CHECK: crl %r0, 0xffffffff00000018 +0xc6 0x0d 0x80 0x00 0x00 0x00 + +# CHECK: crl %r15, 0xffffffff0000001e +0xc6 0xfd 0x80 0x00 0x00 0x00 + +# CHECK: crl %r0, 0x100000022 +0xc6 0x0d 0x7f 0xff 0xff 0xff + +# CHECK: crl %r15, 0x100000028 +0xc6 0xfd 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-cs.txt b/test/MC/Disassembler/SystemZ/insn-cs.txt new file mode 100644 index 0000000000..63765f2d73 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cs.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cs %r0, %r0, 0 +0xba 0x00 0x00 0x00 + +# CHECK: cs %r0, %r0, 4095 +0xba 0x00 0x0f 0xff + +# CHECK: cs %r0, %r0, 0(%r1) +0xba 0x00 0x10 0x00 + +# CHECK: cs %r0, %r0, 0(%r15) +0xba 0x00 0xf0 0x00 + +# CHECK: cs %r0, %r0, 4095(%r1) +0xba 0x00 0x1f 0xff + +# CHECK: cs %r0, %r0, 4095(%r15) +0xba 0x00 0xff 0xff + +# CHECK: cs %r0, %r15, 0 +0xba 0x0f 0x00 0x00 + +# CHECK: cs %r15, %r0, 0 +0xba 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-csg.txt b/test/MC/Disassembler/SystemZ/insn-csg.txt new file mode 100644 index 0000000000..a1fc7337de --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-csg.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: csg %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x30 + +# CHECK: csg %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x30 + +# CHECK: csg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x30 + +# CHECK: csg %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x30 + +# CHECK: csg %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x30 + +# CHECK: csg %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x30 + +# CHECK: csg %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x30 + +# CHECK: csg %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x30 + +# CHECK: csg %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x30 + +# CHECK: csg %r0, %r15, 0 +0xeb 0x0f 0x00 0x00 0x00 0x30 + +# CHECK: csg %r15, %r0, 0 +0xeb 0xf0 0x00 0x00 0x00 0x30 diff --git a/test/MC/Disassembler/SystemZ/insn-csy.txt b/test/MC/Disassembler/SystemZ/insn-csy.txt new file mode 100644 index 0000000000..d112afbb6c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-csy.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: csy %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x14 + +# CHECK: csy %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x14 + +# CHECK: csy %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x14 + +# CHECK: csy %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x14 + +# CHECK: csy %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x14 + +# CHECK: csy %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x14 + +# CHECK: csy %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x14 + +# CHECK: csy %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x14 + +# CHECK: csy %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x14 + +# CHECK: csy %r0, %r15, 0 +0xeb 0x0f 0x00 0x00 0x00 0x14 + +# CHECK: csy %r15, %r0, 0 +0xeb 0xf0 0x00 0x00 0x00 0x14 diff --git a/test/MC/Disassembler/SystemZ/insn-cxbr.txt b/test/MC/Disassembler/SystemZ/insn-cxbr.txt new file mode 100644 index 0000000000..fe212bdeb7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cxbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cxbr %f0, %f0 +0xb3 0x49 0x00 0x00 + +# CHECK: cxbr %f0, %f13 +0xb3 0x49 0x00 0x0d + +# CHECK: cxbr %f8, %f8 +0xb3 0x49 0x00 0x88 + +# CHECK: cxbr %f13, %f0 +0xb3 0x49 0x00 0xd0 diff --git a/test/MC/Disassembler/SystemZ/insn-cxfbr.txt b/test/MC/Disassembler/SystemZ/insn-cxfbr.txt new file mode 100644 index 0000000000..2a1199c8d7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cxfbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cxfbr %f0, %r0 +0xb3 0x96 0x00 0x00 + +# CHECK: cxfbr %f0, %r15 +0xb3 0x96 0x00 0x0f + +# CHECK: cxfbr %f13, %r0 +0xb3 0x96 0x00 0xd0 + +# CHECK: cxfbr %f8, %r7 +0xb3 0x96 0x00 0x87 + +# CHECK: cxfbr %f13, %r15 +0xb3 0x96 0x00 0xdf diff --git a/test/MC/Disassembler/SystemZ/insn-cxgbr.txt b/test/MC/Disassembler/SystemZ/insn-cxgbr.txt new file mode 100644 index 0000000000..83fa1e87fe --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cxgbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cxgbr %f0, %r0 +0xb3 0xa6 0x00 0x00 + +# CHECK: cxgbr %f0, %r15 +0xb3 0xa6 0x00 0x0f + +# CHECK: cxgbr %f13, %r0 +0xb3 0xa6 0x00 0xd0 + +# CHECK: cxgbr %f8, %r7 +0xb3 0xa6 0x00 0x87 + +# CHECK: cxgbr %f13, %r15 +0xb3 0xa6 0x00 0xdf diff --git a/test/MC/Disassembler/SystemZ/insn-cy.txt b/test/MC/Disassembler/SystemZ/insn-cy.txt new file mode 100644 index 0000000000..20a2cba769 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-cy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: cy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x59 + +# CHECK: cy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x59 + +# CHECK: cy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x59 + +# CHECK: cy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x59 + +# CHECK: cy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x59 + +# CHECK: cy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x59 + +# CHECK: cy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x59 + +# CHECK: cy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x59 + +# CHECK: cy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x59 + +# CHECK: cy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x59 diff --git a/test/MC/Disassembler/SystemZ/insn-ddb.txt b/test/MC/Disassembler/SystemZ/insn-ddb.txt new file mode 100644 index 0000000000..8c8e012307 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ddb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ddb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x1d + +# CHECK: ddb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x1d + +# CHECK: ddb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x1d + +# CHECK: ddb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x1d + +# CHECK: ddb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x1d + +# CHECK: ddb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x1d + +# CHECK: ddb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x1d diff --git a/test/MC/Disassembler/SystemZ/insn-ddbr.txt b/test/MC/Disassembler/SystemZ/insn-ddbr.txt new file mode 100644 index 0000000000..cba474e4c4 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ddbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ddbr %f0, %f0 +0xb3 0x1d 0x00 0x00 + +# CHECK: ddbr %f0, %f15 +0xb3 0x1d 0x00 0x0f + +# CHECK: ddbr %f7, %f8 +0xb3 0x1d 0x00 0x78 + +# CHECK: ddbr %f15, %f0 +0xb3 0x1d 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-deb.txt b/test/MC/Disassembler/SystemZ/insn-deb.txt new file mode 100644 index 0000000000..e983027588 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-deb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: deb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x0d + +# CHECK: deb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x0d + +# CHECK: deb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x0d + +# CHECK: deb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x0d + +# CHECK: deb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x0d + +# CHECK: deb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x0d + +# CHECK: deb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x0d diff --git a/test/MC/Disassembler/SystemZ/insn-debr.txt b/test/MC/Disassembler/SystemZ/insn-debr.txt new file mode 100644 index 0000000000..8af807c707 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-debr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: debr %f0, %f0 +0xb3 0x0d 0x00 0x00 + +# CHECK: debr %f0, %f15 +0xb3 0x0d 0x00 0x0f + +# CHECK: debr %f7, %f8 +0xb3 0x0d 0x00 0x78 + +# CHECK: debr %f15, %f0 +0xb3 0x0d 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-dl.txt b/test/MC/Disassembler/SystemZ/insn-dl.txt new file mode 100644 index 0000000000..6762f0f532 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-dl.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: dl %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x97 + +# CHECK: dl %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x97 + +# CHECK: dl %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x97 + +# CHECK: dl %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x97 + +# CHECK: dl %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x97 + +# CHECK: dl %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x97 + +# CHECK: dl %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x97 + +# CHECK: dl %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x97 + +# CHECK: dl %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x97 + +# CHECK: dl %r14, 0 +0xe3 0xe0 0x00 0x00 0x00 0x97 diff --git a/test/MC/Disassembler/SystemZ/insn-dlg.txt b/test/MC/Disassembler/SystemZ/insn-dlg.txt new file mode 100644 index 0000000000..374fd36a94 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-dlg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: dlg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x87 + +# CHECK: dlg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x87 + +# CHECK: dlg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x87 + +# CHECK: dlg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x87 + +# CHECK: dlg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x87 + +# CHECK: dlg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x87 + +# CHECK: dlg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x87 + +# CHECK: dlg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x87 + +# CHECK: dlg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x87 + +# CHECK: dlg %r14, 0 +0xe3 0xe0 0x00 0x00 0x00 0x87 diff --git a/test/MC/Disassembler/SystemZ/insn-dlgr.txt b/test/MC/Disassembler/SystemZ/insn-dlgr.txt new file mode 100644 index 0000000000..91c15565d4 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-dlgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: dlgr %r0, %r0 +0xb9 0x87 0x00 0x00 + +# CHECK: dlgr %r0, %r15 +0xb9 0x87 0x00 0x0f + +# CHECK: dlgr %r14, %r0 +0xb9 0x87 0x00 0xe0 + +# CHECK: dlgr %r6, %r9 +0xb9 0x87 0x00 0x69 diff --git a/test/MC/Disassembler/SystemZ/insn-dlr.txt b/test/MC/Disassembler/SystemZ/insn-dlr.txt new file mode 100644 index 0000000000..035cb6c7a7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-dlr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: dlr %r0, %r0 +0xb9 0x97 0x00 0x00 + +# CHECK: dlr %r0, %r15 +0xb9 0x97 0x00 0x0f + +# CHECK: dlr %r14, %r0 +0xb9 0x97 0x00 0xe0 + +# CHECK: dlr %r6, %r9 +0xb9 0x97 0x00 0x69 diff --git a/test/MC/Disassembler/SystemZ/insn-dsg.txt b/test/MC/Disassembler/SystemZ/insn-dsg.txt new file mode 100644 index 0000000000..00b6a3f1dc --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-dsg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: dsg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x0d + +# CHECK: dsg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x0d + +# CHECK: dsg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x0d + +# CHECK: dsg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x0d + +# CHECK: dsg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x0d + +# CHECK: dsg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x0d + +# CHECK: dsg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x0d + +# CHECK: dsg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x0d + +# CHECK: dsg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x0d + +# CHECK: dsg %r14, 0 +0xe3 0xe0 0x00 0x00 0x00 0x0d diff --git a/test/MC/Disassembler/SystemZ/insn-dsgf.txt b/test/MC/Disassembler/SystemZ/insn-dsgf.txt new file mode 100644 index 0000000000..eb68d5c8cd --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-dsgf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: dsgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x1d + +# CHECK: dsgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x1d + +# CHECK: dsgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x1d + +# CHECK: dsgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x1d + +# CHECK: dsgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x1d + +# CHECK: dsgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x1d + +# CHECK: dsgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x1d + +# CHECK: dsgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x1d + +# CHECK: dsgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x1d + +# CHECK: dsgf %r14, 0 +0xe3 0xe0 0x00 0x00 0x00 0x1d diff --git a/test/MC/Disassembler/SystemZ/insn-dsgfr.txt b/test/MC/Disassembler/SystemZ/insn-dsgfr.txt new file mode 100644 index 0000000000..103bea652e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-dsgfr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: dsgfr %r0, %r0 +0xb9 0x1d 0x00 0x00 + +# CHECK: dsgfr %r0, %r15 +0xb9 0x1d 0x00 0x0f + +# CHECK: dsgfr %r14, %r0 +0xb9 0x1d 0x00 0xe0 + +# CHECK: dsgfr %r6, %r9 +0xb9 0x1d 0x00 0x69 diff --git a/test/MC/Disassembler/SystemZ/insn-dsgr.txt b/test/MC/Disassembler/SystemZ/insn-dsgr.txt new file mode 100644 index 0000000000..aa7df55178 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-dsgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: dsgr %r0, %r0 +0xb9 0x0d 0x00 0x00 + +# CHECK: dsgr %r0, %r15 +0xb9 0x0d 0x00 0x0f + +# CHECK: dsgr %r14, %r0 +0xb9 0x0d 0x00 0xe0 + +# CHECK: dsgr %r6, %r9 +0xb9 0x0d 0x00 0x69 diff --git a/test/MC/Disassembler/SystemZ/insn-dxbr.txt b/test/MC/Disassembler/SystemZ/insn-dxbr.txt new file mode 100644 index 0000000000..492b9e8892 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-dxbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: dxbr %f0, %f0 +0xb3 0x4d 0x00 0x00 + +# CHECK: dxbr %f0, %f13 +0xb3 0x4d 0x00 0x0d + +# CHECK: dxbr %f8, %f8 +0xb3 0x4d 0x00 0x88 + +# CHECK: dxbr %f13, %f0 +0xb3 0x4d 0x00 0xd0 diff --git a/test/MC/Disassembler/SystemZ/insn-ear.txt b/test/MC/Disassembler/SystemZ/insn-ear.txt new file mode 100644 index 0000000000..dbf240531e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ear.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ear %r0, %a0 +0xb2 0x4f 0x00 0x00 + +# CHECK: ear %r0, %a15 +0xb2 0x4f 0x00 0x0f + +# CHECK: ear %r15, %a0 +0xb2 0x4f 0x00 0xf0 + +# CHECK: ear %r7, %a8 +0xb2 0x4f 0x00 0x78 + +# CHECK: ear %r15, %a15 +0xb2 0x4f 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-fidbr.txt b/test/MC/Disassembler/SystemZ/insn-fidbr.txt new file mode 100644 index 0000000000..ffc0933458 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-fidbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: fidbr %f0, 0, %f0 +0xb3 0x5f 0x00 0x00 + +# CHECK: fidbr %f0, 0, %f15 +0xb3 0x5f 0x00 0x0f + +# CHECK: fidbr %f0, 15, %f0 +0xb3 0x5f 0xf0 0x00 + +# CHECK: fidbr %f4, 5, %f6 +0xb3 0x5f 0x50 0x46 + +# CHECK: fidbr %f15, 0, %f0 +0xb3 0x5f 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-fiebr.txt b/test/MC/Disassembler/SystemZ/insn-fiebr.txt new file mode 100644 index 0000000000..94d8e7b812 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-fiebr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: fiebr %f0, 0, %f0 +0xb3 0x57 0x00 0x00 + +# CHECK: fiebr %f0, 0, %f15 +0xb3 0x57 0x00 0x0f + +# CHECK: fiebr %f0, 15, %f0 +0xb3 0x57 0xf0 0x00 + +# CHECK: fiebr %f4, 5, %f6 +0xb3 0x57 0x50 0x46 + +# CHECK: fiebr %f15, 0, %f0 +0xb3 0x57 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-fixbr.txt b/test/MC/Disassembler/SystemZ/insn-fixbr.txt new file mode 100644 index 0000000000..25ce43e7da --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-fixbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: fixbr %f0, 0, %f0 +0xb3 0x47 0x00 0x00 + +# CHECK: fixbr %f0, 0, %f13 +0xb3 0x47 0x00 0x0d + +# CHECK: fixbr %f0, 15, %f0 +0xb3 0x47 0xf0 0x00 + +# CHECK: fixbr %f4, 5, %f8 +0xb3 0x47 0x50 0x48 + +# CHECK: fixbr %f13, 0, %f0 +0xb3 0x47 0x00 0xd0 diff --git a/test/MC/Disassembler/SystemZ/insn-flogr.txt b/test/MC/Disassembler/SystemZ/insn-flogr.txt new file mode 100644 index 0000000000..dee0da8800 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-flogr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: flogr %r0, %r0 +0xb9 0x83 0x00 0x00 + +# CHECK: flogr %r0, %r15 +0xb9 0x83 0x00 0x0f + +# CHECK: flogr %r10, %r9 +0xb9 0x83 0x00 0xa9 + +# CHECK: flogr %r14, %r0 +0xb9 0x83 0x00 0xe0 diff --git a/test/MC/Disassembler/SystemZ/insn-ic.txt b/test/MC/Disassembler/SystemZ/insn-ic.txt new file mode 100644 index 0000000000..989f03e2e5 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ic.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ic %r0, 0 +0x43 0x00 0x00 0x00 + +# CHECK: ic %r0, 4095 +0x43 0x00 0x0f 0xff + +# CHECK: ic %r0, 0(%r1) +0x43 0x00 0x10 0x00 + +# CHECK: ic %r0, 0(%r15) +0x43 0x00 0xf0 0x00 + +# CHECK: ic %r0, 4095(%r1,%r15) +0x43 0x01 0xff 0xff + +# CHECK: ic %r0, 4095(%r15,%r1) +0x43 0x0f 0x1f 0xff + +# CHECK: ic %r15, 0 +0x43 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-icy.txt b/test/MC/Disassembler/SystemZ/insn-icy.txt new file mode 100644 index 0000000000..3ae53106ca --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-icy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: icy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x73 + +# CHECK: icy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x73 + +# CHECK: icy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x73 + +# CHECK: icy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x73 + +# CHECK: icy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x73 + +# CHECK: icy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x73 + +# CHECK: icy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x73 + +# CHECK: icy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x73 + +# CHECK: icy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x73 + +# CHECK: icy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x73 diff --git a/test/MC/Disassembler/SystemZ/insn-iihf.txt b/test/MC/Disassembler/SystemZ/insn-iihf.txt new file mode 100644 index 0000000000..d4f46c4ea0 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-iihf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: iihf %r0, 0 +0xc0 0x08 0x00 0x00 0x00 0x00 + +# CHECK: iihf %r0, 4294967295 +0xc0 0x08 0xff 0xff 0xff 0xff + +# CHECK: iihf %r15, 0 +0xc0 0xf8 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-iihh.txt b/test/MC/Disassembler/SystemZ/insn-iihh.txt new file mode 100644 index 0000000000..aed6ba8c4d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-iihh.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: iihh %r0, 0 +0xa5 0x00 0x00 0x00 + +# CHECK: iihh %r0, 32768 +0xa5 0x00 0x80 0x00 + +# CHECK: iihh %r0, 65535 +0xa5 0x00 0xff 0xff + +# CHECK: iihh %r15, 0 +0xa5 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-iihl.txt b/test/MC/Disassembler/SystemZ/insn-iihl.txt new file mode 100644 index 0000000000..9e9b4559ae --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-iihl.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: iihl %r0, 0 +0xa5 0x01 0x00 0x00 + +# CHECK: iihl %r0, 32768 +0xa5 0x01 0x80 0x00 + +# CHECK: iihl %r0, 65535 +0xa5 0x01 0xff 0xff + +# CHECK: iihl %r15, 0 +0xa5 0xf1 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-iilf.txt b/test/MC/Disassembler/SystemZ/insn-iilf.txt new file mode 100644 index 0000000000..c57692db44 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-iilf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: iilf %r0, 0 +0xc0 0x09 0x00 0x00 0x00 0x00 + +# CHECK: iilf %r0, 4294967295 +0xc0 0x09 0xff 0xff 0xff 0xff + +# CHECK: iilf %r15, 0 +0xc0 0xf9 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-iilh.txt b/test/MC/Disassembler/SystemZ/insn-iilh.txt new file mode 100644 index 0000000000..3692cb3908 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-iilh.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: iilh %r0, 0 +0xa5 0x02 0x00 0x00 + +# CHECK: iilh %r0, 32768 +0xa5 0x02 0x80 0x00 + +# CHECK: iilh %r0, 65535 +0xa5 0x02 0xff 0xff + +# CHECK: iilh %r15, 0 +0xa5 0xf2 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-iill.txt b/test/MC/Disassembler/SystemZ/insn-iill.txt new file mode 100644 index 0000000000..2975894e3a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-iill.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: iill %r0, 0 +0xa5 0x03 0x00 0x00 + +# CHECK: iill %r0, 32768 +0xa5 0x03 0x80 0x00 + +# CHECK: iill %r0, 65535 +0xa5 0x03 0xff 0xff + +# CHECK: iill %r15, 0 +0xa5 0xf3 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-l.txt b/test/MC/Disassembler/SystemZ/insn-l.txt new file mode 100644 index 0000000000..a266c487be --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-l.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: l %r0, 0 +0x58 0x00 0x00 0x00 + +# CHECK: l %r0, 4095 +0x58 0x00 0x0f 0xff + +# CHECK: l %r0, 0(%r1) +0x58 0x00 0x10 0x00 + +# CHECK: l %r0, 0(%r15) +0x58 0x00 0xf0 0x00 + +# CHECK: l %r0, 4095(%r1,%r15) +0x58 0x01 0xff 0xff + +# CHECK: l %r0, 4095(%r15,%r1) +0x58 0x0f 0x1f 0xff + +# CHECK: l %r15, 0 +0x58 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-la.txt b/test/MC/Disassembler/SystemZ/insn-la.txt new file mode 100644 index 0000000000..90d99f8581 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-la.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: la %r0, 0 +0x41 0x00 0x00 0x00 + +# CHECK: la %r0, 4095 +0x41 0x00 0x0f 0xff + +# CHECK: la %r0, 0(%r1) +0x41 0x00 0x10 0x00 + +# CHECK: la %r0, 0(%r15) +0x41 0x00 0xf0 0x00 + +# CHECK: la %r0, 4095(%r1,%r15) +0x41 0x01 0xff 0xff + +# CHECK: la %r0, 4095(%r15,%r1) +0x41 0x0f 0x1f 0xff + +# CHECK: la %r15, 0 +0x41 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-larl.txt b/test/MC/Disassembler/SystemZ/insn-larl.txt new file mode 100644 index 0000000000..814bba52da --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-larl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: larl %r0, 0x0 +0xc0 0x00 0x00 0x00 0x00 0x00 + +# CHECK: larl %r15, 0x6 +0xc0 0xf0 0x00 0x00 0x00 0x00 + +# CHECK: larl %r0, 0xa +0xc0 0x00 0xff 0xff 0xff 0xff + +# CHECK: larl %r15, 0x10 +0xc0 0xf0 0xff 0xff 0xff 0xff + +# CHECK: larl %r0, 0xffffffff00000018 +0xc0 0x00 0x80 0x00 0x00 0x00 + +# CHECK: larl %r15, 0xffffffff0000001e +0xc0 0xf0 0x80 0x00 0x00 0x00 + +# CHECK: larl %r0, 0x100000022 +0xc0 0x00 0x7f 0xff 0xff 0xff + +# CHECK: larl %r15, 0x100000028 +0xc0 0xf0 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-lay.txt b/test/MC/Disassembler/SystemZ/insn-lay.txt new file mode 100644 index 0000000000..35b2e50d42 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lay.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lay %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x71 + +# CHECK: lay %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x71 + +# CHECK: lay %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x71 + +# CHECK: lay %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x71 + +# CHECK: lay %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x71 + +# CHECK: lay %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x71 + +# CHECK: lay %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x71 + +# CHECK: lay %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x71 + +# CHECK: lay %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x71 + +# CHECK: lay %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x71 diff --git a/test/MC/Disassembler/SystemZ/insn-lb.txt b/test/MC/Disassembler/SystemZ/insn-lb.txt new file mode 100644 index 0000000000..af0e7cce5c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lb.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lb %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x76 + +# CHECK: lb %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x76 + +# CHECK: lb %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x76 + +# CHECK: lb %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x76 + +# CHECK: lb %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x76 + +# CHECK: lb %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x76 + +# CHECK: lb %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x76 + +# CHECK: lb %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x76 + +# CHECK: lb %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x76 + +# CHECK: lb %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x76 diff --git a/test/MC/Disassembler/SystemZ/insn-lbr.txt b/test/MC/Disassembler/SystemZ/insn-lbr.txt new file mode 100644 index 0000000000..9745bcc408 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lbr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lbr %r0, %r15 +0xb9 0x26 0x00 0x0f + +# CHECK: lbr %r7, %r8 +0xb9 0x26 0x00 0x78 + +# CHECK: lbr %r15, %r0 +0xb9 0x26 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-lcdbr.txt b/test/MC/Disassembler/SystemZ/insn-lcdbr.txt new file mode 100644 index 0000000000..409eb2d65f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lcdbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lcdbr %f0, %f9 +0xb3 0x13 0x00 0x09 + +# CHECK: lcdbr %f0, %f15 +0xb3 0x13 0x00 0x0f + +# CHECK: lcdbr %f15, %f0 +0xb3 0x13 0x00 0xf0 + +# CHECK: lcdbr %f15, %f9 +0xb3 0x13 0x00 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-lcebr.txt b/test/MC/Disassembler/SystemZ/insn-lcebr.txt new file mode 100644 index 0000000000..67ea2d4edb --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lcebr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lcebr %f0, %f9 +0xb3 0x03 0x00 0x09 + +# CHECK: lcebr %f0, %f15 +0xb3 0x03 0x00 0x0f + +# CHECK: lcebr %f15, %f0 +0xb3 0x03 0x00 0xf0 + +# CHECK: lcebr %f15, %f9 +0xb3 0x03 0x00 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-lcgfr.txt b/test/MC/Disassembler/SystemZ/insn-lcgfr.txt new file mode 100644 index 0000000000..c13739c58b --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lcgfr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lcgfr %r0, %r0 +0xb9 0x13 0x00 0x00 + +# CHECK: lcgfr %r0, %r15 +0xb9 0x13 0x00 0x0f + +# CHECK: lcgfr %r15, %r0 +0xb9 0x13 0x00 0xf0 + +# CHECK: lcgfr %r7, %r8 +0xb9 0x13 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-lcgr.txt b/test/MC/Disassembler/SystemZ/insn-lcgr.txt new file mode 100644 index 0000000000..540fa6e3b6 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lcgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lcgr %r0, %r0 +0xb9 0x03 0x00 0x00 + +# CHECK: lcgr %r0, %r15 +0xb9 0x03 0x00 0x0f + +# CHECK: lcgr %r15, %r0 +0xb9 0x03 0x00 0xf0 + +# CHECK: lcgr %r7, %r8 +0xb9 0x03 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-lcr.txt b/test/MC/Disassembler/SystemZ/insn-lcr.txt new file mode 100644 index 0000000000..1194ccd005 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lcr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lcr %r0, %r0 +0x13 0x00 + +# CHECK: lcr %r0, %r15 +0x13 0x0f + +# CHECK: lcr %r15, %r0 +0x13 0xf0 + +# CHECK: lcr %r7, %r8 +0x13 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-lcxbr.txt b/test/MC/Disassembler/SystemZ/insn-lcxbr.txt new file mode 100644 index 0000000000..31471ad9ef --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lcxbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lcxbr %f0, %f8 +0xb3 0x43 0x00 0x08 + +# CHECK: lcxbr %f0, %f13 +0xb3 0x43 0x00 0x0d + +# CHECK: lcxbr %f13, %f0 +0xb3 0x43 0x00 0xd0 + +# CHECK: lcxbr %f13, %f9 +0xb3 0x43 0x00 0xd9 diff --git a/test/MC/Disassembler/SystemZ/insn-ld.txt b/test/MC/Disassembler/SystemZ/insn-ld.txt new file mode 100644 index 0000000000..c9361c63d6 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ld.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ld %f0, 0 +0x68 0x00 0x00 0x00 + +# CHECK: ld %f0, 4095 +0x68 0x00 0x0f 0xff + +# CHECK: ld %f0, 0(%r1) +0x68 0x00 0x10 0x00 + +# CHECK: ld %f0, 0(%r15) +0x68 0x00 0xf0 0x00 + +# CHECK: ld %f0, 4095(%r1,%r15) +0x68 0x01 0xff 0xff + +# CHECK: ld %f0, 4095(%r15,%r1) +0x68 0x0f 0x1f 0xff + +# CHECK: ld %f15, 0 +0x68 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-ldeb.txt b/test/MC/Disassembler/SystemZ/insn-ldeb.txt new file mode 100644 index 0000000000..d45b01dcdc --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ldeb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ldeb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x04 + +# CHECK: ldeb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x04 + +# CHECK: ldeb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x04 + +# CHECK: ldeb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x04 + +# CHECK: ldeb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x04 + +# CHECK: ldeb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x04 + +# CHECK: ldeb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x04 diff --git a/test/MC/Disassembler/SystemZ/insn-ldebr.txt b/test/MC/Disassembler/SystemZ/insn-ldebr.txt new file mode 100644 index 0000000000..dc855187c3 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ldebr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ldebr %f0, %f15 +0xb3 0x04 0x00 0x0f + +# CHECK: ldebr %f7, %f8 +0xb3 0x04 0x00 0x78 + +# CHECK: ldebr %f15, %f0 +0xb3 0x04 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-ldgr.txt b/test/MC/Disassembler/SystemZ/insn-ldgr.txt new file mode 100644 index 0000000000..80d303bfc9 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ldgr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ldgr %f0, %r0 +0xb3 0xc1 0x00 0x00 + +# CHECK: ldgr %f0, %r15 +0xb3 0xc1 0x00 0x0f + +# CHECK: ldgr %f15, %r0 +0xb3 0xc1 0x00 0xf0 + +# CHECK: ldgr %f7, %r9 +0xb3 0xc1 0x00 0x79 + +# CHECK: ldgr %f15, %r15 +0xb3 0xc1 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-ldr.txt b/test/MC/Disassembler/SystemZ/insn-ldr.txt new file mode 100644 index 0000000000..25e061bf88 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ldr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ldr %f0, %f9 +0x28 0x09 + +# CHECK: ldr %f0, %f15 +0x28 0x0f + +# CHECK: ldr %f15, %f0 +0x28 0xf0 + +# CHECK: ldr %f15, %f9 +0x28 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-ldxbr.txt b/test/MC/Disassembler/SystemZ/insn-ldxbr.txt new file mode 100644 index 0000000000..9d438dcdc7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ldxbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ldxbr %f0, %f0 +0xb3 0x45 0x00 0x00 + +# CHECK: ldxbr %f0, %f13 +0xb3 0x45 0x00 0x0d + +# CHECK: ldxbr %f8, %f12 +0xb3 0x45 0x00 0x8c + +# CHECK: ldxbr %f13, %f0 +0xb3 0x45 0x00 0xd0 + +# CHECK: ldxbr %f13, %f13 +0xb3 0x45 0x00 0xdd diff --git a/test/MC/Disassembler/SystemZ/insn-ldy.txt b/test/MC/Disassembler/SystemZ/insn-ldy.txt new file mode 100644 index 0000000000..712aca0b70 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ldy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ldy %f0, -524288 +0xed 0x00 0x00 0x00 0x80 0x65 + +# CHECK: ldy %f0, -1 +0xed 0x00 0x0f 0xff 0xff 0x65 + +# CHECK: ldy %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x65 + +# CHECK: ldy %f0, 1 +0xed 0x00 0x00 0x01 0x00 0x65 + +# CHECK: ldy %f0, 524287 +0xed 0x00 0x0f 0xff 0x7f 0x65 + +# CHECK: ldy %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x65 + +# CHECK: ldy %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x65 + +# CHECK: ldy %f0, 524287(%r1,%r15) +0xed 0x01 0xff 0xff 0x7f 0x65 + +# CHECK: ldy %f0, 524287(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x7f 0x65 + +# CHECK: ldy %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x65 diff --git a/test/MC/Disassembler/SystemZ/insn-le.txt b/test/MC/Disassembler/SystemZ/insn-le.txt new file mode 100644 index 0000000000..2b11f001c8 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-le.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: le %f0, 0 +0x78 0x00 0x00 0x00 + +# CHECK: le %f0, 4095 +0x78 0x00 0x0f 0xff + +# CHECK: le %f0, 0(%r1) +0x78 0x00 0x10 0x00 + +# CHECK: le %f0, 0(%r15) +0x78 0x00 0xf0 0x00 + +# CHECK: le %f0, 4095(%r1,%r15) +0x78 0x01 0xff 0xff + +# CHECK: le %f0, 4095(%r15,%r1) +0x78 0x0f 0x1f 0xff + +# CHECK: le %f15, 0 +0x78 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-ledbr.txt b/test/MC/Disassembler/SystemZ/insn-ledbr.txt new file mode 100644 index 0000000000..5a7d41d302 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ledbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ledbr %f0, %f0 +0xb3 0x44 0x00 0x00 + +# CHECK: ledbr %f0, %f15 +0xb3 0x44 0x00 0x0f + +# CHECK: ledbr %f7, %f8 +0xb3 0x44 0x00 0x78 + +# CHECK: ledbr %f15, %f0 +0xb3 0x44 0x00 0xf0 + +# CHECK: ledbr %f15, %f15 +0xb3 0x44 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-ler.txt b/test/MC/Disassembler/SystemZ/insn-ler.txt new file mode 100644 index 0000000000..f18dc45713 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ler.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ler %f0, %f9 +0x38 0x09 + +# CHECK: ler %f0, %f15 +0x38 0x0f + +# CHECK: ler %f15, %f0 +0x38 0xf0 + +# CHECK: ler %f15, %f9 +0x38 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-lexbr.txt b/test/MC/Disassembler/SystemZ/insn-lexbr.txt new file mode 100644 index 0000000000..377a187a63 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lexbr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lexbr %f0, %f0 +0xb3 0x46 0x00 0x00 + +# CHECK: lexbr %f0, %f13 +0xb3 0x46 0x00 0x0d + +# CHECK: lexbr %f8, %f12 +0xb3 0x46 0x00 0x8c + +# CHECK: lexbr %f13, %f0 +0xb3 0x46 0x00 0xd0 + +# CHECK: lexbr %f13, %f13 +0xb3 0x46 0x00 0xdd diff --git a/test/MC/Disassembler/SystemZ/insn-ley.txt b/test/MC/Disassembler/SystemZ/insn-ley.txt new file mode 100644 index 0000000000..97a3b3882f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ley.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ley %f0, -524288 +0xed 0x00 0x00 0x00 0x80 0x64 + +# CHECK: ley %f0, -1 +0xed 0x00 0x0f 0xff 0xff 0x64 + +# CHECK: ley %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x64 + +# CHECK: ley %f0, 1 +0xed 0x00 0x00 0x01 0x00 0x64 + +# CHECK: ley %f0, 524287 +0xed 0x00 0x0f 0xff 0x7f 0x64 + +# CHECK: ley %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x64 + +# CHECK: ley %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x64 + +# CHECK: ley %f0, 524287(%r1,%r15) +0xed 0x01 0xff 0xff 0x7f 0x64 + +# CHECK: ley %f0, 524287(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x7f 0x64 + +# CHECK: ley %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x64 diff --git a/test/MC/Disassembler/SystemZ/insn-lg.txt b/test/MC/Disassembler/SystemZ/insn-lg.txt new file mode 100644 index 0000000000..956495f48c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x04 + +# CHECK: lg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x04 + +# CHECK: lg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x04 + +# CHECK: lg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x04 + +# CHECK: lg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x04 + +# CHECK: lg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x04 + +# CHECK: lg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x04 + +# CHECK: lg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x04 + +# CHECK: lg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x04 + +# CHECK: lg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x04 diff --git a/test/MC/Disassembler/SystemZ/insn-lgb.txt b/test/MC/Disassembler/SystemZ/insn-lgb.txt new file mode 100644 index 0000000000..fa21f324b3 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgb.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgb %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x77 + +# CHECK: lgb %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x77 + +# CHECK: lgb %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x77 + +# CHECK: lgb %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x77 + +# CHECK: lgb %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x77 + +# CHECK: lgb %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x77 + +# CHECK: lgb %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x77 + +# CHECK: lgb %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x77 + +# CHECK: lgb %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x77 + +# CHECK: lgb %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x77 diff --git a/test/MC/Disassembler/SystemZ/insn-lgbr.txt b/test/MC/Disassembler/SystemZ/insn-lgbr.txt new file mode 100644 index 0000000000..1f1d28d84a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgbr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgbr %r0, %r15 +0xb9 0x06 0x00 0x0f + +# CHECK: lgbr %r7, %r8 +0xb9 0x06 0x00 0x78 + +# CHECK: lgbr %r15, %r0 +0xb9 0x06 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-lgdr.txt b/test/MC/Disassembler/SystemZ/insn-lgdr.txt new file mode 100644 index 0000000000..a3059757aa --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgdr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgdr %r0, %f0 +0xb3 0xcd 0x00 0x00 + +# CHECK: lgdr %r0, %f15 +0xb3 0xcd 0x00 0x0f + +# CHECK: lgdr %r15, %f0 +0xb3 0xcd 0x00 0xf0 + +# CHECK: lgdr %r8, %f8 +0xb3 0xcd 0x00 0x88 + +# CHECK: lgdr %r15, %f15 +0xb3 0xcd 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-lgf.txt b/test/MC/Disassembler/SystemZ/insn-lgf.txt new file mode 100644 index 0000000000..9bc22998a6 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x14 + +# CHECK: lgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x14 + +# CHECK: lgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x14 + +# CHECK: lgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x14 + +# CHECK: lgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x14 + +# CHECK: lgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x14 + +# CHECK: lgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x14 + +# CHECK: lgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x14 + +# CHECK: lgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x14 + +# CHECK: lgf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x14 diff --git a/test/MC/Disassembler/SystemZ/insn-lgfi.txt b/test/MC/Disassembler/SystemZ/insn-lgfi.txt new file mode 100644 index 0000000000..736a8045c7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgfi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgfi %r0, -2147483648 +0xc0 0x01 0x80 0x00 0x00 0x00 + +# CHECK: lgfi %r0, -1 +0xc0 0x01 0xff 0xff 0xff 0xff + +# CHECK: lgfi %r0, 0 +0xc0 0x01 0x00 0x00 0x00 0x00 + +# CHECK: lgfi %r0, 1 +0xc0 0x01 0x00 0x00 0x00 0x01 + +# CHECK: lgfi %r0, 2147483647 +0xc0 0x01 0x7f 0xff 0xff 0xff + +# CHECK: lgfi %r15, 0 +0xc0 0xf1 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-lgfr.txt b/test/MC/Disassembler/SystemZ/insn-lgfr.txt new file mode 100644 index 0000000000..d57a9db84a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgfr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgfr %r0, %r15 +0xb9 0x14 0x00 0x0f + +# CHECK: lgfr %r7, %r8 +0xb9 0x14 0x00 0x78 + +# CHECK: lgfr %r15, %r0 +0xb9 0x14 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-lgfrl.txt b/test/MC/Disassembler/SystemZ/insn-lgfrl.txt new file mode 100644 index 0000000000..fecd3458b7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgfrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgfrl %r0, 0x0 +0xc4 0x0c 0x00 0x00 0x00 0x00 + +# CHECK: lgfrl %r15, 0x6 +0xc4 0xfc 0x00 0x00 0x00 0x00 + +# CHECK: lgfrl %r0, 0xa +0xc4 0x0c 0xff 0xff 0xff 0xff + +# CHECK: lgfrl %r15, 0x10 +0xc4 0xfc 0xff 0xff 0xff 0xff + +# CHECK: lgfrl %r0, 0xffffffff00000018 +0xc4 0x0c 0x80 0x00 0x00 0x00 + +# CHECK: lgfrl %r15, 0xffffffff0000001e +0xc4 0xfc 0x80 0x00 0x00 0x00 + +# CHECK: lgfrl %r0, 0x100000022 +0xc4 0x0c 0x7f 0xff 0xff 0xff + +# CHECK: lgfrl %r15, 0x100000028 +0xc4 0xfc 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-lgh.txt b/test/MC/Disassembler/SystemZ/insn-lgh.txt new file mode 100644 index 0000000000..a3ea87fcd2 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgh.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x15 + +# CHECK: lgh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x15 + +# CHECK: lgh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x15 + +# CHECK: lgh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x15 + +# CHECK: lgh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x15 + +# CHECK: lgh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x15 + +# CHECK: lgh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x15 + +# CHECK: lgh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x15 + +# CHECK: lgh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x15 + +# CHECK: lgh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x15 diff --git a/test/MC/Disassembler/SystemZ/insn-lghi.txt b/test/MC/Disassembler/SystemZ/insn-lghi.txt new file mode 100644 index 0000000000..ad8366f95c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lghi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lghi %r0, -32768 +0xa7 0x09 0x80 0x00 + +# CHECK: lghi %r0, -1 +0xa7 0x09 0xff 0xff + +# CHECK: lghi %r0, 0 +0xa7 0x09 0x00 0x00 + +# CHECK: lghi %r0, 1 +0xa7 0x09 0x00 0x01 + +# CHECK: lghi %r0, 32767 +0xa7 0x09 0x7f 0xff + +# CHECK: lghi %r15, 0 +0xa7 0xf9 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-lghr.txt b/test/MC/Disassembler/SystemZ/insn-lghr.txt new file mode 100644 index 0000000000..d7e9e461fd --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lghr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lghr %r0, %r15 +0xb9 0x07 0x00 0x0f + +# CHECK: lghr %r7, %r8 +0xb9 0x07 0x00 0x78 + +# CHECK: lghr %r15, %r0 +0xb9 0x07 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-lghrl.txt b/test/MC/Disassembler/SystemZ/insn-lghrl.txt new file mode 100644 index 0000000000..cfa9622c8a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lghrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lghrl %r0, 0x0 +0xc4 0x04 0x00 0x00 0x00 0x00 + +# CHECK: lghrl %r15, 0x6 +0xc4 0xf4 0x00 0x00 0x00 0x00 + +# CHECK: lghrl %r0, 0xa +0xc4 0x04 0xff 0xff 0xff 0xff + +# CHECK: lghrl %r15, 0x10 +0xc4 0xf4 0xff 0xff 0xff 0xff + +# CHECK: lghrl %r0, 0xffffffff00000018 +0xc4 0x04 0x80 0x00 0x00 0x00 + +# CHECK: lghrl %r15, 0xffffffff0000001e +0xc4 0xf4 0x80 0x00 0x00 0x00 + +# CHECK: lghrl %r0, 0x100000022 +0xc4 0x04 0x7f 0xff 0xff 0xff + +# CHECK: lghrl %r15, 0x100000028 +0xc4 0xf4 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-lgr.txt b/test/MC/Disassembler/SystemZ/insn-lgr.txt new file mode 100644 index 0000000000..23998e62af --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgr %r0, %r9 +0xb9 0x04 0x00 0x09 + +# CHECK: lgr %r0, %r15 +0xb9 0x04 0x00 0x0f + +# CHECK: lgr %r15, %r0 +0xb9 0x04 0x00 0xf0 + +# CHECK: lgr %r15, %r9 +0xb9 0x04 0x00 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-lgrl.txt b/test/MC/Disassembler/SystemZ/insn-lgrl.txt new file mode 100644 index 0000000000..785aa97f59 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lgrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lgrl %r0, 0x0 +0xc4 0x08 0x00 0x00 0x00 0x00 + +# CHECK: lgrl %r15, 0x6 +0xc4 0xf8 0x00 0x00 0x00 0x00 + +# CHECK: lgrl %r0, 0xa +0xc4 0x08 0xff 0xff 0xff 0xff + +# CHECK: lgrl %r15, 0x10 +0xc4 0xf8 0xff 0xff 0xff 0xff + +# CHECK: lgrl %r0, 0xffffffff00000018 +0xc4 0x08 0x80 0x00 0x00 0x00 + +# CHECK: lgrl %r15, 0xffffffff0000001e +0xc4 0xf8 0x80 0x00 0x00 0x00 + +# CHECK: lgrl %r0, 0x100000022 +0xc4 0x08 0x7f 0xff 0xff 0xff + +# CHECK: lgrl %r15, 0x100000028 +0xc4 0xf8 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-lh.txt b/test/MC/Disassembler/SystemZ/insn-lh.txt new file mode 100644 index 0000000000..700b942619 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lh.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lh %r0, 0 +0x48 0x00 0x00 0x00 + +# CHECK: lh %r0, 4095 +0x48 0x00 0x0f 0xff + +# CHECK: lh %r0, 0(%r1) +0x48 0x00 0x10 0x00 + +# CHECK: lh %r0, 0(%r15) +0x48 0x00 0xf0 0x00 + +# CHECK: lh %r0, 4095(%r1,%r15) +0x48 0x01 0xff 0xff + +# CHECK: lh %r0, 4095(%r15,%r1) +0x48 0x0f 0x1f 0xff + +# CHECK: lh %r15, 0 +0x48 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-lhi.txt b/test/MC/Disassembler/SystemZ/insn-lhi.txt new file mode 100644 index 0000000000..fbb10f5497 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lhi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lhi %r0, -32768 +0xa7 0x08 0x80 0x00 + +# CHECK: lhi %r0, -1 +0xa7 0x08 0xff 0xff + +# CHECK: lhi %r0, 0 +0xa7 0x08 0x00 0x00 + +# CHECK: lhi %r0, 1 +0xa7 0x08 0x00 0x01 + +# CHECK: lhi %r0, 32767 +0xa7 0x08 0x7f 0xff + +# CHECK: lhi %r15, 0 +0xa7 0xf8 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-lhr.txt b/test/MC/Disassembler/SystemZ/insn-lhr.txt new file mode 100644 index 0000000000..24a38a5f73 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lhr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lhr %r0, %r15 +0xb9 0x27 0x00 0x0f + +# CHECK: lhr %r7, %r8 +0xb9 0x27 0x00 0x78 + +# CHECK: lhr %r15, %r0 +0xb9 0x27 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-lhrl.txt b/test/MC/Disassembler/SystemZ/insn-lhrl.txt new file mode 100644 index 0000000000..1728e054e1 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lhrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lhrl %r0, 0x0 +0xc4 0x05 0x00 0x00 0x00 0x00 + +# CHECK: lhrl %r15, 0x6 +0xc4 0xf5 0x00 0x00 0x00 0x00 + +# CHECK: lhrl %r0, 0xa +0xc4 0x05 0xff 0xff 0xff 0xff + +# CHECK: lhrl %r15, 0x10 +0xc4 0xf5 0xff 0xff 0xff 0xff + +# CHECK: lhrl %r0, 0xffffffff00000018 +0xc4 0x05 0x80 0x00 0x00 0x00 + +# CHECK: lhrl %r15, 0xffffffff0000001e +0xc4 0xf5 0x80 0x00 0x00 0x00 + +# CHECK: lhrl %r0, 0x100000022 +0xc4 0x05 0x7f 0xff 0xff 0xff + +# CHECK: lhrl %r15, 0x100000028 +0xc4 0xf5 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-lhy.txt b/test/MC/Disassembler/SystemZ/insn-lhy.txt new file mode 100644 index 0000000000..679353e765 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lhy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lhy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x78 + +# CHECK: lhy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x78 + +# CHECK: lhy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x78 + +# CHECK: lhy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x78 + +# CHECK: lhy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x78 + +# CHECK: lhy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x78 + +# CHECK: lhy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x78 + +# CHECK: lhy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x78 + +# CHECK: lhy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x78 + +# CHECK: lhy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-llc.txt b/test/MC/Disassembler/SystemZ/insn-llc.txt new file mode 100644 index 0000000000..895cef22c5 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llc.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x94 + +# CHECK: llc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x94 + +# CHECK: llc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x94 + +# CHECK: llc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x94 + +# CHECK: llc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x94 + +# CHECK: llc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x94 + +# CHECK: llc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x94 + +# CHECK: llc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x94 + +# CHECK: llc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x94 + +# CHECK: llc %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x94 diff --git a/test/MC/Disassembler/SystemZ/insn-llcr.txt b/test/MC/Disassembler/SystemZ/insn-llcr.txt new file mode 100644 index 0000000000..cc67524366 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llcr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llcr %r0, %r15 +0xb9 0x94 0x00 0x0f + +# CHECK: llcr %r7, %r8 +0xb9 0x94 0x00 0x78 + +# CHECK: llcr %r15, %r0 +0xb9 0x94 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-llgc.txt b/test/MC/Disassembler/SystemZ/insn-llgc.txt new file mode 100644 index 0000000000..eeea56ac2e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llgc.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llgc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x90 + +# CHECK: llgc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x90 + +# CHECK: llgc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x90 + +# CHECK: llgc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x90 + +# CHECK: llgc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x90 + +# CHECK: llgc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x90 + +# CHECK: llgc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x90 + +# CHECK: llgc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x90 + +# CHECK: llgc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x90 + +# CHECK: llgc %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x90 diff --git a/test/MC/Disassembler/SystemZ/insn-llgcr.txt b/test/MC/Disassembler/SystemZ/insn-llgcr.txt new file mode 100644 index 0000000000..8c0b6df54e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llgcr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llgcr %r0, %r15 +0xb9 0x84 0x00 0x0f + +# CHECK: llgcr %r7, %r8 +0xb9 0x84 0x00 0x78 + +# CHECK: llgcr %r15, %r0 +0xb9 0x84 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-llgf.txt b/test/MC/Disassembler/SystemZ/insn-llgf.txt new file mode 100644 index 0000000000..f97baa9bc7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llgf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x16 + +# CHECK: llgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x16 + +# CHECK: llgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x16 + +# CHECK: llgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x16 + +# CHECK: llgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x16 + +# CHECK: llgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x16 + +# CHECK: llgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x16 + +# CHECK: llgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x16 + +# CHECK: llgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x16 + +# CHECK: llgf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x16 diff --git a/test/MC/Disassembler/SystemZ/insn-llgfr.txt b/test/MC/Disassembler/SystemZ/insn-llgfr.txt new file mode 100644 index 0000000000..c68a6c9013 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llgfr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llgfr %r0, %r15 +0xb9 0x16 0x00 0x0f + +# CHECK: llgfr %r7, %r8 +0xb9 0x16 0x00 0x78 + +# CHECK: llgfr %r15, %r0 +0xb9 0x16 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-llgfrl.txt b/test/MC/Disassembler/SystemZ/insn-llgfrl.txt new file mode 100644 index 0000000000..908ae6d738 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llgfrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llgfrl %r0, 0x0 +0xc4 0x0e 0x00 0x00 0x00 0x00 + +# CHECK: llgfrl %r15, 0x6 +0xc4 0xfe 0x00 0x00 0x00 0x00 + +# CHECK: llgfrl %r0, 0xa +0xc4 0x0e 0xff 0xff 0xff 0xff + +# CHECK: llgfrl %r15, 0x10 +0xc4 0xfe 0xff 0xff 0xff 0xff + +# CHECK: llgfrl %r0, 0xffffffff00000018 +0xc4 0x0e 0x80 0x00 0x00 0x00 + +# CHECK: llgfrl %r15, 0xffffffff0000001e +0xc4 0xfe 0x80 0x00 0x00 0x00 + +# CHECK: llgfrl %r0, 0x100000022 +0xc4 0x0e 0x7f 0xff 0xff 0xff + +# CHECK: llgfrl %r15, 0x100000028 +0xc4 0xfe 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-llgh.txt b/test/MC/Disassembler/SystemZ/insn-llgh.txt new file mode 100644 index 0000000000..7e64a55207 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llgh.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llgh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x91 + +# CHECK: llgh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x91 + +# CHECK: llgh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x91 + +# CHECK: llgh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x91 + +# CHECK: llgh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x91 + +# CHECK: llgh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x91 + +# CHECK: llgh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x91 + +# CHECK: llgh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x91 + +# CHECK: llgh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x91 + +# CHECK: llgh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x91 diff --git a/test/MC/Disassembler/SystemZ/insn-llghr.txt b/test/MC/Disassembler/SystemZ/insn-llghr.txt new file mode 100644 index 0000000000..ceed654b61 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llghr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llghr %r0, %r15 +0xb9 0x85 0x00 0x0f + +# CHECK: llghr %r7, %r8 +0xb9 0x85 0x00 0x78 + +# CHECK: llghr %r15, %r0 +0xb9 0x85 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-llghrl.txt b/test/MC/Disassembler/SystemZ/insn-llghrl.txt new file mode 100644 index 0000000000..0960afb706 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llghrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llghrl %r0, 0x0 +0xc4 0x06 0x00 0x00 0x00 0x00 + +# CHECK: llghrl %r15, 0x6 +0xc4 0xf6 0x00 0x00 0x00 0x00 + +# CHECK: llghrl %r0, 0xa +0xc4 0x06 0xff 0xff 0xff 0xff + +# CHECK: llghrl %r15, 0x10 +0xc4 0xf6 0xff 0xff 0xff 0xff + +# CHECK: llghrl %r0, 0xffffffff00000018 +0xc4 0x06 0x80 0x00 0x00 0x00 + +# CHECK: llghrl %r15, 0xffffffff0000001e +0xc4 0xf6 0x80 0x00 0x00 0x00 + +# CHECK: llghrl %r0, 0x100000022 +0xc4 0x06 0x7f 0xff 0xff 0xff + +# CHECK: llghrl %r15, 0x100000028 +0xc4 0xf6 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-llh.txt b/test/MC/Disassembler/SystemZ/insn-llh.txt new file mode 100644 index 0000000000..6b660cb900 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llh.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x95 + +# CHECK: llh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x95 + +# CHECK: llh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x95 + +# CHECK: llh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x95 + +# CHECK: llh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x95 + +# CHECK: llh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x95 + +# CHECK: llh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x95 + +# CHECK: llh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x95 + +# CHECK: llh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x95 + +# CHECK: llh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x95 diff --git a/test/MC/Disassembler/SystemZ/insn-llhr.txt b/test/MC/Disassembler/SystemZ/insn-llhr.txt new file mode 100644 index 0000000000..c01eac25fe --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llhr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llhr %r0, %r15 +0xb9 0x95 0x00 0x0f + +# CHECK: llhr %r7, %r8 +0xb9 0x95 0x00 0x78 + +# CHECK: llhr %r15, %r0 +0xb9 0x95 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-llhrl.txt b/test/MC/Disassembler/SystemZ/insn-llhrl.txt new file mode 100644 index 0000000000..a8000ca233 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llhrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llhrl %r0, 0x0 +0xc4 0x02 0x00 0x00 0x00 0x00 + +# CHECK: llhrl %r15, 0x6 +0xc4 0xf2 0x00 0x00 0x00 0x00 + +# CHECK: llhrl %r0, 0xa +0xc4 0x02 0xff 0xff 0xff 0xff + +# CHECK: llhrl %r15, 0x10 +0xc4 0xf2 0xff 0xff 0xff 0xff + +# CHECK: llhrl %r0, 0xffffffff00000018 +0xc4 0x02 0x80 0x00 0x00 0x00 + +# CHECK: llhrl %r15, 0xffffffff0000001e +0xc4 0xf2 0x80 0x00 0x00 0x00 + +# CHECK: llhrl %r0, 0x100000022 +0xc4 0x02 0x7f 0xff 0xff 0xff + +# CHECK: llhrl %r15, 0x100000028 +0xc4 0xf2 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-llihf.txt b/test/MC/Disassembler/SystemZ/insn-llihf.txt new file mode 100644 index 0000000000..64f58d3bd6 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llihf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llihf %r0, 0 +0xc0 0x0e 0x00 0x00 0x00 0x00 + +# CHECK: llihf %r0, 4294967295 +0xc0 0x0e 0xff 0xff 0xff 0xff + +# CHECK: llihf %r15, 0 +0xc0 0xfe 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-llihh.txt b/test/MC/Disassembler/SystemZ/insn-llihh.txt new file mode 100644 index 0000000000..610ce8f67f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llihh.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llihh %r0, 0 +0xa5 0x0c 0x00 0x00 + +# CHECK: llihh %r0, 32768 +0xa5 0x0c 0x80 0x00 + +# CHECK: llihh %r0, 65535 +0xa5 0x0c 0xff 0xff + +# CHECK: llihh %r15, 0 +0xa5 0xfc 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-llihl.txt b/test/MC/Disassembler/SystemZ/insn-llihl.txt new file mode 100644 index 0000000000..8de06f98fb --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llihl.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llihl %r0, 0 +0xa5 0x0d 0x00 0x00 + +# CHECK: llihl %r0, 32768 +0xa5 0x0d 0x80 0x00 + +# CHECK: llihl %r0, 65535 +0xa5 0x0d 0xff 0xff + +# CHECK: llihl %r15, 0 +0xa5 0xfd 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-llilf.txt b/test/MC/Disassembler/SystemZ/insn-llilf.txt new file mode 100644 index 0000000000..008827ea40 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llilf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llilf %r0, 0 +0xc0 0x0f 0x00 0x00 0x00 0x00 + +# CHECK: llilf %r0, 4294967295 +0xc0 0x0f 0xff 0xff 0xff 0xff + +# CHECK: llilf %r15, 0 +0xc0 0xff 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-llilh.txt b/test/MC/Disassembler/SystemZ/insn-llilh.txt new file mode 100644 index 0000000000..5b9336ad8b --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llilh.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llilh %r0, 0 +0xa5 0x0e 0x00 0x00 + +# CHECK: llilh %r0, 32768 +0xa5 0x0e 0x80 0x00 + +# CHECK: llilh %r0, 65535 +0xa5 0x0e 0xff 0xff + +# CHECK: llilh %r15, 0 +0xa5 0xfe 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-llill.txt b/test/MC/Disassembler/SystemZ/insn-llill.txt new file mode 100644 index 0000000000..65c27dd48c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-llill.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: llill %r0, 0 +0xa5 0x0f 0x00 0x00 + +# CHECK: llill %r0, 32768 +0xa5 0x0f 0x80 0x00 + +# CHECK: llill %r0, 65535 +0xa5 0x0f 0xff 0xff + +# CHECK: llill %r15, 0 +0xa5 0xff 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-lmg.txt b/test/MC/Disassembler/SystemZ/insn-lmg.txt new file mode 100644 index 0000000000..2a7599608c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lmg.txt @@ -0,0 +1,39 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lmg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x04 + +# CHECK: lmg %r0, %r15, 0 +0xeb 0x0f 0x00 0x00 0x00 0x04 + +# CHECK: lmg %r14, %r15, 0 +0xeb 0xef 0x00 0x00 0x00 0x04 + +# CHECK: lmg %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0x04 + +# CHECK: lmg %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x04 + +# CHECK: lmg %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x04 + +# CHECK: lmg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x04 + +# CHECK: lmg %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x04 + +# CHECK: lmg %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x04 + +# CHECK: lmg %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x04 + +# CHECK: lmg %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x04 + +# CHECK: lmg %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x04 + +# CHECK: lmg %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x04 diff --git a/test/MC/Disassembler/SystemZ/insn-lndbr.txt b/test/MC/Disassembler/SystemZ/insn-lndbr.txt new file mode 100644 index 0000000000..d3d727882e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lndbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lndbr %f0, %f9 +0xb3 0x11 0x00 0x09 + +# CHECK: lndbr %f0, %f15 +0xb3 0x11 0x00 0x0f + +# CHECK: lndbr %f15, %f0 +0xb3 0x11 0x00 0xf0 + +# CHECK: lndbr %f15, %f9 +0xb3 0x11 0x00 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-lnebr.txt b/test/MC/Disassembler/SystemZ/insn-lnebr.txt new file mode 100644 index 0000000000..ee3925c83f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lnebr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lnebr %f0, %f9 +0xb3 0x01 0x00 0x09 + +# CHECK: lnebr %f0, %f15 +0xb3 0x01 0x00 0x0f + +# CHECK: lnebr %f15, %f0 +0xb3 0x01 0x00 0xf0 + +# CHECK: lnebr %f15, %f9 +0xb3 0x01 0x00 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-lnxbr.txt b/test/MC/Disassembler/SystemZ/insn-lnxbr.txt new file mode 100644 index 0000000000..41f1c03eca --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lnxbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lnxbr %f0, %f8 +0xb3 0x41 0x00 0x08 + +# CHECK: lnxbr %f0, %f13 +0xb3 0x41 0x00 0x0d + +# CHECK: lnxbr %f13, %f0 +0xb3 0x41 0x00 0xd0 + +# CHECK: lnxbr %f13, %f9 +0xb3 0x41 0x00 0xd9 diff --git a/test/MC/Disassembler/SystemZ/insn-lpdbr.txt b/test/MC/Disassembler/SystemZ/insn-lpdbr.txt new file mode 100644 index 0000000000..1c1f05adf5 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lpdbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lpdbr %f0, %f9 +0xb3 0x10 0x00 0x09 + +# CHECK: lpdbr %f0, %f15 +0xb3 0x10 0x00 0x0f + +# CHECK: lpdbr %f15, %f0 +0xb3 0x10 0x00 0xf0 + +# CHECK: lpdbr %f15, %f9 +0xb3 0x10 0x00 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-lpebr.txt b/test/MC/Disassembler/SystemZ/insn-lpebr.txt new file mode 100644 index 0000000000..ac324fef64 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lpebr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lpebr %f0, %f9 +0xb3 0x00 0x00 0x09 + +# CHECK: lpebr %f0, %f15 +0xb3 0x00 0x00 0x0f + +# CHECK: lpebr %f15, %f0 +0xb3 0x00 0x00 0xf0 + +# CHECK: lpebr %f15, %f9 +0xb3 0x00 0x00 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-lpxbr.txt b/test/MC/Disassembler/SystemZ/insn-lpxbr.txt new file mode 100644 index 0000000000..384e1d9301 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lpxbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lpxbr %f0, %f8 +0xb3 0x40 0x00 0x08 + +# CHECK: lpxbr %f0, %f13 +0xb3 0x40 0x00 0x0d + +# CHECK: lpxbr %f13, %f0 +0xb3 0x40 0x00 0xd0 + +# CHECK: lpxbr %f13, %f9 +0xb3 0x40 0x00 0xd9 diff --git a/test/MC/Disassembler/SystemZ/insn-lr.txt b/test/MC/Disassembler/SystemZ/insn-lr.txt new file mode 100644 index 0000000000..8e89d41975 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lr %r0, %r9 +0x18 0x09 + +# CHECK: lr %r0, %r15 +0x18 0x0f + +# CHECK: lr %r15, %r0 +0x18 0xf0 + +# CHECK: lr %r15, %r9 +0x18 0xf9 diff --git a/test/MC/Disassembler/SystemZ/insn-lrl.txt b/test/MC/Disassembler/SystemZ/insn-lrl.txt new file mode 100644 index 0000000000..b5ca391fe7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lrl %r0, 0x0 +0xc4 0x0d 0x00 0x00 0x00 0x00 + +# CHECK: lrl %r15, 0x6 +0xc4 0xfd 0x00 0x00 0x00 0x00 + +# CHECK: lrl %r0, 0xa +0xc4 0x0d 0xff 0xff 0xff 0xff + +# CHECK: lrl %r15, 0x10 +0xc4 0xfd 0xff 0xff 0xff 0xff + +# CHECK: lrl %r0, 0xffffffff00000018 +0xc4 0x0d 0x80 0x00 0x00 0x00 + +# CHECK: lrl %r15, 0xffffffff0000001e +0xc4 0xfd 0x80 0x00 0x00 0x00 + +# CHECK: lrl %r0, 0x100000022 +0xc4 0x0d 0x7f 0xff 0xff 0xff + +# CHECK: lrl %r15, 0x100000028 +0xc4 0xfd 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-lrv.txt b/test/MC/Disassembler/SystemZ/insn-lrv.txt new file mode 100644 index 0000000000..30e497675a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lrv.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lrv %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x1e + +# CHECK: lrv %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x1e + +# CHECK: lrv %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x1e + +# CHECK: lrv %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x1e + +# CHECK: lrv %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x1e + +# CHECK: lrv %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x1e + +# CHECK: lrv %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x1e + +# CHECK: lrv %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x1e + +# CHECK: lrv %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x1e + +# CHECK: lrv %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x1e diff --git a/test/MC/Disassembler/SystemZ/insn-lrvg.txt b/test/MC/Disassembler/SystemZ/insn-lrvg.txt new file mode 100644 index 0000000000..86b09136d3 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lrvg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lrvg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x0f + +# CHECK: lrvg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x0f + +# CHECK: lrvg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x0f + +# CHECK: lrvg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x0f + +# CHECK: lrvg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x0f + +# CHECK: lrvg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x0f + +# CHECK: lrvg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x0f + +# CHECK: lrvg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x0f + +# CHECK: lrvg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x0f + +# CHECK: lrvg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x0f diff --git a/test/MC/Disassembler/SystemZ/insn-lrvgr.txt b/test/MC/Disassembler/SystemZ/insn-lrvgr.txt new file mode 100644 index 0000000000..eda1b3c62e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lrvgr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lrvgr %r0, %r0 +0xb9 0x0f 0x00 0x00 + +# CHECK: lrvgr %r0, %r15 +0xb9 0x0f 0x00 0x0f + +# CHECK: lrvgr %r15, %r0 +0xb9 0x0f 0x00 0xf0 + +# CHECK: lrvgr %r7, %r8 +0xb9 0x0f 0x00 0x78 + +# CHECK: lrvgr %r15, %r15 +0xb9 0x0f 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-lrvr.txt b/test/MC/Disassembler/SystemZ/insn-lrvr.txt new file mode 100644 index 0000000000..fc8a8e6012 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lrvr.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lrvr %r0, %r0 +0xb9 0x1f 0x00 0x00 + +# CHECK: lrvr %r0, %r15 +0xb9 0x1f 0x00 0x0f + +# CHECK: lrvr %r15, %r0 +0xb9 0x1f 0x00 0xf0 + +# CHECK: lrvr %r7, %r8 +0xb9 0x1f 0x00 0x78 + +# CHECK: lrvr %r15, %r15 +0xb9 0x1f 0x00 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-lxr.txt b/test/MC/Disassembler/SystemZ/insn-lxr.txt new file mode 100644 index 0000000000..bd989cd6b0 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lxr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lxr %f0, %f8 +0xb3 0x65 0x00 0x08 + +# CHECK: lxr %f0, %f13 +0xb3 0x65 0x00 0x0d + +# CHECK: lxr %f13, %f0 +0xb3 0x65 0x00 0xd0 + +# CHECK: lxr %f13, %f9 +0xb3 0x65 0x00 0xd9 diff --git a/test/MC/Disassembler/SystemZ/insn-ly.txt b/test/MC/Disassembler/SystemZ/insn-ly.txt new file mode 100644 index 0000000000..b9112d72a9 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ly.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ly %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x58 + +# CHECK: ly %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x58 + +# CHECK: ly %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x58 + +# CHECK: ly %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x58 + +# CHECK: ly %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x58 + +# CHECK: ly %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x58 + +# CHECK: ly %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x58 + +# CHECK: ly %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x58 + +# CHECK: ly %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x58 + +# CHECK: ly %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x58 diff --git a/test/MC/Disassembler/SystemZ/insn-lzdr.txt b/test/MC/Disassembler/SystemZ/insn-lzdr.txt new file mode 100644 index 0000000000..5e64f355b8 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lzdr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lzdr %f0 +0xb3 0x75 0x00 0x00 + +# CHECK: lzdr %f7 +0xb3 0x75 0x00 0x70 + +# CHECK: lzdr %f15 +0xb3 0x75 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-lzer.txt b/test/MC/Disassembler/SystemZ/insn-lzer.txt new file mode 100644 index 0000000000..f86cb2efe3 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lzer.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lzer %f0 +0xb3 0x74 0x00 0x00 + +# CHECK: lzer %f7 +0xb3 0x74 0x00 0x70 + +# CHECK: lzer %f15 +0xb3 0x74 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-lzxr.txt b/test/MC/Disassembler/SystemZ/insn-lzxr.txt new file mode 100644 index 0000000000..f2e64445df --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-lzxr.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: lzxr %f0 +0xb3 0x76 0x00 0x00 + +# CHECK: lzxr %f8 +0xb3 0x76 0x00 0x80 + +# CHECK: lzxr %f13 +0xb3 0x76 0x00 0xd0 diff --git a/test/MC/Disassembler/SystemZ/insn-madb.txt b/test/MC/Disassembler/SystemZ/insn-madb.txt new file mode 100644 index 0000000000..bbc8e5ec94 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-madb.txt @@ -0,0 +1,27 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: madb %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x1e + +# CHECK: madb %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x1e + +# CHECK: madb %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x1e + +# CHECK: madb %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x1e + +# CHECK: madb %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x1e + +# CHECK: madb %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x1e + +# CHECK: madb %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x1e + +# CHECK: madb %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x1e + +# CHECK: madb %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x1e diff --git a/test/MC/Disassembler/SystemZ/insn-madbr.txt b/test/MC/Disassembler/SystemZ/insn-madbr.txt new file mode 100644 index 0000000000..44c80acfff --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-madbr.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: madbr %f0, %f0, %f0 +0xb3 0x1e 0x00 0x00 + +# CHECK: madbr %f0, %f0, %f15 +0xb3 0x1e 0x00 0x0f + +# CHECK: madbr %f0, %f15, %f0 +0xb3 0x1e 0x00 0xf0 + +# CHECK: madbr %f15, %f0, %f0 +0xb3 0x1e 0xf0 0x00 + +# CHECK: madbr %f7, %f8, %f9 +0xb3 0x1e 0x70 0x89 + +# CHECK: madbr %f15, %f15, %f15 +0xb3 0x1e 0xf0 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-maeb.txt b/test/MC/Disassembler/SystemZ/insn-maeb.txt new file mode 100644 index 0000000000..3da44d3399 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-maeb.txt @@ -0,0 +1,27 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: maeb %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x0e + +# CHECK: maeb %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x0e + +# CHECK: maeb %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x0e + +# CHECK: maeb %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x0e + +# CHECK: maeb %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x0e + +# CHECK: maeb %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x0e + +# CHECK: maeb %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x0e + +# CHECK: maeb %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x0e + +# CHECK: maeb %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x0e diff --git a/test/MC/Disassembler/SystemZ/insn-maebr.txt b/test/MC/Disassembler/SystemZ/insn-maebr.txt new file mode 100644 index 0000000000..614c9ac26e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-maebr.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: maebr %f0, %f0, %f0 +0xb3 0x0e 0x00 0x00 + +# CHECK: maebr %f0, %f0, %f15 +0xb3 0x0e 0x00 0x0f + +# CHECK: maebr %f0, %f15, %f0 +0xb3 0x0e 0x00 0xf0 + +# CHECK: maebr %f15, %f0, %f0 +0xb3 0x0e 0xf0 0x00 + +# CHECK: maebr %f7, %f8, %f9 +0xb3 0x0e 0x70 0x89 + +# CHECK: maebr %f15, %f15, %f15 +0xb3 0x0e 0xf0 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-mdb.txt b/test/MC/Disassembler/SystemZ/insn-mdb.txt new file mode 100644 index 0000000000..69f030af9b --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mdb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mdb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x1c + +# CHECK: mdb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x1c + +# CHECK: mdb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x1c + +# CHECK: mdb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x1c + +# CHECK: mdb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x1c + +# CHECK: mdb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x1c + +# CHECK: mdb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x1c diff --git a/test/MC/Disassembler/SystemZ/insn-mdbr.txt b/test/MC/Disassembler/SystemZ/insn-mdbr.txt new file mode 100644 index 0000000000..e5cef83df5 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mdbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mdbr %f0, %f0 +0xb3 0x1c 0x00 0x00 + +# CHECK: mdbr %f0, %f15 +0xb3 0x1c 0x00 0x0f + +# CHECK: mdbr %f7, %f8 +0xb3 0x1c 0x00 0x78 + +# CHECK: mdbr %f15, %f0 +0xb3 0x1c 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-mdeb.txt b/test/MC/Disassembler/SystemZ/insn-mdeb.txt new file mode 100644 index 0000000000..074ca7f285 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mdeb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mdeb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x0c + +# CHECK: mdeb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x0c + +# CHECK: mdeb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x0c + +# CHECK: mdeb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x0c + +# CHECK: mdeb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x0c + +# CHECK: mdeb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x0c + +# CHECK: mdeb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x0c diff --git a/test/MC/Disassembler/SystemZ/insn-mdebr.txt b/test/MC/Disassembler/SystemZ/insn-mdebr.txt new file mode 100644 index 0000000000..8503424c20 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mdebr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mdebr %f0, %f0 +0xb3 0x0c 0x00 0x00 + +# CHECK: mdebr %f0, %f15 +0xb3 0x0c 0x00 0x0f + +# CHECK: mdebr %f7, %f8 +0xb3 0x0c 0x00 0x78 + +# CHECK: mdebr %f15, %f0 +0xb3 0x0c 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-meeb.txt b/test/MC/Disassembler/SystemZ/insn-meeb.txt new file mode 100644 index 0000000000..f4dbf5fd23 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-meeb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: meeb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x17 + +# CHECK: meeb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x17 + +# CHECK: meeb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x17 + +# CHECK: meeb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x17 + +# CHECK: meeb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x17 + +# CHECK: meeb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x17 + +# CHECK: meeb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x17 diff --git a/test/MC/Disassembler/SystemZ/insn-meebr.txt b/test/MC/Disassembler/SystemZ/insn-meebr.txt new file mode 100644 index 0000000000..57f342b5fe --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-meebr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: meebr %f0, %f0 +0xb3 0x17 0x00 0x00 + +# CHECK: meebr %f0, %f15 +0xb3 0x17 0x00 0x0f + +# CHECK: meebr %f7, %f8 +0xb3 0x17 0x00 0x78 + +# CHECK: meebr %f15, %f0 +0xb3 0x17 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-mghi.txt b/test/MC/Disassembler/SystemZ/insn-mghi.txt new file mode 100644 index 0000000000..42bb316682 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mghi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mghi %r0, -32768 +0xa7 0x0d 0x80 0x00 + +# CHECK: mghi %r0, -1 +0xa7 0x0d 0xff 0xff + +# CHECK: mghi %r0, 0 +0xa7 0x0d 0x00 0x00 + +# CHECK: mghi %r0, 1 +0xa7 0x0d 0x00 0x01 + +# CHECK: mghi %r0, 32767 +0xa7 0x0d 0x7f 0xff + +# CHECK: mghi %r15, 0 +0xa7 0xfd 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-mh.txt b/test/MC/Disassembler/SystemZ/insn-mh.txt new file mode 100644 index 0000000000..d5ab3928c1 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mh.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mh %r0, 0 +0x4c 0x00 0x00 0x00 + +# CHECK: mh %r0, 4095 +0x4c 0x00 0x0f 0xff + +# CHECK: mh %r0, 0(%r1) +0x4c 0x00 0x10 0x00 + +# CHECK: mh %r0, 0(%r15) +0x4c 0x00 0xf0 0x00 + +# CHECK: mh %r0, 4095(%r1,%r15) +0x4c 0x01 0xff 0xff + +# CHECK: mh %r0, 4095(%r15,%r1) +0x4c 0x0f 0x1f 0xff + +# CHECK: mh %r15, 0 +0x4c 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-mhi.txt b/test/MC/Disassembler/SystemZ/insn-mhi.txt new file mode 100644 index 0000000000..b282683fba --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mhi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mhi %r0, -32768 +0xa7 0x0c 0x80 0x00 + +# CHECK: mhi %r0, -1 +0xa7 0x0c 0xff 0xff + +# CHECK: mhi %r0, 0 +0xa7 0x0c 0x00 0x00 + +# CHECK: mhi %r0, 1 +0xa7 0x0c 0x00 0x01 + +# CHECK: mhi %r0, 32767 +0xa7 0x0c 0x7f 0xff + +# CHECK: mhi %r15, 0 +0xa7 0xfc 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-mhy.txt b/test/MC/Disassembler/SystemZ/insn-mhy.txt new file mode 100644 index 0000000000..9279db1727 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mhy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mhy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x7c + +# CHECK: mhy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x7c + +# CHECK: mhy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x7c + +# CHECK: mhy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x7c + +# CHECK: mhy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x7c + +# CHECK: mhy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x7c + +# CHECK: mhy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x7c + +# CHECK: mhy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x7c + +# CHECK: mhy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x7c + +# CHECK: mhy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x7c diff --git a/test/MC/Disassembler/SystemZ/insn-mlg.txt b/test/MC/Disassembler/SystemZ/insn-mlg.txt new file mode 100644 index 0000000000..eeceecea8e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mlg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mlg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x86 + +# CHECK: mlg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x86 + +# CHECK: mlg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x86 + +# CHECK: mlg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x86 + +# CHECK: mlg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x86 + +# CHECK: mlg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x86 + +# CHECK: mlg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x86 + +# CHECK: mlg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x86 + +# CHECK: mlg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x86 + +# CHECK: mlg %r14, 0 +0xe3 0xe0 0x00 0x00 0x00 0x86 diff --git a/test/MC/Disassembler/SystemZ/insn-mlgr.txt b/test/MC/Disassembler/SystemZ/insn-mlgr.txt new file mode 100644 index 0000000000..ab7c2e5d05 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mlgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mlgr %r0, %r0 +0xb9 0x86 0x00 0x00 + +# CHECK: mlgr %r0, %r15 +0xb9 0x86 0x00 0x0f + +# CHECK: mlgr %r14, %r0 +0xb9 0x86 0x00 0xe0 + +# CHECK: mlgr %r6, %r9 +0xb9 0x86 0x00 0x69 diff --git a/test/MC/Disassembler/SystemZ/insn-ms.txt b/test/MC/Disassembler/SystemZ/insn-ms.txt new file mode 100644 index 0000000000..558f9cb823 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ms.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ms %r0, 0 +0x71 0x00 0x00 0x00 + +# CHECK: ms %r0, 4095 +0x71 0x00 0x0f 0xff + +# CHECK: ms %r0, 0(%r1) +0x71 0x00 0x10 0x00 + +# CHECK: ms %r0, 0(%r15) +0x71 0x00 0xf0 0x00 + +# CHECK: ms %r0, 4095(%r1,%r15) +0x71 0x01 0xff 0xff + +# CHECK: ms %r0, 4095(%r15,%r1) +0x71 0x0f 0x1f 0xff + +# CHECK: ms %r15, 0 +0x71 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-msdb.txt b/test/MC/Disassembler/SystemZ/insn-msdb.txt new file mode 100644 index 0000000000..12e1e3ce64 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msdb.txt @@ -0,0 +1,27 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msdb %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x1f + +# CHECK: msdb %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x1f + +# CHECK: msdb %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x1f + +# CHECK: msdb %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x1f + +# CHECK: msdb %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x1f + +# CHECK: msdb %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x1f + +# CHECK: msdb %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x1f + +# CHECK: msdb %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x1f + +# CHECK: msdb %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x1f diff --git a/test/MC/Disassembler/SystemZ/insn-msdbr.txt b/test/MC/Disassembler/SystemZ/insn-msdbr.txt new file mode 100644 index 0000000000..c24d23b405 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msdbr.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msdbr %f0, %f0, %f0 +0xb3 0x1f 0x00 0x00 + +# CHECK: msdbr %f0, %f0, %f15 +0xb3 0x1f 0x00 0x0f + +# CHECK: msdbr %f0, %f15, %f0 +0xb3 0x1f 0x00 0xf0 + +# CHECK: msdbr %f15, %f0, %f0 +0xb3 0x1f 0xf0 0x00 + +# CHECK: msdbr %f7, %f8, %f9 +0xb3 0x1f 0x70 0x89 + +# CHECK: msdbr %f15, %f15, %f15 +0xb3 0x1f 0xf0 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-mseb.txt b/test/MC/Disassembler/SystemZ/insn-mseb.txt new file mode 100644 index 0000000000..f53cc7c44a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mseb.txt @@ -0,0 +1,27 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mseb %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x0f + +# CHECK: mseb %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x0f + +# CHECK: mseb %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x0f + +# CHECK: mseb %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x0f + +# CHECK: mseb %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x0f + +# CHECK: mseb %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x0f + +# CHECK: mseb %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x0f + +# CHECK: mseb %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x0f + +# CHECK: mseb %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x0f diff --git a/test/MC/Disassembler/SystemZ/insn-msebr.txt b/test/MC/Disassembler/SystemZ/insn-msebr.txt new file mode 100644 index 0000000000..d157edcd24 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msebr.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msebr %f0, %f0, %f0 +0xb3 0x0f 0x00 0x00 + +# CHECK: msebr %f0, %f0, %f15 +0xb3 0x0f 0x00 0x0f + +# CHECK: msebr %f0, %f15, %f0 +0xb3 0x0f 0x00 0xf0 + +# CHECK: msebr %f15, %f0, %f0 +0xb3 0x0f 0xf0 0x00 + +# CHECK: msebr %f7, %f8, %f9 +0xb3 0x0f 0x70 0x89 + +# CHECK: msebr %f15, %f15, %f15 +0xb3 0x0f 0xf0 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-msfi.txt b/test/MC/Disassembler/SystemZ/insn-msfi.txt new file mode 100644 index 0000000000..9991f62f2f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msfi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msfi %r0, -2147483648 +0xc2 0x01 0x80 0x00 0x00 0x00 + +# CHECK: msfi %r0, -1 +0xc2 0x01 0xff 0xff 0xff 0xff + +# CHECK: msfi %r0, 0 +0xc2 0x01 0x00 0x00 0x00 0x00 + +# CHECK: msfi %r0, 1 +0xc2 0x01 0x00 0x00 0x00 0x01 + +# CHECK: msfi %r0, 2147483647 +0xc2 0x01 0x7f 0xff 0xff 0xff + +# CHECK: msfi %r15, 0 +0xc2 0xf1 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-msg.txt b/test/MC/Disassembler/SystemZ/insn-msg.txt new file mode 100644 index 0000000000..9185433099 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x0c + +# CHECK: msg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x0c + +# CHECK: msg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x0c + +# CHECK: msg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x0c + +# CHECK: msg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x0c + +# CHECK: msg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x0c + +# CHECK: msg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x0c + +# CHECK: msg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x0c + +# CHECK: msg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x0c + +# CHECK: msg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x0c diff --git a/test/MC/Disassembler/SystemZ/insn-msgf.txt b/test/MC/Disassembler/SystemZ/insn-msgf.txt new file mode 100644 index 0000000000..031922bcef --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msgf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x1c + +# CHECK: msgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x1c + +# CHECK: msgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x1c + +# CHECK: msgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x1c + +# CHECK: msgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x1c + +# CHECK: msgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x1c + +# CHECK: msgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x1c + +# CHECK: msgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x1c + +# CHECK: msgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x1c + +# CHECK: msgf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x1c diff --git a/test/MC/Disassembler/SystemZ/insn-msgfi.txt b/test/MC/Disassembler/SystemZ/insn-msgfi.txt new file mode 100644 index 0000000000..86300ef41b --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msgfi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msgfi %r0, -2147483648 +0xc2 0x00 0x80 0x00 0x00 0x00 + +# CHECK: msgfi %r0, -1 +0xc2 0x00 0xff 0xff 0xff 0xff + +# CHECK: msgfi %r0, 0 +0xc2 0x00 0x00 0x00 0x00 0x00 + +# CHECK: msgfi %r0, 1 +0xc2 0x00 0x00 0x00 0x00 0x01 + +# CHECK: msgfi %r0, 2147483647 +0xc2 0x00 0x7f 0xff 0xff 0xff + +# CHECK: msgfi %r15, 0 +0xc2 0xf0 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-msgfr.txt b/test/MC/Disassembler/SystemZ/insn-msgfr.txt new file mode 100644 index 0000000000..028d36aea6 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msgfr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msgfr %r0, %r0 +0xb9 0x1c 0x00 0x00 + +# CHECK: msgfr %r0, %r15 +0xb9 0x1c 0x00 0x0f + +# CHECK: msgfr %r15, %r0 +0xb9 0x1c 0x00 0xf0 + +# CHECK: msgfr %r7, %r8 +0xb9 0x1c 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-msgr.txt b/test/MC/Disassembler/SystemZ/insn-msgr.txt new file mode 100644 index 0000000000..85c1e47892 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msgr %r0, %r0 +0xb9 0x0c 0x00 0x00 + +# CHECK: msgr %r0, %r15 +0xb9 0x0c 0x00 0x0f + +# CHECK: msgr %r15, %r0 +0xb9 0x0c 0x00 0xf0 + +# CHECK: msgr %r7, %r8 +0xb9 0x0c 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-msr.txt b/test/MC/Disassembler/SystemZ/insn-msr.txt new file mode 100644 index 0000000000..61a88a18bd --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msr %r0, %r0 +0xb2 0x52 0x00 0x00 + +# CHECK: msr %r0, %r15 +0xb2 0x52 0x00 0x0f + +# CHECK: msr %r15, %r0 +0xb2 0x52 0x00 0xf0 + +# CHECK: msr %r7, %r8 +0xb2 0x52 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-msy.txt b/test/MC/Disassembler/SystemZ/insn-msy.txt new file mode 100644 index 0000000000..46524563be --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-msy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: msy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x51 + +# CHECK: msy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x51 + +# CHECK: msy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x51 + +# CHECK: msy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x51 + +# CHECK: msy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x51 + +# CHECK: msy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x51 + +# CHECK: msy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x51 + +# CHECK: msy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x51 + +# CHECK: msy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x51 + +# CHECK: msy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x51 diff --git a/test/MC/Disassembler/SystemZ/insn-mvghi.txt b/test/MC/Disassembler/SystemZ/insn-mvghi.txt new file mode 100644 index 0000000000..c6abe4bf83 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mvghi.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mvghi 0, 0 +0xe5 0x48 0x00 0x00 0x00 0x00 + +# CHECK: mvghi 4095, 0 +0xe5 0x48 0x0f 0xff 0x00 0x00 + +# CHECK: mvghi 0, -32768 +0xe5 0x48 0x00 0x00 0x80 0x00 + +# CHECK: mvghi 0, -1 +0xe5 0x48 0x00 0x00 0xff 0xff + +# CHECK: mvghi 0, 0 +0xe5 0x48 0x00 0x00 0x00 0x00 + +# CHECK: mvghi 0, 1 +0xe5 0x48 0x00 0x00 0x00 0x01 + +# CHECK: mvghi 0, 32767 +0xe5 0x48 0x00 0x00 0x7f 0xff + +# CHECK: mvghi 0(%r1), 42 +0xe5 0x48 0x10 0x00 0x00 0x2a + +# CHECK: mvghi 0(%r15), 42 +0xe5 0x48 0xf0 0x00 0x00 0x2a + +# CHECK: mvghi 4095(%r1), 42 +0xe5 0x48 0x1f 0xff 0x00 0x2a + +# CHECK: mvghi 4095(%r15), 42 +0xe5 0x48 0xff 0xff 0x00 0x2a diff --git a/test/MC/Disassembler/SystemZ/insn-mvhhi.txt b/test/MC/Disassembler/SystemZ/insn-mvhhi.txt new file mode 100644 index 0000000000..3ee6576da6 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mvhhi.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mvhhi 0, 0 +0xe5 0x44 0x00 0x00 0x00 0x00 + +# CHECK: mvhhi 4095, 0 +0xe5 0x44 0x0f 0xff 0x00 0x00 + +# CHECK: mvhhi 0, -32768 +0xe5 0x44 0x00 0x00 0x80 0x00 + +# CHECK: mvhhi 0, -1 +0xe5 0x44 0x00 0x00 0xff 0xff + +# CHECK: mvhhi 0, 0 +0xe5 0x44 0x00 0x00 0x00 0x00 + +# CHECK: mvhhi 0, 1 +0xe5 0x44 0x00 0x00 0x00 0x01 + +# CHECK: mvhhi 0, 32767 +0xe5 0x44 0x00 0x00 0x7f 0xff + +# CHECK: mvhhi 0(%r1), 42 +0xe5 0x44 0x10 0x00 0x00 0x2a + +# CHECK: mvhhi 0(%r15), 42 +0xe5 0x44 0xf0 0x00 0x00 0x2a + +# CHECK: mvhhi 4095(%r1), 42 +0xe5 0x44 0x1f 0xff 0x00 0x2a + +# CHECK: mvhhi 4095(%r15), 42 +0xe5 0x44 0xff 0xff 0x00 0x2a diff --git a/test/MC/Disassembler/SystemZ/insn-mvhi.txt b/test/MC/Disassembler/SystemZ/insn-mvhi.txt new file mode 100644 index 0000000000..15ef24e7eb --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mvhi.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mvhi 0, 0 +0xe5 0x4c 0x00 0x00 0x00 0x00 + +# CHECK: mvhi 4095, 0 +0xe5 0x4c 0x0f 0xff 0x00 0x00 + +# CHECK: mvhi 0, -32768 +0xe5 0x4c 0x00 0x00 0x80 0x00 + +# CHECK: mvhi 0, -1 +0xe5 0x4c 0x00 0x00 0xff 0xff + +# CHECK: mvhi 0, 0 +0xe5 0x4c 0x00 0x00 0x00 0x00 + +# CHECK: mvhi 0, 1 +0xe5 0x4c 0x00 0x00 0x00 0x01 + +# CHECK: mvhi 0, 32767 +0xe5 0x4c 0x00 0x00 0x7f 0xff + +# CHECK: mvhi 0(%r1), 42 +0xe5 0x4c 0x10 0x00 0x00 0x2a + +# CHECK: mvhi 0(%r15), 42 +0xe5 0x4c 0xf0 0x00 0x00 0x2a + +# CHECK: mvhi 4095(%r1), 42 +0xe5 0x4c 0x1f 0xff 0x00 0x2a + +# CHECK: mvhi 4095(%r15), 42 +0xe5 0x4c 0xff 0xff 0x00 0x2a diff --git a/test/MC/Disassembler/SystemZ/insn-mvi.txt b/test/MC/Disassembler/SystemZ/insn-mvi.txt new file mode 100644 index 0000000000..f81a7455eb --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mvi.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mvi 0, 0 +0x92 0x00 0x00 0x00 + +# CHECK: mvi 4095, 0 +0x92 0x00 0x0f 0xff + +# CHECK: mvi 0, 255 +0x92 0xff 0x00 0x00 + +# CHECK: mvi 0(%r1), 42 +0x92 0x2a 0x10 0x00 + +# CHECK: mvi 0(%r15), 42 +0x92 0x2a 0xf0 0x00 + +# CHECK: mvi 4095(%r1), 42 +0x92 0x2a 0x1f 0xff + +# CHECK: mvi 4095(%r15), 42 +0x92 0x2a 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-mviy.txt b/test/MC/Disassembler/SystemZ/insn-mviy.txt new file mode 100644 index 0000000000..ed249c7aa2 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mviy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mviy -524288, 0 +0xeb 0x00 0x00 0x00 0x80 0x52 + +# CHECK: mviy -1, 0 +0xeb 0x00 0x0f 0xff 0xff 0x52 + +# CHECK: mviy 0, 0 +0xeb 0x00 0x00 0x00 0x00 0x52 + +# CHECK: mviy 1, 0 +0xeb 0x00 0x00 0x01 0x00 0x52 + +# CHECK: mviy 524287, 0 +0xeb 0x00 0x0f 0xff 0x7f 0x52 + +# CHECK: mviy 0, 255 +0xeb 0xff 0x00 0x00 0x00 0x52 + +# CHECK: mviy 0(%r1), 42 +0xeb 0x2a 0x10 0x00 0x00 0x52 + +# CHECK: mviy 0(%r15), 42 +0xeb 0x2a 0xf0 0x00 0x00 0x52 + +# CHECK: mviy 524287(%r1), 42 +0xeb 0x2a 0x1f 0xff 0x7f 0x52 + +# CHECK: mviy 524287(%r15), 42 +0xeb 0x2a 0xff 0xff 0x7f 0x52 diff --git a/test/MC/Disassembler/SystemZ/insn-mxbr.txt b/test/MC/Disassembler/SystemZ/insn-mxbr.txt new file mode 100644 index 0000000000..acc30aae23 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mxbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mxbr %f0, %f0 +0xb3 0x4c 0x00 0x00 + +# CHECK: mxbr %f0, %f13 +0xb3 0x4c 0x00 0x0d + +# CHECK: mxbr %f8, %f5 +0xb3 0x4c 0x00 0x85 + +# CHECK: mxbr %f13, %f13 +0xb3 0x4c 0x00 0xdd diff --git a/test/MC/Disassembler/SystemZ/insn-mxdb.txt b/test/MC/Disassembler/SystemZ/insn-mxdb.txt new file mode 100644 index 0000000000..d355c48d5c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mxdb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mxdb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x07 + +# CHECK: mxdb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x07 + +# CHECK: mxdb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x07 + +# CHECK: mxdb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x07 + +# CHECK: mxdb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x07 + +# CHECK: mxdb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x07 + +# CHECK: mxdb %f13, 0 +0xed 0xd0 0x00 0x00 0x00 0x07 diff --git a/test/MC/Disassembler/SystemZ/insn-mxdbr.txt b/test/MC/Disassembler/SystemZ/insn-mxdbr.txt new file mode 100644 index 0000000000..1f3b6e3043 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-mxdbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: mxdbr %f0, %f0 +0xb3 0x07 0x00 0x00 + +# CHECK: mxdbr %f0, %f15 +0xb3 0x07 0x00 0x0f + +# CHECK: mxdbr %f8, %f8 +0xb3 0x07 0x00 0x88 + +# CHECK: mxdbr %f13, %f0 +0xb3 0x07 0x00 0xd0 diff --git a/test/MC/Disassembler/SystemZ/insn-n.txt b/test/MC/Disassembler/SystemZ/insn-n.txt new file mode 100644 index 0000000000..67e0746147 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-n.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: n %r0, 0 +0x54 0x00 0x00 0x00 + +# CHECK: n %r0, 4095 +0x54 0x00 0x0f 0xff + +# CHECK: n %r0, 0(%r1) +0x54 0x00 0x10 0x00 + +# CHECK: n %r0, 0(%r15) +0x54 0x00 0xf0 0x00 + +# CHECK: n %r0, 4095(%r1,%r15) +0x54 0x01 0xff 0xff + +# CHECK: n %r0, 4095(%r15,%r1) +0x54 0x0f 0x1f 0xff + +# CHECK: n %r15, 0 +0x54 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-ng.txt b/test/MC/Disassembler/SystemZ/insn-ng.txt new file mode 100644 index 0000000000..082c04b7a8 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ng.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ng %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x80 + +# CHECK: ng %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x80 + +# CHECK: ng %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x80 + +# CHECK: ng %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x80 + +# CHECK: ng %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x80 + +# CHECK: ng %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x80 + +# CHECK: ng %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x80 + +# CHECK: ng %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x80 + +# CHECK: ng %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x80 + +# CHECK: ng %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x80 diff --git a/test/MC/Disassembler/SystemZ/insn-ngr.txt b/test/MC/Disassembler/SystemZ/insn-ngr.txt new file mode 100644 index 0000000000..08e957e4ec --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ngr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ngr %r0, %r0 +0xb9 0x80 0x00 0x00 + +# CHECK: ngr %r0, %r15 +0xb9 0x80 0x00 0x0f + +# CHECK: ngr %r15, %r0 +0xb9 0x80 0x00 0xf0 + +# CHECK: ngr %r7, %r8 +0xb9 0x80 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-ni.txt b/test/MC/Disassembler/SystemZ/insn-ni.txt new file mode 100644 index 0000000000..b90888d71b --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ni.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ni 0, 0 +0x94 0x00 0x00 0x00 + +# CHECK: ni 4095, 0 +0x94 0x00 0x0f 0xff + +# CHECK: ni 0, 255 +0x94 0xff 0x00 0x00 + +# CHECK: ni 0(%r1), 42 +0x94 0x2a 0x10 0x00 + +# CHECK: ni 0(%r15), 42 +0x94 0x2a 0xf0 0x00 + +# CHECK: ni 4095(%r1), 42 +0x94 0x2a 0x1f 0xff + +# CHECK: ni 4095(%r15), 42 +0x94 0x2a 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-nihf.txt b/test/MC/Disassembler/SystemZ/insn-nihf.txt new file mode 100644 index 0000000000..ee91a7869a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-nihf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: nihf %r0, 0 +0xc0 0x0a 0x00 0x00 0x00 0x00 + +# CHECK: nihf %r0, 4294967295 +0xc0 0x0a 0xff 0xff 0xff 0xff + +# CHECK: nihf %r15, 0 +0xc0 0xfa 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-nihh.txt b/test/MC/Disassembler/SystemZ/insn-nihh.txt new file mode 100644 index 0000000000..4036ff4748 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-nihh.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: nihh %r0, 0 +0xa5 0x04 0x00 0x00 + +# CHECK: nihh %r0, 32768 +0xa5 0x04 0x80 0x00 + +# CHECK: nihh %r0, 65535 +0xa5 0x04 0xff 0xff + +# CHECK: nihh %r15, 0 +0xa5 0xf4 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-nihl.txt b/test/MC/Disassembler/SystemZ/insn-nihl.txt new file mode 100644 index 0000000000..3cc72b9f4e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-nihl.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: nihl %r0, 0 +0xa5 0x05 0x00 0x00 + +# CHECK: nihl %r0, 32768 +0xa5 0x05 0x80 0x00 + +# CHECK: nihl %r0, 65535 +0xa5 0x05 0xff 0xff + +# CHECK: nihl %r15, 0 +0xa5 0xf5 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-nilf.txt b/test/MC/Disassembler/SystemZ/insn-nilf.txt new file mode 100644 index 0000000000..6ba3212fbe --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-nilf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: nilf %r0, 0 +0xc0 0x0b 0x00 0x00 0x00 0x00 + +# CHECK: nilf %r0, 4294967295 +0xc0 0x0b 0xff 0xff 0xff 0xff + +# CHECK: nilf %r15, 0 +0xc0 0xfb 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-nilh.txt b/test/MC/Disassembler/SystemZ/insn-nilh.txt new file mode 100644 index 0000000000..bda87c3c9c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-nilh.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: nilh %r0, 0 +0xa5 0x06 0x00 0x00 + +# CHECK: nilh %r0, 32768 +0xa5 0x06 0x80 0x00 + +# CHECK: nilh %r0, 65535 +0xa5 0x06 0xff 0xff + +# CHECK: nilh %r15, 0 +0xa5 0xf6 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-nill.txt b/test/MC/Disassembler/SystemZ/insn-nill.txt new file mode 100644 index 0000000000..e79984444e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-nill.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: nill %r0, 0 +0xa5 0x07 0x00 0x00 + +# CHECK: nill %r0, 32768 +0xa5 0x07 0x80 0x00 + +# CHECK: nill %r0, 65535 +0xa5 0x07 0xff 0xff + +# CHECK: nill %r15, 0 +0xa5 0xf7 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-niy.txt b/test/MC/Disassembler/SystemZ/insn-niy.txt new file mode 100644 index 0000000000..96767b45e4 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-niy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: niy -524288, 0 +0xeb 0x00 0x00 0x00 0x80 0x54 + +# CHECK: niy -1, 0 +0xeb 0x00 0x0f 0xff 0xff 0x54 + +# CHECK: niy 0, 0 +0xeb 0x00 0x00 0x00 0x00 0x54 + +# CHECK: niy 1, 0 +0xeb 0x00 0x00 0x01 0x00 0x54 + +# CHECK: niy 524287, 0 +0xeb 0x00 0x0f 0xff 0x7f 0x54 + +# CHECK: niy 0, 255 +0xeb 0xff 0x00 0x00 0x00 0x54 + +# CHECK: niy 0(%r1), 42 +0xeb 0x2a 0x10 0x00 0x00 0x54 + +# CHECK: niy 0(%r15), 42 +0xeb 0x2a 0xf0 0x00 0x00 0x54 + +# CHECK: niy 524287(%r1), 42 +0xeb 0x2a 0x1f 0xff 0x7f 0x54 + +# CHECK: niy 524287(%r15), 42 +0xeb 0x2a 0xff 0xff 0x7f 0x54 diff --git a/test/MC/Disassembler/SystemZ/insn-nr.txt b/test/MC/Disassembler/SystemZ/insn-nr.txt new file mode 100644 index 0000000000..af57513654 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-nr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: nr %r0, %r0 +0x14 0x00 + +# CHECK: nr %r0, %r15 +0x14 0x0f + +# CHECK: nr %r15, %r0 +0x14 0xf0 + +# CHECK: nr %r7, %r8 +0x14 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-ny.txt b/test/MC/Disassembler/SystemZ/insn-ny.txt new file mode 100644 index 0000000000..ac9d06c5be --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ny.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ny %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x54 + +# CHECK: ny %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x54 + +# CHECK: ny %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x54 + +# CHECK: ny %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x54 + +# CHECK: ny %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x54 + +# CHECK: ny %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x54 + +# CHECK: ny %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x54 + +# CHECK: ny %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x54 + +# CHECK: ny %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x54 + +# CHECK: ny %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x54 diff --git a/test/MC/Disassembler/SystemZ/insn-o.txt b/test/MC/Disassembler/SystemZ/insn-o.txt new file mode 100644 index 0000000000..56d876ba6c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-o.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: o %r0, 0 +0x56 0x00 0x00 0x00 + +# CHECK: o %r0, 4095 +0x56 0x00 0x0f 0xff + +# CHECK: o %r0, 0(%r1) +0x56 0x00 0x10 0x00 + +# CHECK: o %r0, 0(%r15) +0x56 0x00 0xf0 0x00 + +# CHECK: o %r0, 4095(%r1,%r15) +0x56 0x01 0xff 0xff + +# CHECK: o %r0, 4095(%r15,%r1) +0x56 0x0f 0x1f 0xff + +# CHECK: o %r15, 0 +0x56 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-og.txt b/test/MC/Disassembler/SystemZ/insn-og.txt new file mode 100644 index 0000000000..6d7961a556 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-og.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: og %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x81 + +# CHECK: og %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x81 + +# CHECK: og %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x81 + +# CHECK: og %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x81 + +# CHECK: og %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x81 + +# CHECK: og %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x81 + +# CHECK: og %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x81 + +# CHECK: og %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x81 + +# CHECK: og %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x81 + +# CHECK: og %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x81 diff --git a/test/MC/Disassembler/SystemZ/insn-ogr.txt b/test/MC/Disassembler/SystemZ/insn-ogr.txt new file mode 100644 index 0000000000..9f3f105d9a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ogr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ogr %r0, %r0 +0xb9 0x81 0x00 0x00 + +# CHECK: ogr %r0, %r15 +0xb9 0x81 0x00 0x0f + +# CHECK: ogr %r15, %r0 +0xb9 0x81 0x00 0xf0 + +# CHECK: ogr %r7, %r8 +0xb9 0x81 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-oi.txt b/test/MC/Disassembler/SystemZ/insn-oi.txt new file mode 100644 index 0000000000..daa3bb76ed --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-oi.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: oi 0, 0 +0x96 0x00 0x00 0x00 + +# CHECK: oi 4095, 0 +0x96 0x00 0x0f 0xff + +# CHECK: oi 0, 255 +0x96 0xff 0x00 0x00 + +# CHECK: oi 0(%r1), 42 +0x96 0x2a 0x10 0x00 + +# CHECK: oi 0(%r15), 42 +0x96 0x2a 0xf0 0x00 + +# CHECK: oi 4095(%r1), 42 +0x96 0x2a 0x1f 0xff + +# CHECK: oi 4095(%r15), 42 +0x96 0x2a 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-oihf.txt b/test/MC/Disassembler/SystemZ/insn-oihf.txt new file mode 100644 index 0000000000..d481dabd7f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-oihf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: oihf %r0, 0 +0xc0 0x0c 0x00 0x00 0x00 0x00 + +# CHECK: oihf %r0, 4294967295 +0xc0 0x0c 0xff 0xff 0xff 0xff + +# CHECK: oihf %r15, 0 +0xc0 0xfc 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-oihh.txt b/test/MC/Disassembler/SystemZ/insn-oihh.txt new file mode 100644 index 0000000000..a063ad322f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-oihh.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: oihh %r0, 0 +0xa5 0x08 0x00 0x00 + +# CHECK: oihh %r0, 32768 +0xa5 0x08 0x80 0x00 + +# CHECK: oihh %r0, 65535 +0xa5 0x08 0xff 0xff + +# CHECK: oihh %r15, 0 +0xa5 0xf8 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-oihl.txt b/test/MC/Disassembler/SystemZ/insn-oihl.txt new file mode 100644 index 0000000000..da762f30ce --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-oihl.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: oihl %r0, 0 +0xa5 0x09 0x00 0x00 + +# CHECK: oihl %r0, 32768 +0xa5 0x09 0x80 0x00 + +# CHECK: oihl %r0, 65535 +0xa5 0x09 0xff 0xff + +# CHECK: oihl %r15, 0 +0xa5 0xf9 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-oilf.txt b/test/MC/Disassembler/SystemZ/insn-oilf.txt new file mode 100644 index 0000000000..22dc79d1e7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-oilf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: oilf %r0, 0 +0xc0 0x0d 0x00 0x00 0x00 0x00 + +# CHECK: oilf %r0, 4294967295 +0xc0 0x0d 0xff 0xff 0xff 0xff + +# CHECK: oilf %r15, 0 +0xc0 0xfd 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-oilh.txt b/test/MC/Disassembler/SystemZ/insn-oilh.txt new file mode 100644 index 0000000000..ce3041c1fd --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-oilh.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: oilh %r0, 0 +0xa5 0x0a 0x00 0x00 + +# CHECK: oilh %r0, 32768 +0xa5 0x0a 0x80 0x00 + +# CHECK: oilh %r0, 65535 +0xa5 0x0a 0xff 0xff + +# CHECK: oilh %r15, 0 +0xa5 0xfa 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-oill.txt b/test/MC/Disassembler/SystemZ/insn-oill.txt new file mode 100644 index 0000000000..34663a3f13 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-oill.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: oill %r0, 0 +0xa5 0x0b 0x00 0x00 + +# CHECK: oill %r0, 32768 +0xa5 0x0b 0x80 0x00 + +# CHECK: oill %r0, 65535 +0xa5 0x0b 0xff 0xff + +# CHECK: oill %r15, 0 +0xa5 0xfb 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-oiy.txt b/test/MC/Disassembler/SystemZ/insn-oiy.txt new file mode 100644 index 0000000000..c56b2de3b7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-oiy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: oiy -524288, 0 +0xeb 0x00 0x00 0x00 0x80 0x56 + +# CHECK: oiy -1, 0 +0xeb 0x00 0x0f 0xff 0xff 0x56 + +# CHECK: oiy 0, 0 +0xeb 0x00 0x00 0x00 0x00 0x56 + +# CHECK: oiy 1, 0 +0xeb 0x00 0x00 0x01 0x00 0x56 + +# CHECK: oiy 524287, 0 +0xeb 0x00 0x0f 0xff 0x7f 0x56 + +# CHECK: oiy 0, 255 +0xeb 0xff 0x00 0x00 0x00 0x56 + +# CHECK: oiy 0(%r1), 42 +0xeb 0x2a 0x10 0x00 0x00 0x56 + +# CHECK: oiy 0(%r15), 42 +0xeb 0x2a 0xf0 0x00 0x00 0x56 + +# CHECK: oiy 524287(%r1), 42 +0xeb 0x2a 0x1f 0xff 0x7f 0x56 + +# CHECK: oiy 524287(%r15), 42 +0xeb 0x2a 0xff 0xff 0x7f 0x56 diff --git a/test/MC/Disassembler/SystemZ/insn-or.txt b/test/MC/Disassembler/SystemZ/insn-or.txt new file mode 100644 index 0000000000..e79c6aa038 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-or.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: or %r0, %r0 +0x16 0x00 + +# CHECK: or %r0, %r15 +0x16 0x0f + +# CHECK: or %r15, %r0 +0x16 0xf0 + +# CHECK: or %r7, %r8 +0x16 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-oy.txt b/test/MC/Disassembler/SystemZ/insn-oy.txt new file mode 100644 index 0000000000..a4ea8eda36 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-oy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: oy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x56 + +# CHECK: oy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x56 + +# CHECK: oy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x56 + +# CHECK: oy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x56 + +# CHECK: oy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x56 + +# CHECK: oy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x56 + +# CHECK: oy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x56 + +# CHECK: oy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x56 + +# CHECK: oy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x56 + +# CHECK: oy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x56 diff --git a/test/MC/Disassembler/SystemZ/insn-risbg.txt b/test/MC/Disassembler/SystemZ/insn-risbg.txt new file mode 100644 index 0000000000..b0bde8412e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-risbg.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: risbg %r0, %r0, 0, 0, 0 +0xec 0x00 0x00 0x00 0x00 0x55 + +# CHECK: risbg %r0, %r0, 0, 0, 63 +0xec 0x00 0x00 0x00 0x3f 0x55 + +# CHECK: risbg %r0, %r0, 0, 63, 0 +0xec 0x00 0x00 0x3f 0x00 0x55 + +# CHECK: risbg %r0, %r0, 63, 0, 0 +0xec 0x00 0x3f 0x00 0x00 0x55 + +# CHECK: risbg %r0, %r15, 0, 0, 0 +0xec 0x0f 0x00 0x00 0x00 0x55 + +# CHECK: risbg %r15, %r0, 0, 0, 0 +0xec 0xf0 0x00 0x00 0x00 0x55 + +# CHECK: risbg %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x07 0x08 0x55 diff --git a/test/MC/Disassembler/SystemZ/insn-rll.txt b/test/MC/Disassembler/SystemZ/insn-rll.txt new file mode 100644 index 0000000000..97a09f8ace --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-rll.txt @@ -0,0 +1,36 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: rll %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x1d + +# CHECK: rll %r15, %r1, 0 +0xeb 0xf1 0x00 0x00 0x00 0x1d + +# CHECK: rll %r1, %r15, 0 +0xeb 0x1f 0x00 0x00 0x00 0x1d + +# CHECK: rll %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0x1d + +# CHECK: rll %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x1d + +# CHECK: rll %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x1d + +# CHECK: rll %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x1d + +# CHECK: rll %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x1d + +# CHECK: rll %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x1d + +# CHECK: rll %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x1d + +# CHECK: rll %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x1d + +# CHECK: rll %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x1d diff --git a/test/MC/Disassembler/SystemZ/insn-rllg.txt b/test/MC/Disassembler/SystemZ/insn-rllg.txt new file mode 100644 index 0000000000..65d273f328 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-rllg.txt @@ -0,0 +1,36 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: rllg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x1c + +# CHECK: rllg %r15, %r1, 0 +0xeb 0xf1 0x00 0x00 0x00 0x1c + +# CHECK: rllg %r1, %r15, 0 +0xeb 0x1f 0x00 0x00 0x00 0x1c + +# CHECK: rllg %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0x1c + +# CHECK: rllg %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x1c + +# CHECK: rllg %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x1c + +# CHECK: rllg %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x1c + +# CHECK: rllg %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x1c + +# CHECK: rllg %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x1c + +# CHECK: rllg %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x1c + +# CHECK: rllg %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x1c + +# CHECK: rllg %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x1c diff --git a/test/MC/Disassembler/SystemZ/insn-s.txt b/test/MC/Disassembler/SystemZ/insn-s.txt new file mode 100644 index 0000000000..8f61de1b3b --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-s.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: s %r0, 0 +0x5b 0x00 0x00 0x00 + +# CHECK: s %r0, 4095 +0x5b 0x00 0x0f 0xff + +# CHECK: s %r0, 0(%r1) +0x5b 0x00 0x10 0x00 + +# CHECK: s %r0, 0(%r15) +0x5b 0x00 0xf0 0x00 + +# CHECK: s %r0, 4095(%r1,%r15) +0x5b 0x01 0xff 0xff + +# CHECK: s %r0, 4095(%r15,%r1) +0x5b 0x0f 0x1f 0xff + +# CHECK: s %r15, 0 +0x5b 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-sdb.txt b/test/MC/Disassembler/SystemZ/insn-sdb.txt new file mode 100644 index 0000000000..b310e6f16d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sdb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sdb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x1b + +# CHECK: sdb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x1b + +# CHECK: sdb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x1b + +# CHECK: sdb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x1b + +# CHECK: sdb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x1b + +# CHECK: sdb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x1b + +# CHECK: sdb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x1b diff --git a/test/MC/Disassembler/SystemZ/insn-sdbr.txt b/test/MC/Disassembler/SystemZ/insn-sdbr.txt new file mode 100644 index 0000000000..8722a32395 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sdbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sdbr %f0, %f0 +0xb3 0x1b 0x00 0x00 + +# CHECK: sdbr %f0, %f15 +0xb3 0x1b 0x00 0x0f + +# CHECK: sdbr %f7, %f8 +0xb3 0x1b 0x00 0x78 + +# CHECK: sdbr %f15, %f0 +0xb3 0x1b 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-seb.txt b/test/MC/Disassembler/SystemZ/insn-seb.txt new file mode 100644 index 0000000000..864f692013 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-seb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: seb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x0b + +# CHECK: seb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x0b + +# CHECK: seb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x0b + +# CHECK: seb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x0b + +# CHECK: seb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x0b + +# CHECK: seb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x0b + +# CHECK: seb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x0b diff --git a/test/MC/Disassembler/SystemZ/insn-sebr.txt b/test/MC/Disassembler/SystemZ/insn-sebr.txt new file mode 100644 index 0000000000..289b0afa74 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sebr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sebr %f0, %f0 +0xb3 0x0b 0x00 0x00 + +# CHECK: sebr %f0, %f15 +0xb3 0x0b 0x00 0x0f + +# CHECK: sebr %f7, %f8 +0xb3 0x0b 0x00 0x78 + +# CHECK: sebr %f15, %f0 +0xb3 0x0b 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-sg.txt b/test/MC/Disassembler/SystemZ/insn-sg.txt new file mode 100644 index 0000000000..fdbf1ac60e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x09 + +# CHECK: sg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x09 + +# CHECK: sg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x09 + +# CHECK: sg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x09 + +# CHECK: sg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x09 + +# CHECK: sg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x09 + +# CHECK: sg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x09 + +# CHECK: sg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x09 + +# CHECK: sg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x09 + +# CHECK: sg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x09 diff --git a/test/MC/Disassembler/SystemZ/insn-sgf.txt b/test/MC/Disassembler/SystemZ/insn-sgf.txt new file mode 100644 index 0000000000..f8d6db946d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sgf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x19 + +# CHECK: sgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x19 + +# CHECK: sgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x19 + +# CHECK: sgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x19 + +# CHECK: sgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x19 + +# CHECK: sgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x19 + +# CHECK: sgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x19 + +# CHECK: sgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x19 + +# CHECK: sgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x19 + +# CHECK: sgf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x19 diff --git a/test/MC/Disassembler/SystemZ/insn-sgfr.txt b/test/MC/Disassembler/SystemZ/insn-sgfr.txt new file mode 100644 index 0000000000..1d4f34ed1b --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sgfr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sgfr %r0, %r0 +0xb9 0x19 0x00 0x00 + +# CHECK: sgfr %r0, %r15 +0xb9 0x19 0x00 0x0f + +# CHECK: sgfr %r15, %r0 +0xb9 0x19 0x00 0xf0 + +# CHECK: sgfr %r7, %r8 +0xb9 0x19 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-sgr.txt b/test/MC/Disassembler/SystemZ/insn-sgr.txt new file mode 100644 index 0000000000..084da973b2 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sgr %r0, %r0 +0xb9 0x09 0x00 0x00 + +# CHECK: sgr %r0, %r15 +0xb9 0x09 0x00 0x0f + +# CHECK: sgr %r15, %r0 +0xb9 0x09 0x00 0xf0 + +# CHECK: sgr %r7, %r8 +0xb9 0x09 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-sl.txt b/test/MC/Disassembler/SystemZ/insn-sl.txt new file mode 100644 index 0000000000..0a29f90f51 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sl.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sl %r0, 0 +0x5f 0x00 0x00 0x00 + +# CHECK: sl %r0, 4095 +0x5f 0x00 0x0f 0xff + +# CHECK: sl %r0, 0(%r1) +0x5f 0x00 0x10 0x00 + +# CHECK: sl %r0, 0(%r15) +0x5f 0x00 0xf0 0x00 + +# CHECK: sl %r0, 4095(%r1,%r15) +0x5f 0x01 0xff 0xff + +# CHECK: sl %r0, 4095(%r15,%r1) +0x5f 0x0f 0x1f 0xff + +# CHECK: sl %r15, 0 +0x5f 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-slb.txt b/test/MC/Disassembler/SystemZ/insn-slb.txt new file mode 100644 index 0000000000..b34a914540 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slb.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slb %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x99 + +# CHECK: slb %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x99 + +# CHECK: slb %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x99 + +# CHECK: slb %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x99 + +# CHECK: slb %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x99 + +# CHECK: slb %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x99 + +# CHECK: slb %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x99 + +# CHECK: slb %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x99 + +# CHECK: slb %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x99 + +# CHECK: slb %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x99 diff --git a/test/MC/Disassembler/SystemZ/insn-slbg.txt b/test/MC/Disassembler/SystemZ/insn-slbg.txt new file mode 100644 index 0000000000..e9a918be1c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slbg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slbg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x89 + +# CHECK: slbg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x89 + +# CHECK: slbg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x89 + +# CHECK: slbg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x89 + +# CHECK: slbg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x89 + +# CHECK: slbg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x89 + +# CHECK: slbg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x89 + +# CHECK: slbg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x89 + +# CHECK: slbg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x89 + +# CHECK: slbg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x89 diff --git a/test/MC/Disassembler/SystemZ/insn-slbgr.txt b/test/MC/Disassembler/SystemZ/insn-slbgr.txt new file mode 100644 index 0000000000..4c4b77a98c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slbgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slbgr %r0, %r0 +0xb9 0x89 0x00 0x00 + +# CHECK: slbgr %r0, %r15 +0xb9 0x89 0x00 0x0f + +# CHECK: slbgr %r15, %r0 +0xb9 0x89 0x00 0xf0 + +# CHECK: slbgr %r7, %r8 +0xb9 0x89 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-slbr.txt b/test/MC/Disassembler/SystemZ/insn-slbr.txt new file mode 100644 index 0000000000..83d8cf913f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slbr %r0, %r0 +0xb9 0x99 0x00 0x00 + +# CHECK: slbr %r0, %r15 +0xb9 0x99 0x00 0x0f + +# CHECK: slbr %r15, %r0 +0xb9 0x99 0x00 0xf0 + +# CHECK: slbr %r7, %r8 +0xb9 0x99 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-slfi.txt b/test/MC/Disassembler/SystemZ/insn-slfi.txt new file mode 100644 index 0000000000..ae8f4237ec --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slfi.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slfi %r0, 0 +0xc2 0x05 0x00 0x00 0x00 0x00 + +# CHECK: slfi %r0, 4294967295 +0xc2 0x05 0xff 0xff 0xff 0xff + +# CHECK: slfi %r15, 0 +0xc2 0xf5 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-slg.txt b/test/MC/Disassembler/SystemZ/insn-slg.txt new file mode 100644 index 0000000000..c93412e40e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x0b + +# CHECK: slg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x0b + +# CHECK: slg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x0b + +# CHECK: slg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x0b + +# CHECK: slg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x0b + +# CHECK: slg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x0b + +# CHECK: slg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x0b + +# CHECK: slg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x0b + +# CHECK: slg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x0b + +# CHECK: slg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x0b diff --git a/test/MC/Disassembler/SystemZ/insn-slgf.txt b/test/MC/Disassembler/SystemZ/insn-slgf.txt new file mode 100644 index 0000000000..088aac6c53 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slgf.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x1b + +# CHECK: slgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x1b + +# CHECK: slgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x1b + +# CHECK: slgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x1b + +# CHECK: slgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x1b + +# CHECK: slgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x1b + +# CHECK: slgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x1b + +# CHECK: slgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x1b + +# CHECK: slgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x1b + +# CHECK: slgf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x1b diff --git a/test/MC/Disassembler/SystemZ/insn-slgfi.txt b/test/MC/Disassembler/SystemZ/insn-slgfi.txt new file mode 100644 index 0000000000..e618210e7f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slgfi.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slgfi %r0, 0 +0xc2 0x04 0x00 0x00 0x00 0x00 + +# CHECK: slgfi %r0, 4294967295 +0xc2 0x04 0xff 0xff 0xff 0xff + +# CHECK: slgfi %r15, 0 +0xc2 0xf4 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-slgfr.txt b/test/MC/Disassembler/SystemZ/insn-slgfr.txt new file mode 100644 index 0000000000..4f881bf0f3 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slgfr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slgfr %r0, %r0 +0xb9 0x1b 0x00 0x00 + +# CHECK: slgfr %r0, %r15 +0xb9 0x1b 0x00 0x0f + +# CHECK: slgfr %r15, %r0 +0xb9 0x1b 0x00 0xf0 + +# CHECK: slgfr %r7, %r8 +0xb9 0x1b 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-slgr.txt b/test/MC/Disassembler/SystemZ/insn-slgr.txt new file mode 100644 index 0000000000..efea07b0c7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slgr %r0, %r0 +0xb9 0x0b 0x00 0x00 + +# CHECK: slgr %r0, %r15 +0xb9 0x0b 0x00 0x0f + +# CHECK: slgr %r15, %r0 +0xb9 0x0b 0x00 0xf0 + +# CHECK: slgr %r7, %r8 +0xb9 0x0b 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-sll.txt b/test/MC/Disassembler/SystemZ/insn-sll.txt new file mode 100644 index 0000000000..a31b5c7241 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sll.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sll %r0, 0 +0x89 0x00 0x00 0x00 + +# CHECK: sll %r7, 0 +0x89 0x70 0x00 0x00 + +# CHECK: sll %r15, 0 +0x89 0xf0 0x00 0x00 + +# CHECK: sll %r0, 4095 +0x89 0x00 0x0f 0xff + +# CHECK: sll %r0, 0(%r1) +0x89 0x00 0x10 0x00 + +# CHECK: sll %r0, 0(%r15) +0x89 0x00 0xf0 0x00 + +# CHECK: sll %r0, 4095(%r1) +0x89 0x00 0x1f 0xff + +# CHECK: sll %r0, 4095(%r15) +0x89 0x00 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-sllg.txt b/test/MC/Disassembler/SystemZ/insn-sllg.txt new file mode 100644 index 0000000000..b4204ac88a --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sllg.txt @@ -0,0 +1,36 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sllg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x0d + +# CHECK: sllg %r15, %r1, 0 +0xeb 0xf1 0x00 0x00 0x00 0x0d + +# CHECK: sllg %r1, %r15, 0 +0xeb 0x1f 0x00 0x00 0x00 0x0d + +# CHECK: sllg %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0x0d + +# CHECK: sllg %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x0d + +# CHECK: sllg %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x0d + +# CHECK: sllg %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x0d + +# CHECK: sllg %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x0d + +# CHECK: sllg %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x0d + +# CHECK: sllg %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x0d + +# CHECK: sllg %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x0d + +# CHECK: sllg %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x0d diff --git a/test/MC/Disassembler/SystemZ/insn-slr.txt b/test/MC/Disassembler/SystemZ/insn-slr.txt new file mode 100644 index 0000000000..6a98744be6 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-slr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: slr %r0, %r0 +0x1f 0x00 + +# CHECK: slr %r0, %r15 +0x1f 0x0f + +# CHECK: slr %r15, %r0 +0x1f 0xf0 + +# CHECK: slr %r7, %r8 +0x1f 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-sly.txt b/test/MC/Disassembler/SystemZ/insn-sly.txt new file mode 100644 index 0000000000..a5e4926121 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sly.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sly %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x5f + +# CHECK: sly %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x5f + +# CHECK: sly %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x5f + +# CHECK: sly %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x5f + +# CHECK: sly %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x5f + +# CHECK: sly %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x5f + +# CHECK: sly %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x5f + +# CHECK: sly %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x5f + +# CHECK: sly %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x5f + +# CHECK: sly %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x5f diff --git a/test/MC/Disassembler/SystemZ/insn-sqdb.txt b/test/MC/Disassembler/SystemZ/insn-sqdb.txt new file mode 100644 index 0000000000..1e4aad4594 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sqdb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sqdb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x15 + +# CHECK: sqdb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x15 + +# CHECK: sqdb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x15 + +# CHECK: sqdb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x15 + +# CHECK: sqdb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x15 + +# CHECK: sqdb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x15 + +# CHECK: sqdb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x15 diff --git a/test/MC/Disassembler/SystemZ/insn-sqdbr.txt b/test/MC/Disassembler/SystemZ/insn-sqdbr.txt new file mode 100644 index 0000000000..3369e3267f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sqdbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sqdbr %f0, %f0 +0xb3 0x15 0x00 0x00 + +# CHECK: sqdbr %f0, %f15 +0xb3 0x15 0x00 0x0f + +# CHECK: sqdbr %f7, %f8 +0xb3 0x15 0x00 0x78 + +# CHECK: sqdbr %f15, %f0 +0xb3 0x15 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-sqeb.txt b/test/MC/Disassembler/SystemZ/insn-sqeb.txt new file mode 100644 index 0000000000..18541df671 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sqeb.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sqeb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x14 + +# CHECK: sqeb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x14 + +# CHECK: sqeb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x14 + +# CHECK: sqeb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x14 + +# CHECK: sqeb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x14 + +# CHECK: sqeb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x14 + +# CHECK: sqeb %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x14 diff --git a/test/MC/Disassembler/SystemZ/insn-sqebr.txt b/test/MC/Disassembler/SystemZ/insn-sqebr.txt new file mode 100644 index 0000000000..38bafdea52 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sqebr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sqebr %f0, %f0 +0xb3 0x14 0x00 0x00 + +# CHECK: sqebr %f0, %f15 +0xb3 0x14 0x00 0x0f + +# CHECK: sqebr %f7, %f8 +0xb3 0x14 0x00 0x78 + +# CHECK: sqebr %f15, %f0 +0xb3 0x14 0x00 0xf0 diff --git a/test/MC/Disassembler/SystemZ/insn-sqxbr.txt b/test/MC/Disassembler/SystemZ/insn-sqxbr.txt new file mode 100644 index 0000000000..19fb61d116 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sqxbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sqxbr %f0, %f0 +0xb3 0x16 0x00 0x00 + +# CHECK: sqxbr %f0, %f13 +0xb3 0x16 0x00 0x0d + +# CHECK: sqxbr %f8, %f8 +0xb3 0x16 0x00 0x88 + +# CHECK: sqxbr %f13, %f0 +0xb3 0x16 0x00 0xd0 diff --git a/test/MC/Disassembler/SystemZ/insn-sr.txt b/test/MC/Disassembler/SystemZ/insn-sr.txt new file mode 100644 index 0000000000..e871d97d50 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sr %r0, %r0 +0x1b 0x00 + +# CHECK: sr %r0, %r15 +0x1b 0x0f + +# CHECK: sr %r15, %r0 +0x1b 0xf0 + +# CHECK: sr %r7, %r8 +0x1b 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-sra.txt b/test/MC/Disassembler/SystemZ/insn-sra.txt new file mode 100644 index 0000000000..796b9097ff --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sra.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sra %r0, 0 +0x8a 0x00 0x00 0x00 + +# CHECK: sra %r7, 0 +0x8a 0x70 0x00 0x00 + +# CHECK: sra %r15, 0 +0x8a 0xf0 0x00 0x00 + +# CHECK: sra %r0, 4095 +0x8a 0x00 0x0f 0xff + +# CHECK: sra %r0, 0(%r1) +0x8a 0x00 0x10 0x00 + +# CHECK: sra %r0, 0(%r15) +0x8a 0x00 0xf0 0x00 + +# CHECK: sra %r0, 4095(%r1) +0x8a 0x00 0x1f 0xff + +# CHECK: sra %r0, 4095(%r15) +0x8a 0x00 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-srag.txt b/test/MC/Disassembler/SystemZ/insn-srag.txt new file mode 100644 index 0000000000..38afa43c8f --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-srag.txt @@ -0,0 +1,36 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: srag %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x0a + +# CHECK: srag %r15, %r1, 0 +0xeb 0xf1 0x00 0x00 0x00 0x0a + +# CHECK: srag %r1, %r15, 0 +0xeb 0x1f 0x00 0x00 0x00 0x0a + +# CHECK: srag %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0x0a + +# CHECK: srag %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x0a + +# CHECK: srag %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x0a + +# CHECK: srag %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x0a + +# CHECK: srag %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x0a + +# CHECK: srag %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x0a + +# CHECK: srag %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x0a + +# CHECK: srag %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x0a + +# CHECK: srag %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x0a diff --git a/test/MC/Disassembler/SystemZ/insn-srl.txt b/test/MC/Disassembler/SystemZ/insn-srl.txt new file mode 100644 index 0000000000..c1c500ba92 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-srl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: srl %r0, 0 +0x88 0x00 0x00 0x00 + +# CHECK: srl %r7, 0 +0x88 0x70 0x00 0x00 + +# CHECK: srl %r15, 0 +0x88 0xf0 0x00 0x00 + +# CHECK: srl %r0, 4095 +0x88 0x00 0x0f 0xff + +# CHECK: srl %r0, 0(%r1) +0x88 0x00 0x10 0x00 + +# CHECK: srl %r0, 0(%r15) +0x88 0x00 0xf0 0x00 + +# CHECK: srl %r0, 4095(%r1) +0x88 0x00 0x1f 0xff + +# CHECK: srl %r0, 4095(%r15) +0x88 0x00 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-srlg.txt b/test/MC/Disassembler/SystemZ/insn-srlg.txt new file mode 100644 index 0000000000..84cf968325 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-srlg.txt @@ -0,0 +1,36 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: srlg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x0c + +# CHECK: srlg %r15, %r1, 0 +0xeb 0xf1 0x00 0x00 0x00 0x0c + +# CHECK: srlg %r1, %r15, 0 +0xeb 0x1f 0x00 0x00 0x00 0x0c + +# CHECK: srlg %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0x0c + +# CHECK: srlg %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x0c + +# CHECK: srlg %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x0c + +# CHECK: srlg %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x0c + +# CHECK: srlg %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x0c + +# CHECK: srlg %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x0c + +# CHECK: srlg %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x0c + +# CHECK: srlg %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x0c + +# CHECK: srlg %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x0c diff --git a/test/MC/Disassembler/SystemZ/insn-st.txt b/test/MC/Disassembler/SystemZ/insn-st.txt new file mode 100644 index 0000000000..3fcc391aac --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-st.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: st %r0, 0 +0x50 0x00 0x00 0x00 + +# CHECK: st %r0, 4095 +0x50 0x00 0x0f 0xff + +# CHECK: st %r0, 0(%r1) +0x50 0x00 0x10 0x00 + +# CHECK: st %r0, 0(%r15) +0x50 0x00 0xf0 0x00 + +# CHECK: st %r0, 4095(%r1,%r15) +0x50 0x01 0xff 0xff + +# CHECK: st %r0, 4095(%r15,%r1) +0x50 0x0f 0x1f 0xff + +# CHECK: st %r15, 0 +0x50 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-stc.txt b/test/MC/Disassembler/SystemZ/insn-stc.txt new file mode 100644 index 0000000000..20cc349259 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-stc.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: stc %r0, 0 +0x42 0x00 0x00 0x00 + +# CHECK: stc %r0, 4095 +0x42 0x00 0x0f 0xff + +# CHECK: stc %r0, 0(%r1) +0x42 0x00 0x10 0x00 + +# CHECK: stc %r0, 0(%r15) +0x42 0x00 0xf0 0x00 + +# CHECK: stc %r0, 4095(%r1,%r15) +0x42 0x01 0xff 0xff + +# CHECK: stc %r0, 4095(%r15,%r1) +0x42 0x0f 0x1f 0xff + +# CHECK: stc %r15, 0 +0x42 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-stcy.txt b/test/MC/Disassembler/SystemZ/insn-stcy.txt new file mode 100644 index 0000000000..8d4f419338 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-stcy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: stcy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x72 + +# CHECK: stcy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x72 + +# CHECK: stcy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x72 + +# CHECK: stcy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x72 + +# CHECK: stcy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x72 + +# CHECK: stcy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x72 + +# CHECK: stcy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x72 + +# CHECK: stcy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x72 + +# CHECK: stcy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x72 + +# CHECK: stcy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x72 diff --git a/test/MC/Disassembler/SystemZ/insn-std.txt b/test/MC/Disassembler/SystemZ/insn-std.txt new file mode 100644 index 0000000000..7a455833b9 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-std.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: std %f0, 0 +0x60 0x00 0x00 0x00 + +# CHECK: std %f0, 4095 +0x60 0x00 0x0f 0xff + +# CHECK: std %f0, 0(%r1) +0x60 0x00 0x10 0x00 + +# CHECK: std %f0, 0(%r15) +0x60 0x00 0xf0 0x00 + +# CHECK: std %f0, 4095(%r1,%r15) +0x60 0x01 0xff 0xff + +# CHECK: std %f0, 4095(%r15,%r1) +0x60 0x0f 0x1f 0xff + +# CHECK: std %f15, 0 +0x60 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-stdy.txt b/test/MC/Disassembler/SystemZ/insn-stdy.txt new file mode 100644 index 0000000000..c414c868c0 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-stdy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: stdy %f0, -524288 +0xed 0x00 0x00 0x00 0x80 0x67 + +# CHECK: stdy %f0, -1 +0xed 0x00 0x0f 0xff 0xff 0x67 + +# CHECK: stdy %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x67 + +# CHECK: stdy %f0, 1 +0xed 0x00 0x00 0x01 0x00 0x67 + +# CHECK: stdy %f0, 524287 +0xed 0x00 0x0f 0xff 0x7f 0x67 + +# CHECK: stdy %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x67 + +# CHECK: stdy %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x67 + +# CHECK: stdy %f0, 524287(%r1,%r15) +0xed 0x01 0xff 0xff 0x7f 0x67 + +# CHECK: stdy %f0, 524287(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x7f 0x67 + +# CHECK: stdy %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x67 diff --git a/test/MC/Disassembler/SystemZ/insn-ste.txt b/test/MC/Disassembler/SystemZ/insn-ste.txt new file mode 100644 index 0000000000..2ae3ede171 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-ste.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: ste %f0, 0 +0x70 0x00 0x00 0x00 + +# CHECK: ste %f0, 4095 +0x70 0x00 0x0f 0xff + +# CHECK: ste %f0, 0(%r1) +0x70 0x00 0x10 0x00 + +# CHECK: ste %f0, 0(%r15) +0x70 0x00 0xf0 0x00 + +# CHECK: ste %f0, 4095(%r1,%r15) +0x70 0x01 0xff 0xff + +# CHECK: ste %f0, 4095(%r15,%r1) +0x70 0x0f 0x1f 0xff + +# CHECK: ste %f15, 0 +0x70 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-stey.txt b/test/MC/Disassembler/SystemZ/insn-stey.txt new file mode 100644 index 0000000000..f9f0c93bb0 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-stey.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: stey %f0, -524288 +0xed 0x00 0x00 0x00 0x80 0x66 + +# CHECK: stey %f0, -1 +0xed 0x00 0x0f 0xff 0xff 0x66 + +# CHECK: stey %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x66 + +# CHECK: stey %f0, 1 +0xed 0x00 0x00 0x01 0x00 0x66 + +# CHECK: stey %f0, 524287 +0xed 0x00 0x0f 0xff 0x7f 0x66 + +# CHECK: stey %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x66 + +# CHECK: stey %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x66 + +# CHECK: stey %f0, 524287(%r1,%r15) +0xed 0x01 0xff 0xff 0x7f 0x66 + +# CHECK: stey %f0, 524287(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x7f 0x66 + +# CHECK: stey %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x66 diff --git a/test/MC/Disassembler/SystemZ/insn-stg.txt b/test/MC/Disassembler/SystemZ/insn-stg.txt new file mode 100644 index 0000000000..6aca5c8311 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-stg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: stg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x24 + +# CHECK: stg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x24 + +# CHECK: stg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x24 + +# CHECK: stg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x24 + +# CHECK: stg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x24 + +# CHECK: stg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x24 + +# CHECK: stg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x24 + +# CHECK: stg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x24 + +# CHECK: stg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x24 + +# CHECK: stg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x24 diff --git a/test/MC/Disassembler/SystemZ/insn-stgrl.txt b/test/MC/Disassembler/SystemZ/insn-stgrl.txt new file mode 100644 index 0000000000..599fdb9954 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-stgrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: stgrl %r0, 0x0 +0xc4 0x0b 0x00 0x00 0x00 0x00 + +# CHECK: stgrl %r15, 0x6 +0xc4 0xfb 0x00 0x00 0x00 0x00 + +# CHECK: stgrl %r0, 0xa +0xc4 0x0b 0xff 0xff 0xff 0xff + +# CHECK: stgrl %r15, 0x10 +0xc4 0xfb 0xff 0xff 0xff 0xff + +# CHECK: stgrl %r0, 0xffffffff00000018 +0xc4 0x0b 0x80 0x00 0x00 0x00 + +# CHECK: stgrl %r15, 0xffffffff0000001e +0xc4 0xfb 0x80 0x00 0x00 0x00 + +# CHECK: stgrl %r0, 0x100000022 +0xc4 0x0b 0x7f 0xff 0xff 0xff + +# CHECK: stgrl %r15, 0x100000028 +0xc4 0xfb 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-sth.txt b/test/MC/Disassembler/SystemZ/insn-sth.txt new file mode 100644 index 0000000000..448a0a88f7 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sth.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sth %r0, 0 +0x40 0x00 0x00 0x00 + +# CHECK: sth %r0, 4095 +0x40 0x00 0x0f 0xff + +# CHECK: sth %r0, 0(%r1) +0x40 0x00 0x10 0x00 + +# CHECK: sth %r0, 0(%r15) +0x40 0x00 0xf0 0x00 + +# CHECK: sth %r0, 4095(%r1,%r15) +0x40 0x01 0xff 0xff + +# CHECK: sth %r0, 4095(%r15,%r1) +0x40 0x0f 0x1f 0xff + +# CHECK: sth %r15, 0 +0x40 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-sthrl.txt b/test/MC/Disassembler/SystemZ/insn-sthrl.txt new file mode 100644 index 0000000000..544ac0cfae --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sthrl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sthrl %r0, 0x0 +0xc4 0x07 0x00 0x00 0x00 0x00 + +# CHECK: sthrl %r15, 0x6 +0xc4 0xf7 0x00 0x00 0x00 0x00 + +# CHECK: sthrl %r0, 0xa +0xc4 0x07 0xff 0xff 0xff 0xff + +# CHECK: sthrl %r15, 0x10 +0xc4 0xf7 0xff 0xff 0xff 0xff + +# CHECK: sthrl %r0, 0xffffffff00000018 +0xc4 0x07 0x80 0x00 0x00 0x00 + +# CHECK: sthrl %r15, 0xffffffff0000001e +0xc4 0xf7 0x80 0x00 0x00 0x00 + +# CHECK: sthrl %r0, 0x100000022 +0xc4 0x07 0x7f 0xff 0xff 0xff + +# CHECK: sthrl %r15, 0x100000028 +0xc4 0xf7 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-sthy.txt b/test/MC/Disassembler/SystemZ/insn-sthy.txt new file mode 100644 index 0000000000..d3b2e49b9c --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sthy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sthy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x70 + +# CHECK: sthy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x70 + +# CHECK: sthy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x70 + +# CHECK: sthy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x70 + +# CHECK: sthy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x70 + +# CHECK: sthy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x70 + +# CHECK: sthy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x70 + +# CHECK: sthy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x70 + +# CHECK: sthy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x70 + +# CHECK: sthy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x70 diff --git a/test/MC/Disassembler/SystemZ/insn-stmg.txt b/test/MC/Disassembler/SystemZ/insn-stmg.txt new file mode 100644 index 0000000000..33184631b8 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-stmg.txt @@ -0,0 +1,39 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: stmg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x24 + +# CHECK: stmg %r0, %r15, 0 +0xeb 0x0f 0x00 0x00 0x00 0x24 + +# CHECK: stmg %r14, %r15, 0 +0xeb 0xef 0x00 0x00 0x00 0x24 + +# CHECK: stmg %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0x24 + +# CHECK: stmg %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x24 + +# CHECK: stmg %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x24 + +# CHECK: stmg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x24 + +# CHECK: stmg %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x24 + +# CHECK: stmg %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x24 + +# CHECK: stmg %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x24 + +# CHECK: stmg %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x24 + +# CHECK: stmg %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x24 + +# CHECK: stmg %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x24 diff --git a/test/MC/Disassembler/SystemZ/insn-strl.txt b/test/MC/Disassembler/SystemZ/insn-strl.txt new file mode 100644 index 0000000000..0468d3a262 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-strl.txt @@ -0,0 +1,24 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: strl %r0, 0x0 +0xc4 0x0f 0x00 0x00 0x00 0x00 + +# CHECK: strl %r15, 0x6 +0xc4 0xff 0x00 0x00 0x00 0x00 + +# CHECK: strl %r0, 0xa +0xc4 0x0f 0xff 0xff 0xff 0xff + +# CHECK: strl %r15, 0x10 +0xc4 0xff 0xff 0xff 0xff 0xff + +# CHECK: strl %r0, 0xffffffff00000018 +0xc4 0x0f 0x80 0x00 0x00 0x00 + +# CHECK: strl %r15, 0xffffffff0000001e +0xc4 0xff 0x80 0x00 0x00 0x00 + +# CHECK: strl %r0, 0x100000022 +0xc4 0x0f 0x7f 0xff 0xff 0xff + +# CHECK: strl %r15, 0x100000028 +0xc4 0xff 0x7f 0xff 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-strv.txt b/test/MC/Disassembler/SystemZ/insn-strv.txt new file mode 100644 index 0000000000..d9629ea573 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-strv.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: strv %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x3e + +# CHECK: strv %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x3e + +# CHECK: strv %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x3e + +# CHECK: strv %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x3e + +# CHECK: strv %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x3e + +# CHECK: strv %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x3e + +# CHECK: strv %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x3e + +# CHECK: strv %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x3e + +# CHECK: strv %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x3e + +# CHECK: strv %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x3e diff --git a/test/MC/Disassembler/SystemZ/insn-strvg.txt b/test/MC/Disassembler/SystemZ/insn-strvg.txt new file mode 100644 index 0000000000..43cfc01040 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-strvg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: strvg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x2f + +# CHECK: strvg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x2f + +# CHECK: strvg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x2f + +# CHECK: strvg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x2f + +# CHECK: strvg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x2f + +# CHECK: strvg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x2f + +# CHECK: strvg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x2f + +# CHECK: strvg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x2f + +# CHECK: strvg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x2f + +# CHECK: strvg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x2f diff --git a/test/MC/Disassembler/SystemZ/insn-sty.txt b/test/MC/Disassembler/SystemZ/insn-sty.txt new file mode 100644 index 0000000000..faee6638a1 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sty.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sty %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x50 + +# CHECK: sty %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x50 + +# CHECK: sty %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x50 + +# CHECK: sty %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x50 + +# CHECK: sty %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x50 + +# CHECK: sty %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x50 + +# CHECK: sty %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x50 + +# CHECK: sty %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x50 + +# CHECK: sty %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x50 + +# CHECK: sty %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x50 diff --git a/test/MC/Disassembler/SystemZ/insn-sxbr.txt b/test/MC/Disassembler/SystemZ/insn-sxbr.txt new file mode 100644 index 0000000000..9fc1e4d866 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sxbr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sxbr %f0, %f0 +0xb3 0x4b 0x00 0x00 + +# CHECK: sxbr %f0, %f13 +0xb3 0x4b 0x00 0x0d + +# CHECK: sxbr %f8, %f8 +0xb3 0x4b 0x00 0x88 + +# CHECK: sxbr %f13, %f0 +0xb3 0x4b 0x00 0xd0 diff --git a/test/MC/Disassembler/SystemZ/insn-sy.txt b/test/MC/Disassembler/SystemZ/insn-sy.txt new file mode 100644 index 0000000000..927f64b34d --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-sy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: sy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x5b + +# CHECK: sy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x5b + +# CHECK: sy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x5b + +# CHECK: sy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x5b + +# CHECK: sy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x5b + +# CHECK: sy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x5b + +# CHECK: sy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x5b + +# CHECK: sy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x5b + +# CHECK: sy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x5b + +# CHECK: sy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x5b diff --git a/test/MC/Disassembler/SystemZ/insn-x.txt b/test/MC/Disassembler/SystemZ/insn-x.txt new file mode 100644 index 0000000000..90dc47b198 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-x.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: x %r0, 0 +0x57 0x00 0x00 0x00 + +# CHECK: x %r0, 4095 +0x57 0x00 0x0f 0xff + +# CHECK: x %r0, 0(%r1) +0x57 0x00 0x10 0x00 + +# CHECK: x %r0, 0(%r15) +0x57 0x00 0xf0 0x00 + +# CHECK: x %r0, 4095(%r1,%r15) +0x57 0x01 0xff 0xff + +# CHECK: x %r0, 4095(%r15,%r1) +0x57 0x0f 0x1f 0xff + +# CHECK: x %r15, 0 +0x57 0xf0 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-xg.txt b/test/MC/Disassembler/SystemZ/insn-xg.txt new file mode 100644 index 0000000000..20838d2178 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-xg.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: xg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x82 + +# CHECK: xg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x82 + +# CHECK: xg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x82 + +# CHECK: xg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x82 + +# CHECK: xg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x82 + +# CHECK: xg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x82 + +# CHECK: xg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x82 + +# CHECK: xg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x82 + +# CHECK: xg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x82 + +# CHECK: xg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x82 diff --git a/test/MC/Disassembler/SystemZ/insn-xgr.txt b/test/MC/Disassembler/SystemZ/insn-xgr.txt new file mode 100644 index 0000000000..c9f4910e3e --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-xgr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: xgr %r0, %r0 +0xb9 0x82 0x00 0x00 + +# CHECK: xgr %r0, %r15 +0xb9 0x82 0x00 0x0f + +# CHECK: xgr %r15, %r0 +0xb9 0x82 0x00 0xf0 + +# CHECK: xgr %r7, %r8 +0xb9 0x82 0x00 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-xi.txt b/test/MC/Disassembler/SystemZ/insn-xi.txt new file mode 100644 index 0000000000..ef201386d3 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-xi.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: xi 0, 0 +0x97 0x00 0x00 0x00 + +# CHECK: xi 4095, 0 +0x97 0x00 0x0f 0xff + +# CHECK: xi 0, 255 +0x97 0xff 0x00 0x00 + +# CHECK: xi 0(%r1), 42 +0x97 0x2a 0x10 0x00 + +# CHECK: xi 0(%r15), 42 +0x97 0x2a 0xf0 0x00 + +# CHECK: xi 4095(%r1), 42 +0x97 0x2a 0x1f 0xff + +# CHECK: xi 4095(%r15), 42 +0x97 0x2a 0xff 0xff diff --git a/test/MC/Disassembler/SystemZ/insn-xihf.txt b/test/MC/Disassembler/SystemZ/insn-xihf.txt new file mode 100644 index 0000000000..e0231ce3de --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-xihf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: xihf %r0, 0 +0xc0 0x06 0x00 0x00 0x00 0x00 + +# CHECK: xihf %r0, 4294967295 +0xc0 0x06 0xff 0xff 0xff 0xff + +# CHECK: xihf %r15, 0 +0xc0 0xf6 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-xilf.txt b/test/MC/Disassembler/SystemZ/insn-xilf.txt new file mode 100644 index 0000000000..bda8ab0c08 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-xilf.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: xilf %r0, 0 +0xc0 0x07 0x00 0x00 0x00 0x00 + +# CHECK: xilf %r0, 4294967295 +0xc0 0x07 0xff 0xff 0xff 0xff + +# CHECK: xilf %r15, 0 +0xc0 0xf7 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/insn-xiy.txt b/test/MC/Disassembler/SystemZ/insn-xiy.txt new file mode 100644 index 0000000000..cc60ebb6f4 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-xiy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: xiy -524288, 0 +0xeb 0x00 0x00 0x00 0x80 0x57 + +# CHECK: xiy -1, 0 +0xeb 0x00 0x0f 0xff 0xff 0x57 + +# CHECK: xiy 0, 0 +0xeb 0x00 0x00 0x00 0x00 0x57 + +# CHECK: xiy 1, 0 +0xeb 0x00 0x00 0x01 0x00 0x57 + +# CHECK: xiy 524287, 0 +0xeb 0x00 0x0f 0xff 0x7f 0x57 + +# CHECK: xiy 0, 255 +0xeb 0xff 0x00 0x00 0x00 0x57 + +# CHECK: xiy 0(%r1), 42 +0xeb 0x2a 0x10 0x00 0x00 0x57 + +# CHECK: xiy 0(%r15), 42 +0xeb 0x2a 0xf0 0x00 0x00 0x57 + +# CHECK: xiy 524287(%r1), 42 +0xeb 0x2a 0x1f 0xff 0x7f 0x57 + +# CHECK: xiy 524287(%r15), 42 +0xeb 0x2a 0xff 0xff 0x7f 0x57 diff --git a/test/MC/Disassembler/SystemZ/insn-xr.txt b/test/MC/Disassembler/SystemZ/insn-xr.txt new file mode 100644 index 0000000000..70cb0036c3 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-xr.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: xr %r0, %r0 +0x17 0x00 + +# CHECK: xr %r0, %r15 +0x17 0x0f + +# CHECK: xr %r15, %r0 +0x17 0xf0 + +# CHECK: xr %r7, %r8 +0x17 0x78 diff --git a/test/MC/Disassembler/SystemZ/insn-xy.txt b/test/MC/Disassembler/SystemZ/insn-xy.txt new file mode 100644 index 0000000000..dea20278c5 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insn-xy.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# CHECK: xy %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x57 + +# CHECK: xy %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x57 + +# CHECK: xy %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x57 + +# CHECK: xy %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x57 + +# CHECK: xy %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x57 + +# CHECK: xy %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x57 + +# CHECK: xy %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x57 + +# CHECK: xy %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x57 + +# CHECK: xy %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x57 + +# CHECK: xy %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x57 diff --git a/test/MC/Disassembler/SystemZ/invalid-regs-01.txt b/test/MC/Disassembler/SystemZ/invalid-regs-01.txt new file mode 100644 index 0000000000..12440677ba --- /dev/null +++ b/test/MC/Disassembler/SystemZ/invalid-regs-01.txt @@ -0,0 +1,22 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu < %s 2>&1 | FileCheck %s + +# This would be "axbr %f14, %f0", but %r14 is invalid. +# +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: 0xb3 0x4a 0x00 0xe0 +# CHECK-NEXT: ^ +0xb3 0x4a 0x00 0xe0 + +# This would be "axbr %f0, %f2", but %f2 is invalid. +# +# CHECK-NEXT: warning: invalid instruction encoding +# CHECK-NEXT: 0xb3 0x4a 0x00 0x02 +# CHECK-NEXT: ^ +0xb3 0x4a 0x00 0x02 + +# This would be "dlr %r1, %r8", but %r1 is invalid. +# +# CHECK-NEXT: warning: invalid instruction encoding +# CHECK-NEXT: 0xb9 0x97 0x00 0x18 +# CHECK-NEXT: ^ +0xb9 0x97 0x00 0x18 diff --git a/test/MC/Disassembler/SystemZ/lit.local.cfg b/test/MC/Disassembler/SystemZ/lit.local.cfg new file mode 100644 index 0000000000..1da00eaef3 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.txt'] + +targets = set(config.root.targets_to_build.split()) +if not 'SystemZ' in targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/SystemZ/trunc-01.txt b/test/MC/Disassembler/SystemZ/trunc-01.txt new file mode 100644 index 0000000000..336142ddea --- /dev/null +++ b/test/MC/Disassembler/SystemZ/trunc-01.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu 2>&1 | FileCheck %s +# Every instruction must be at least two bytes long. +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: 0xc4 +0xc4 diff --git a/test/MC/Disassembler/SystemZ/trunc-02.txt b/test/MC/Disassembler/SystemZ/trunc-02.txt new file mode 100644 index 0000000000..e1e20516e8 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/trunc-02.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu 2>&1 | FileCheck %s +# If the top bits are 0b10, the instruction must be 4 bytes long. +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: 0xb9 0x08 0x00 +0xb9 0x08 0x00 diff --git a/test/MC/Disassembler/SystemZ/trunc-03.txt b/test/MC/Disassembler/SystemZ/trunc-03.txt new file mode 100644 index 0000000000..94d0c37896 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/trunc-03.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu 2>&1 | FileCheck %s +# If the top bits are 0b11, the instruction must be 6 bytes long. +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: 0xed 0x00 0x00 0x00 0x00 +0xed 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/unmapped-01.txt b/test/MC/Disassembler/SystemZ/unmapped-01.txt new file mode 100644 index 0000000000..9379ff6319 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/unmapped-01.txt @@ -0,0 +1,32 @@ +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu 2>&1 | FileCheck %s + +# An unmapped 2-byte instruction +# +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: 0x01 +# CHECK-NEXT: ^ +0x01 +0x10 + +# An unmapped 4-byte instruction +# +# CHECK-NEXT: warning: invalid instruction encoding +# CHECK-NEXT: 0x53 +# CHECK-NEXT: ^ +0x53 +0x00 0x00 0x00 + +# An unmapped 6-byte instruction +# +# CHECK-NEXT: warning: invalid instruction encoding +# CHECK-NEXT: 0xff +# CHECK-NEXT: ^ +0xff +0x00 0x00 0x00 0x00 0x00 + +# A trailing zero (also unmapped) +# +# CHECK-NEXT: warning: invalid instruction encoding +# CHECK-NEXT: 0x00 +# CHECK-NEXT: ^ +0x00 -- cgit v1.2.3 From 15cf700b415f6477fa4152904b8e28cfa501d206 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Tue, 14 May 2013 13:02:37 +0000 Subject: Declare __clear_cache. GCC declares __clear_cache in the gnu modes (-std=gnu++98, -std=gnu++11), but not in the strict modes (-std=c++98, -std=c++11). This patch declares it and therefore fixes the build when using one of the strict modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181785 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Unix/Memory.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/Support/Unix/Memory.inc b/lib/Support/Unix/Memory.inc index 72a8af621d..d56c9e4b38 100644 --- a/lib/Support/Unix/Memory.inc +++ b/lib/Support/Unix/Memory.inc @@ -33,6 +33,7 @@ #endif extern "C" void sys_icache_invalidate(const void *Addr, size_t len); +extern "C" void __clear_cache(char *, char*); namespace { -- cgit v1.2.3 From 8305acb20062ffa37d1579d0063794432c01c26b Mon Sep 17 00:00:00 2001 From: Duncan Sands Date: Tue, 14 May 2013 13:29:16 +0000 Subject: Get the unittests compiling when building with cmake and the setting -DLLVM_ENABLE_THREADS=false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181788 91177308-0d34-0410-b5e6-96231b3b80d8 --- unittests/Support/ManagedStatic.cpp | 3 ++- utils/unittest/CMakeLists.txt | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/unittests/Support/ManagedStatic.cpp b/unittests/Support/ManagedStatic.cpp index 8ddad38ecf..1497f4e340 100644 --- a/unittests/Support/ManagedStatic.cpp +++ b/unittests/Support/ManagedStatic.cpp @@ -19,7 +19,8 @@ using namespace llvm; namespace { -#if defined(HAVE_PTHREAD_H) && !__has_feature(memory_sanitizer) +#if LLVM_ENABLE_THREADS != 0 && defined(HAVE_PTHREAD_H) && \ + !__has_feature(memory_sanitizer) namespace test1 { llvm::ManagedStatic ms; void *helper(void*) { diff --git a/utils/unittest/CMakeLists.txt b/utils/unittest/CMakeLists.txt index 70ed35df2e..8bdfee15c1 100644 --- a/utils/unittest/CMakeLists.txt +++ b/utils/unittest/CMakeLists.txt @@ -27,6 +27,10 @@ endif() set(LLVM_REQUIRES_RTTI 1) add_definitions( -DGTEST_HAS_RTTI=0 ) +if (NOT LLVM_ENABLE_THREADS) + add_definitions( -DGTEST_HAS_PTHREAD=0 ) +endif() + # Visual Studio 2012 only supports up to 8 template parameters in # std::tr1::tuple by default, but gtest requires 10 if(MSVC AND MSVC_VERSION EQUAL 1700) -- cgit v1.2.3 From ec0379224523bbf72d39a004b4db9a710bfc0cef Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 14 May 2013 14:42:56 +0000 Subject: R600/SI: Add processor type for Hainan asic Patch by: Alex Deucher Reviewed-by: Tom Stellard Signed-off-by: Alex Deucher NOTE: This is a candidate for the 3.3 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181792 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDILDeviceInfo.cpp | 3 ++- lib/Target/R600/Processors.td | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/Target/R600/AMDILDeviceInfo.cpp b/lib/Target/R600/AMDILDeviceInfo.cpp index 178795936a..126514b976 100644 --- a/lib/Target/R600/AMDILDeviceInfo.cpp +++ b/lib/Target/R600/AMDILDeviceInfo.cpp @@ -81,7 +81,8 @@ AMDGPUDevice* getDeviceFromName(const std::string &deviceName, return new AMDGPUNIDevice(ptr); } else if (deviceName == "SI" || deviceName == "tahiti" || deviceName == "pitcairn" || - deviceName == "verde" || deviceName == "oland") { + deviceName == "verde" || deviceName == "oland" || + deviceName == "hainan") { return new AMDGPUSIDevice(ptr); } else { #if DEBUG diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td index 5ee1c0d8ae..0cbe919d81 100644 --- a/lib/Target/R600/Processors.td +++ b/lib/Target/R600/Processors.td @@ -45,3 +45,4 @@ def : Proc<"tahiti", SI_Itin, [Feature64BitPtr, FeatureFP64]>; def : Proc<"pitcairn", SI_Itin, [Feature64BitPtr, FeatureFP64]>; def : Proc<"verde", SI_Itin, [Feature64BitPtr, FeatureFP64]>; def : Proc<"oland", SI_Itin, [Feature64BitPtr, FeatureFP64]>; +def : Proc<"hainan", SI_Itin, [Feature64BitPtr, FeatureFP64]>; -- cgit v1.2.3 From 9c9bf9a240ace3445f1dd2b8cb0b24c084e99f0b Mon Sep 17 00:00:00 2001 From: Jyotsna Verma Date: Tue, 14 May 2013 15:33:27 +0000 Subject: Hexagon: Remove dead-code after unconditional return from addPreSched2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181797 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonTargetMachine.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index 2d5529b5c9..f08da4def3 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -169,9 +169,6 @@ bool HexagonPassConfig::addPreSched2() { printAndVerify("After hexagon split const32/64 pass"); } return true; - if (getOptLevel() != CodeGenOpt::None) - addPass(&IfConverterID); - return false; } bool HexagonPassConfig::addPreEmitPass() { -- cgit v1.2.3 From 21e6ea54ff815b345fa2116f156653caaa809e0b Mon Sep 17 00:00:00 2001 From: Jyotsna Verma Date: Tue, 14 May 2013 15:50:49 +0000 Subject: Hexagon: Test case to check if branch probabilities are properly reflected in the jump instructions in the form of taken/not-taken hint. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181799 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Hexagon/BranchPredict.ll | 79 +++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 test/CodeGen/Hexagon/BranchPredict.ll diff --git a/test/CodeGen/Hexagon/BranchPredict.ll b/test/CodeGen/Hexagon/BranchPredict.ll new file mode 100644 index 0000000000..716e85da5a --- /dev/null +++ b/test/CodeGen/Hexagon/BranchPredict.ll @@ -0,0 +1,79 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s + +; Check if the branch probabilities are reflected in the instructions: +; The basic block placement pass should place the more probable successor +; block as the fall-through block. The unconditional jump in the predecessor +; should then get the right hint (not_taken or ":nt") + + +@j = external global i32 + +define i32 @foo(i32 %a) nounwind { +; CHECK: if{{ *}}(!p{{[0-3]}}.new) jump:nt +entry: + %tobool = icmp eq i32 %a, 0 + br i1 %tobool, label %if.else, label %if.then, !prof !0 + +if.then: ; preds = %entry + %add = add nsw i32 %a, 10 + %call = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add) nounwind + br label %return + +if.else: ; preds = %entry + %call2 = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 4) nounwind + br label %return + +return: ; preds = %if.else, %if.then + %retval.0 = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %retval.0 +} + +declare i32 @foobar(...) + +define i32 @bar(i32 %a) nounwind { +; CHECK: if{{ *}}(p{{[0-3]}}.new) jump:nt +entry: + %tobool = icmp eq i32 %a, 0 + br i1 %tobool, label %if.else, label %if.then, !prof !1 + +if.then: ; preds = %entry + %add = add nsw i32 %a, 10 + %call = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add) nounwind + br label %return + +if.else: ; preds = %entry + %call2 = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 4) nounwind + br label %return + +return: ; preds = %if.else, %if.then + %retval.0 = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %retval.0 +} + +define i32 @foo_bar(i32 %a, i16 signext %b) nounwind { +; CHECK: if{{ *}}(!cmp.eq(r{{[0-9]*}}.new, #0)) jump:nt +entry: + %0 = load i32* @j, align 4, !tbaa !2 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %if.else, label %if.then, !prof !0 + +if.then: ; preds = %entry + %add = add nsw i32 %a, 10 + %call = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add) nounwind + br label %return + +if.else: ; preds = %entry + %add1 = add nsw i32 %a, 4 + %call2 = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add1) nounwind + br label %return + +return: ; preds = %if.else, %if.then + %retval.0 = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %retval.0 +} + +!0 = metadata !{metadata !"branch_weights", i32 64, i32 4} +!1 = metadata !{metadata !"branch_weights", i32 4, i32 64} +!2 = metadata !{metadata !"int", metadata !3} +!3 = metadata !{metadata !"omnipotent char", metadata !4} +!4 = metadata !{metadata !"Simple C/C++ TBAA"} -- cgit v1.2.3 From ded53bf4dd499f213334400fa870d0c7896d1d0d Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 14 May 2013 16:08:32 +0000 Subject: PPC32: Fix stack collision between FP and CR save areas. The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181800 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCFrameLowering.cpp | 1 + test/CodeGen/PowerPC/crsave.ll | 12 ++++++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp index cd70aeed87..1f0c3c4b5d 100644 --- a/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1168,6 +1168,7 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, FuncInfo->addMustSaveCR(Reg); } else { CRSpilled = true; + FuncInfo->setSpillsCR(); // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll index d698ab031d..f1cbc5afa8 100644 --- a/test/CodeGen/PowerPC/crsave.ll +++ b/test/CodeGen/PowerPC/crsave.ll @@ -13,9 +13,11 @@ entry: ret i32 %1 } +; PPC32: stw 31, -4(1) +; PPC32: stwu 1, -32(1) ; PPC32: mfcr 12 -; PPC32-NEXT: stw 12, {{[0-9]+}}(31) -; PPC32: lwz 12, {{[0-9]+}}(31) +; PPC32-NEXT: stw 12, 24(31) +; PPC32: lwz 12, 24(31) ; PPC32-NEXT: mtcrf 32, 12 ; PPC64: mfcr 12 @@ -35,9 +37,11 @@ entry: ret i32 %1 } +; PPC32: stw 31, -4(1) +; PPC32: stwu 1, -32(1) ; PPC32: mfcr 12 -; PPC32-NEXT: stw 12, {{[0-9]+}}(31) -; PPC32: lwz 12, {{[0-9]+}}(31) +; PPC32-NEXT: stw 12, 24(31) +; PPC32: lwz 12, 24(31) ; PPC32-NEXT: mtcrf 32, 12 ; PPC32-NEXT: mtcrf 16, 12 ; PPC32-NEXT: mtcrf 8, 12 -- cgit v1.2.3 From ed788b62830c26bd1f5d23d73a6337c88b66ab61 Mon Sep 17 00:00:00 2001 From: Derek Schuff Date: Tue, 14 May 2013 16:26:38 +0000 Subject: Fix ARM FastISel tests, as a first step to enabling ARM FastISel ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/fast-isel-GEP-coalesce.ll | 4 +- test/CodeGen/ARM/fast-isel-br-const.ll | 12 +- .../CodeGen/ARM/fast-isel-call-multi-reg-return.ll | 4 +- test/CodeGen/ARM/fast-isel-call.ll | 159 ++++++++------------- test/CodeGen/ARM/fast-isel-crash.ll | 2 +- test/CodeGen/ARM/fast-isel-crash2.ll | 2 +- test/CodeGen/ARM/fast-isel-deadcode.ll | 2 +- test/CodeGen/ARM/fast-isel-intrinsic.ll | 72 +++++----- test/CodeGen/ARM/fast-isel-ldr-str-arm.ll | 2 +- test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll | 2 +- test/CodeGen/ARM/fast-isel-mvn.ll | 4 +- test/CodeGen/ARM/fast-isel-pic.ll | 8 +- test/CodeGen/ARM/fast-isel-redefinition.ll | 2 +- test/CodeGen/ARM/fast-isel-select.ll | 2 +- test/CodeGen/ARM/fast-isel-static.ll | 6 +- test/CodeGen/ARM/fast-isel.ll | 12 +- test/CodeGen/Thumb2/large-call.ll | 2 +- test/MC/ARM/data-in-code.ll | 14 +- 18 files changed, 143 insertions(+), 168 deletions(-) diff --git a/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll b/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll index 60bc6a62f5..28a84e3bf9 100644 --- a/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll +++ b/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll @@ -26,8 +26,8 @@ entry: ; THUMB: t2 %addr = alloca i32*, align 4 store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4 -; ARM: movw r1, #1148 -; ARM: add r0, r0, r1 +; ARM: movw [[R:r[0-9]+]], #1148 +; ARM: add r0, r{{[0-9]+}}, [[R]] ; THUMB: addw r0, r0, #1148 %0 = load i32** %addr, align 4 ret i32* %0 diff --git a/test/CodeGen/ARM/fast-isel-br-const.ll b/test/CodeGen/ARM/fast-isel-br-const.ll index 4e6efd2489..aefe200dc7 100644 --- a/test/CodeGen/ARM/fast-isel-br-const.ll +++ b/test/CodeGen/ARM/fast-isel-br-const.ll @@ -7,8 +7,8 @@ entry: ; ARM: t1: %x = add i32 %a, %b br i1 1, label %if.then, label %if.else -; THUMB-NOT: b LBB0_1 -; ARM-NOT: b LBB0_1 +; THUMB-NOT: b {{\.?}}LBB0_1 +; ARM-NOT: b {{\.?}}LBB0_1 if.then: ; preds = %entry call void @foo1() @@ -16,8 +16,8 @@ if.then: ; preds = %entry if.else: ; preds = %entry br i1 0, label %if.then2, label %if.else3 -; THUMB: b LBB0_4 -; ARM: b LBB0_4 +; THUMB: b {{\.?}}LBB0_4 +; ARM: b {{\.?}}LBB0_4 if.then2: ; preds = %if.else call void @foo2() @@ -26,8 +26,8 @@ if.then2: ; preds = %if.else if.else3: ; preds = %if.else %y = sub i32 %a, %b br i1 1, label %if.then5, label %if.end -; THUMB-NOT: b LBB0_5 -; ARM-NOT: b LBB0_5 +; THUMB-NOT: b {{\.?}}LBB0_5 +; ARM-NOT: b {{\.?}}LBB0_5 if.then5: ; preds = %if.else3 call void @foo1() diff --git a/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll b/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll index b6f201728c..46d5f997c6 100644 --- a/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll +++ b/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Fast-isel can't handle non-double multi-reg retvals. ; This test just check to make sure we don't hit the assert in FinishCall. diff --git a/test/CodeGen/ARM/fast-isel-call.ll b/test/CodeGen/ARM/fast-isel-call.ll index b6c9098613..6ee2c349ab 100644 --- a/test/CodeGen/ARM/fast-isel-call.ll +++ b/test/CodeGen/ARM/fast-isel-call.ll @@ -2,8 +2,12 @@ ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG -; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP -; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP + +; Note that some of these tests assume that relocations are either +; movw/movt or constant pool loads. Different platforms will select +; different approaches. define i32 @t0(i1 zeroext %a) nounwind { %1 = zext i1 %a to i32 @@ -88,53 +92,53 @@ declare zeroext i1 @t9(); define i32 @t10(i32 %argc, i8** nocapture %argv) { entry: ; ARM: @t10 -; ARM: movw r0, #0 -; ARM: movw r1, #248 -; ARM: movw r2, #187 -; ARM: movw r3, #28 -; ARM: movw r9, #40 -; ARM: movw r12, #186 -; ARM: uxtb r0, r0 -; ARM: uxtb r1, r1 -; ARM: uxtb r2, r2 -; ARM: uxtb r3, r3 -; ARM: uxtb r9, r9 -; ARM: str r9, [sp] -; ARM: uxtb r9, r12 -; ARM: str r9, [sp, #4] -; ARM: bl _bar +; ARM: movw [[R0:l?r[0-9]*]], #0 +; ARM: movw [[R1:l?r[0-9]*]], #248 +; ARM: movw [[R2:l?r[0-9]*]], #187 +; ARM: movw [[R3:l?r[0-9]*]], #28 +; ARM: movw [[R4:l?r[0-9]*]], #40 +; ARM: movw [[R5:l?r[0-9]*]], #186 +; ARM: uxtb [[R0]], [[R0]] +; ARM: uxtb [[R1]], [[R1]] +; ARM: uxtb [[R2]], [[R2]] +; ARM: uxtb [[R3]], [[R3]] +; ARM: uxtb [[R4]], [[R4]] +; ARM: str [[R4]], [sp] +; ARM: uxtb [[R4]], [[R5]] +; ARM: str [[R4]], [sp, #4] +; ARM: bl {{_?}}bar ; ARM-LONG: @t10 -; ARM-LONG: movw lr, :lower16:L_bar$non_lazy_ptr -; ARM-LONG: movt lr, :upper16:L_bar$non_lazy_ptr -; ARM-LONG: ldr lr, [lr] -; ARM-LONG: blx lr +; ARM-LONG: {{(movw)|(ldr)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}} +; ARM-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}} +; ARM-LONG: ldr [[R]], {{\[}}[[R]]{{\]}} +; ARM-LONG: blx [[R]] ; THUMB: @t10 -; THUMB: movs r0, #0 -; THUMB: movt r0, #0 -; THUMB: movs r1, #248 -; THUMB: movt r1, #0 -; THUMB: movs r2, #187 -; THUMB: movt r2, #0 -; THUMB: movs r3, #28 -; THUMB: movt r3, #0 -; THUMB: movw r9, #40 -; THUMB: movt r9, #0 -; THUMB: movw r12, #186 -; THUMB: movt r12, #0 -; THUMB: uxtb r0, r0 -; THUMB: uxtb r1, r1 -; THUMB: uxtb r2, r2 -; THUMB: uxtb r3, r3 -; THUMB: uxtb.w r9, r9 -; THUMB: str.w r9, [sp] -; THUMB: uxtb.w r9, r12 -; THUMB: str.w r9, [sp, #4] -; THUMB: bl _bar +; THUMB: movs [[R0:l?r[0-9]*]], #0 +; THUMB: movt [[R0]], #0 +; THUMB: movs [[R1:l?r[0-9]*]], #248 +; THUMB: movt [[R1]], #0 +; THUMB: movs [[R2:l?r[0-9]*]], #187 +; THUMB: movt [[R2]], #0 +; THUMB: movs [[R3:l?r[0-9]*]], #28 +; THUMB: movt [[R3]], #0 +; THUMB: movw [[R4:l?r[0-9]*]], #40 +; THUMB: movt [[R4]], #0 +; THUMB: movw [[R5:l?r[0-9]*]], #186 +; THUMB: movt [[R5]], #0 +; THUMB: uxtb [[R0]], [[R0]] +; THUMB: uxtb [[R1]], [[R1]] +; THUMB: uxtb [[R2]], [[R2]] +; THUMB: uxtb [[R3]], [[R3]] +; THUMB: uxtb.w [[R4]], [[R4]] +; THUMB: str.w [[R4]], [sp] +; THUMB: uxtb.w [[R4]], [[R5]] +; THUMB: str.w [[R4]], [sp, #4] +; THUMB: bl {{_?}}bar ; THUMB-LONG: @t10 -; THUMB-LONG: movw lr, :lower16:L_bar$non_lazy_ptr -; THUMB-LONG: movt lr, :upper16:L_bar$non_lazy_ptr -; THUMB-LONG: ldr.w lr, [lr] -; THUMB-LONG: blx lr +; THUMB-LONG: {{(movw)|(ldr.n)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}} +; THUMB-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}} +; THUMB-LONG: ldr{{(.w)?}} [[R]], {{\[}}[[R]]{{\]}} +; THUMB-LONG: blx [[R]] %call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70) ret i32 0 } @@ -147,12 +151,12 @@ define i32 @bar0(i32 %i) nounwind { define void @foo3() uwtable { ; ARM: movw r0, #0 -; ARM: movw r1, :lower16:_bar0 -; ARM: movt r1, :upper16:_bar0 +; ARM: {{(movw r1, :lower16:_?bar0)|(ldr r1, .LCPI)}} +; ARM: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}} ; ARM: blx r1 ; THUMB: movs r0, #0 -; THUMB: movw r1, :lower16:_bar0 -; THUMB: movt r1, :upper16:_bar0 +; THUMB: {{(movw r1, :lower16:_?bar0)|(ldr.n r1, .LCPI)}} +; THUMB: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}} ; THUMB: blx r1 %fptr = alloca i32 (i32)*, align 8 store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8 @@ -164,66 +168,23 @@ define void @foo3() uwtable { define i32 @LibCall(i32 %a, i32 %b) { entry: ; ARM: LibCall -; ARM: bl ___udivsi3 +; ARM: bl {{___udivsi3|__aeabi_uidiv}} ; ARM-LONG: LibCall -; ARM-LONG: movw r2, :lower16:L___udivsi3$non_lazy_ptr -; ARM-LONG: movt r2, :upper16:L___udivsi3$non_lazy_ptr +; ARM-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}} +; ARM-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} ; ARM-LONG: ldr r2, [r2] ; ARM-LONG: blx r2 ; THUMB: LibCall -; THUMB: bl ___udivsi3 +; THUMB: bl {{___udivsi3|__aeabi_uidiv}} ; THUMB-LONG: LibCall -; THUMB-LONG: movw r2, :lower16:L___udivsi3$non_lazy_ptr -; THUMB-LONG: movt r2, :upper16:L___udivsi3$non_lazy_ptr +; THUMB-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr.n r2, .LCPI)}} +; THUMB-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} ; THUMB-LONG: ldr r2, [r2] ; THUMB-LONG: blx r2 %tmp1 = udiv i32 %a, %b ; [#uses=1] ret i32 %tmp1 } -define i32 @VarArg() nounwind { -entry: - %i = alloca i32, align 4 - %j = alloca i32, align 4 - %k = alloca i32, align 4 - %m = alloca i32, align 4 - %n = alloca i32, align 4 - %tmp = alloca i32, align 4 - %0 = load i32* %i, align 4 - %1 = load i32* %j, align 4 - %2 = load i32* %k, align 4 - %3 = load i32* %m, align 4 - %4 = load i32* %n, align 4 -; ARM: VarArg -; ARM: mov r7, sp -; ARM: movw r0, #5 -; ARM: ldr r1, [r7, #-4] -; ARM: ldr r2, [r7, #-8] -; ARM: ldr r3, [r7, #-12] -; ARM: ldr r9, [sp, #16] -; ARM: ldr r12, [sp, #12] -; ARM: str r9, [sp] -; ARM: str r12, [sp, #4] -; ARM: bl _CallVariadic -; THUMB: mov r7, sp -; THUMB: movs r0, #5 -; THUMB: movt r0, #0 -; THUMB: ldr r1, [sp, #28] -; THUMB: ldr r2, [sp, #24] -; THUMB: ldr r3, [sp, #20] -; THUMB: ldr.w r9, [sp, #16] -; THUMB: ldr.w r12, [sp, #12] -; THUMB: str.w r9, [sp] -; THUMB: str.w r12, [sp, #4] -; THUMB: bl _CallVariadic - %call = call i32 (i32, ...)* @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) - store i32 %call, i32* %tmp, align 4 - %5 = load i32* %tmp, align 4 - ret i32 %5 -} - -declare i32 @CallVariadic(i32, ...) - ; Test fastcc define fastcc void @fast_callee(float %i) ssp { diff --git a/test/CodeGen/ARM/fast-isel-crash.ll b/test/CodeGen/ARM/fast-isel-crash.ll index 8fb4b66b7d..7d45feff69 100644 --- a/test/CodeGen/ARM/fast-isel-crash.ll +++ b/test/CodeGen/ARM/fast-isel-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=thumbv7-apple-darwin +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin %union.anon = type { <16 x i32> } diff --git a/test/CodeGen/ARM/fast-isel-crash2.ll b/test/CodeGen/ARM/fast-isel-crash2.ll index f245168a8e..8867f87065 100644 --- a/test/CodeGen/ARM/fast-isel-crash2.ll +++ b/test/CodeGen/ARM/fast-isel-crash2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=thumbv7-apple-darwin +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin ; rdar://9515076 ; (Make sure this doesn't crash.) diff --git a/test/CodeGen/ARM/fast-isel-deadcode.ll b/test/CodeGen/ARM/fast-isel-deadcode.ll index 3a943d854b..5e6666c47d 100644 --- a/test/CodeGen/ARM/fast-isel-deadcode.ll +++ b/test/CodeGen/ARM/fast-isel-deadcode.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Target-specific selector can't properly handle the double because it isn't ; being passed via a register, so the materialized arguments become dead code. diff --git a/test/CodeGen/ARM/fast-isel-intrinsic.ll b/test/CodeGen/ARM/fast-isel-intrinsic.ll index 48105dd389..bc9769a537 100644 --- a/test/CodeGen/ARM/fast-isel-intrinsic.ll +++ b/test/CodeGen/ARM/fast-isel-intrinsic.ll @@ -3,33 +3,37 @@ ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG +; Note that some of these tests assume that relocations are either +; movw/movt or constant pool loads. Different platforms will select +; different approaches. + @message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1 @temp = common global [60 x i8] zeroinitializer, align 1 define void @t1() nounwind ssp { ; ARM: t1 -; ARM: movw r0, :lower16:_message1 -; ARM: movt r0, :upper16:_message1 +; ARM: {{(movw r0, :lower16:_?message1)|(ldr r0, .LCPI)}} +; ARM: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}} ; ARM: add r0, r0, #5 ; ARM: movw r1, #64 ; ARM: movw r2, #10 ; ARM: uxtb r1, r1 -; ARM: bl _memset +; ARM: bl {{_?}}memset ; ARM-LONG: t1 ; ARM-LONG: movw r3, :lower16:L_memset$non_lazy_ptr ; ARM-LONG: movt r3, :upper16:L_memset$non_lazy_ptr ; ARM-LONG: ldr r3, [r3] ; ARM-LONG: blx r3 ; THUMB: t1 -; THUMB: movw r0, :lower16:_message1 -; THUMB: movt r0, :upper16:_message1 +; THUMB: {{(movw r0, :lower16:_?message1)|(ldr.n r0, .LCPI)}} +; THUMB: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}} ; THUMB: adds r0, #5 ; THUMB: movs r1, #64 ; THUMB: movt r1, #0 ; THUMB: movs r2, #10 ; THUMB: movt r2, #0 ; THUMB: uxtb r1, r1 -; THUMB: bl _memset +; THUMB: bl {{_?}}memset ; THUMB-LONG: t1 ; THUMB-LONG: movw r3, :lower16:L_memset$non_lazy_ptr ; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr @@ -43,31 +47,33 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind define void @t2() nounwind ssp { ; ARM: t2 -; ARM: movw r0, :lower16:L_temp$non_lazy_ptr -; ARM: movt r0, :upper16:L_temp$non_lazy_ptr +; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; ARM: ldr r0, [r0] ; ARM: add r1, r0, #4 ; ARM: add r0, r0, #16 ; ARM: movw r2, #17 -; ARM: str r0, [sp] @ 4-byte Spill +; ARM: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill ; ARM: mov r0, r1 -; ARM: ldr r1, [sp] @ 4-byte Reload -; ARM: bl _memcpy +; ARM: ldr r1, [sp[[SLOT]]] @ 4-byte Reload +; ARM: bl {{_?}}memcpy ; ARM-LONG: t2 ; ARM-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr ; ARM-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr ; ARM-LONG: ldr r3, [r3] ; ARM-LONG: blx r3 ; THUMB: t2 -; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr -; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr +; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} +; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; THUMB: ldr r0, [r0] ; THUMB: adds r1, r0, #4 ; THUMB: adds r0, #16 ; THUMB: movs r2, #17 ; THUMB: movt r2, #0 +; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill ; THUMB: mov r0, r1 -; THUMB: bl _memcpy +; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload +; THUMB: bl {{_?}}memcpy ; THUMB-LONG: t2 ; THUMB-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr ; THUMB-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr @@ -81,29 +87,31 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, define void @t3() nounwind ssp { ; ARM: t3 -; ARM: movw r0, :lower16:L_temp$non_lazy_ptr -; ARM: movt r0, :upper16:L_temp$non_lazy_ptr +; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; ARM: ldr r0, [r0] ; ARM: add r1, r0, #4 ; ARM: add r0, r0, #16 ; ARM: movw r2, #10 ; ARM: mov r0, r1 -; ARM: bl _memmove +; ARM: bl {{_?}}memmove ; ARM-LONG: t3 ; ARM-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr ; ARM-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr ; ARM-LONG: ldr r3, [r3] ; ARM-LONG: blx r3 ; THUMB: t3 -; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr -; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr +; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} +; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; THUMB: ldr r0, [r0] ; THUMB: adds r1, r0, #4 ; THUMB: adds r0, #16 ; THUMB: movs r2, #10 ; THUMB: movt r2, #0 +; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill ; THUMB: mov r0, r1 -; THUMB: bl _memmove +; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload +; THUMB: bl {{_?}}memmove ; THUMB-LONG: t3 ; THUMB-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr ; THUMB-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr @@ -115,8 +123,8 @@ define void @t3() nounwind ssp { define void @t4() nounwind ssp { ; ARM: t4 -; ARM: movw r0, :lower16:L_temp$non_lazy_ptr -; ARM: movt r0, :upper16:L_temp$non_lazy_ptr +; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; ARM: ldr r0, [r0] ; ARM: ldr r1, [r0, #16] ; ARM: str r1, [r0, #4] @@ -126,8 +134,8 @@ define void @t4() nounwind ssp { ; ARM: strh r1, [r0, #12] ; ARM: bx lr ; THUMB: t4 -; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr -; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr +; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} +; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; THUMB: ldr r0, [r0] ; THUMB: ldr r1, [r0, #16] ; THUMB: str r1, [r0, #4] @@ -144,8 +152,8 @@ declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, define void @t5() nounwind ssp { ; ARM: t5 -; ARM: movw r0, :lower16:L_temp$non_lazy_ptr -; ARM: movt r0, :upper16:L_temp$non_lazy_ptr +; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; ARM: ldr r0, [r0] ; ARM: ldrh r1, [r0, #16] ; ARM: strh r1, [r0, #4] @@ -159,8 +167,8 @@ define void @t5() nounwind ssp { ; ARM: strh r1, [r0, #12] ; ARM: bx lr ; THUMB: t5 -; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr -; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr +; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} +; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; THUMB: ldr r0, [r0] ; THUMB: ldrh r1, [r0, #16] ; THUMB: strh r1, [r0, #4] @@ -179,8 +187,8 @@ define void @t5() nounwind ssp { define void @t6() nounwind ssp { ; ARM: t6 -; ARM: movw r0, :lower16:L_temp$non_lazy_ptr -; ARM: movt r0, :upper16:L_temp$non_lazy_ptr +; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; ARM: ldr r0, [r0] ; ARM: ldrb r1, [r0, #16] ; ARM: strb r1, [r0, #4] @@ -204,8 +212,8 @@ define void @t6() nounwind ssp { ; ARM: strb r1, [r0, #13] ; ARM: bx lr ; THUMB: t6 -; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr -; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr +; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} +; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; THUMB: ldr r0, [r0] ; THUMB: ldrb r1, [r0, #16] ; THUMB: strb r1, [r0, #4] diff --git a/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll b/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll index dfb8c53735..cf294bcfbe 100644 --- a/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll +++ b/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM define i32 @t1(i32* nocapture %ptr) nounwind readonly { entry: diff --git a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll index 0b5267ddc9..0e71322d4e 100644 --- a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll +++ b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; rdar://10418009 define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp { diff --git a/test/CodeGen/ARM/fast-isel-mvn.ll b/test/CodeGen/ARM/fast-isel-mvn.ll index b180e439dd..328168a84f 100644 --- a/test/CodeGen/ARM/fast-isel-mvn.ll +++ b/test/CodeGen/ARM/fast-isel-mvn.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; rdar://10412592 ; Note: The Thumb code is being generated by the target-independent selector. diff --git a/test/CodeGen/ARM/fast-isel-pic.ll b/test/CodeGen/ARM/fast-isel-pic.ll index 867d53f973..6bb9ea3a8c 100644 --- a/test/CodeGen/ARM/fast-isel-pic.ll +++ b/test/CodeGen/ARM/fast-isel-pic.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7 -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7 +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF @g = global i32 0, align 4 diff --git a/test/CodeGen/ARM/fast-isel-redefinition.ll b/test/CodeGen/ARM/fast-isel-redefinition.ll index 563880dab0..ee150facac 100644 --- a/test/CodeGen/ARM/fast-isel-redefinition.ll +++ b/test/CodeGen/ARM/fast-isel-redefinition.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -verify-machineinstrs -optimize-regalloc -regalloc=basic < %s +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic < %s ; This isn't exactly a useful set of command-line options, but check that it ; doesn't crash. (It was crashing because a register was getting redefined.) diff --git a/test/CodeGen/ARM/fast-isel-select.ll b/test/CodeGen/ARM/fast-isel-select.ll index b83a733669..a937036284 100644 --- a/test/CodeGen/ARM/fast-isel-select.ll +++ b/test/CodeGen/ARM/fast-isel-select.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i1 %c) nounwind readnone { diff --git a/test/CodeGen/ARM/fast-isel-static.ll b/test/CodeGen/ARM/fast-isel-static.ll index e8759a7fc4..afdfa84f39 100644 --- a/test/CodeGen/ARM/fast-isel-static.ll +++ b/test/CodeGen/ARM/fast-isel-static.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -relocation-model=static | FileCheck -check-prefix=NORM %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=NORM %s define void @myadd(float* %sum, float* %addend) nounwind { entry: @@ -24,7 +24,7 @@ entry: store float 0.000000e+00, float* %ztot, align 4 store float 1.000000e+00, float* %z, align 4 ; CHECK-LONG: blx r -; CHECK-NORM: bl _myadd +; CHECK-NORM: bl {{_?}}myadd call void @myadd(float* %ztot, float* %z) ret i32 0 } diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index 41fda41326..39ffcac292 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -144,15 +144,19 @@ define void @test4() { store i32 %b, i32* @test4g ret void -; THUMB: movw r0, :lower16:L_test4g$non_lazy_ptr -; THUMB: movt r0, :upper16:L_test4g$non_lazy_ptr + +; Note that relocations are either movw/movt or constant pool +; loads. Different platforms will select different approaches. + +; THUMB: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} +; THUMB: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}} ; THUMB: ldr r0, [r0] ; THUMB: ldr r1, [r0] ; THUMB: adds r1, #1 ; THUMB: str r1, [r0] -; ARM: movw r0, :lower16:L_test4g$non_lazy_ptr -; ARM: movt r0, :upper16:L_test4g$non_lazy_ptr +; ARM: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}} ; ARM: ldr r0, [r0] ; ARM: ldr r1, [r0] ; ARM: add r1, r1, #1 diff --git a/test/CodeGen/Thumb2/large-call.ll b/test/CodeGen/Thumb2/large-call.ll index 61c477aa91..1b4d4625dd 100644 --- a/test/CodeGen/Thumb2/large-call.ll +++ b/test/CodeGen/Thumb2/large-call.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mcpu=cortex-a8 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "thumbv7-apple-ios0.0.0" diff --git a/test/MC/ARM/data-in-code.ll b/test/MC/ARM/data-in-code.ll index e3325b6bf6..9fccf2e9f8 100644 --- a/test/MC/ARM/data-in-code.ll +++ b/test/MC/ARM/data-in-code.ll @@ -1,7 +1,9 @@ -;; RUN: llc -O0 -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \ +;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \ +;; RUN: -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \ ;; RUN: llvm-readobj -t | FileCheck -check-prefix=ARM %s -;; RUN: llc -O0 -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \ +;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \ +;; RUN: -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \ ;; RUN: llvm-readobj -t | FileCheck -check-prefix=TMB %s ;; Ensure that if a jump table is generated that it has Mapping Symbols @@ -119,7 +121,7 @@ exit: ;; ARM: Symbol { ;; ARM: Name: $a -;; ARM-NEXT: Value: 0xAC +;; ARM-NEXT: Value: 0x{{[0-9A-F]+}} ;; ARM-NEXT: Size: 0 ;; ARM-NEXT: Binding: Local ;; ARM-NEXT: Type: None @@ -135,7 +137,7 @@ exit: ;; ARM: Symbol { ;; ARM: Name: $d -;; ARM-NEXT: Value: 0x30 +;; ARM-NEXT: Value: 0x{{[0-9A-F]+}} ;; ARM-NEXT: Size: 0 ;; ARM-NEXT: Binding: Local ;; ARM-NEXT: Type: None @@ -146,7 +148,7 @@ exit: ;; TMB: Symbol { ;; TMB: Name: $d.2 -;; TMB-NEXT: Value: 0x16 +;; TMB-NEXT: Value: 0x{{[0-9A-F]+}} ;; TMB-NEXT: Size: 0 ;; TMB-NEXT: Binding: Local ;; TMB-NEXT: Type: None @@ -164,7 +166,7 @@ exit: ;; TMB: Symbol { ;; TMB: Name: $t -;; TMB-NEXT: Value: 0x36 +;; TMB-NEXT: Value: 0x{{[0-9A-F]+}} ;; TMB-NEXT: Size: 0 ;; TMB-NEXT: Binding: Local ;; TMB-NEXT: Type: None -- cgit v1.2.3 From e4642bc096984c12c1ef129137e17fad61201118 Mon Sep 17 00:00:00 2001 From: Kai Nacke Date: Tue, 14 May 2013 16:30:51 +0000 Subject: Add bitcast to store of personality function. The personality function is user defined and may have an arbitrary result type. The code assumes always i8*. This results in an assertion failure if a different type is used. A bitcast to i8* is added to prevent this failure. Reviewed by: Renato Golin, Bob Wilson git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181802 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SjLjEHPrepare.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/SjLjEHPrepare.cpp b/lib/CodeGen/SjLjEHPrepare.cpp index 3903743878..23984e9986 100644 --- a/lib/CodeGen/SjLjEHPrepare.cpp +++ b/lib/CodeGen/SjLjEHPrepare.cpp @@ -222,7 +222,9 @@ setupFunctionContext(Function &F, ArrayRef LPads) { PersonalityFn = LPads[0]->getPersonalityFn(); Value *PersonalityFieldPtr = Builder.CreateConstGEP2_32(FuncCtx, 0, 3, "pers_fn_gep"); - Builder.CreateStore(PersonalityFn, PersonalityFieldPtr, /*isVolatile=*/true); + Builder.CreateStore(Builder.CreateBitCast(PersonalityFn, + Builder.getInt8PtrTy()), + PersonalityFieldPtr, /*isVolatile=*/true); // LSDA address Value *LSDA = Builder.CreateCall(LSDAAddrFn, "lsda_addr"); -- cgit v1.2.3 From 91eadc6d697647f426d05cab66aae2a19112343e Mon Sep 17 00:00:00 2001 From: Jyotsna Verma Date: Tue, 14 May 2013 16:36:34 +0000 Subject: Hexagon: ArePredicatesComplement should not restrict itself to TFRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181803 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 36 ++++++++++++++++++++++++---- test/CodeGen/Hexagon/packetize_cond_inst.ll | 32 +++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 5 deletions(-) create mode 100644 test/CodeGen/Hexagon/packetize_cond_inst.ll diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index c508d124b3..59b4fabe01 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -837,16 +837,38 @@ bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI, } +/// Gets the predicate register of a predicated instruction. +unsigned getPredicatedRegister(MachineInstr *MI, const HexagonInstrInfo *QII) { + /// We use the following rule: The first predicate register that is a use is + /// the predicate register of a predicated instruction. + + assert(QII->isPredicated(MI) && "Must be predicated instruction"); + + for (MachineInstr::mop_iterator OI = MI->operands_begin(), + OE = MI->operands_end(); OI != OE; ++OI) { + MachineOperand &Op = *OI; + if (Op.isReg() && Op.getReg() && Op.isUse() && + Hexagon::PredRegsRegClass.contains(Op.getReg())) + return Op.getReg(); + } + + llvm_unreachable("Unknown instruction operand layout"); + + return 0; +} + // Given two predicated instructions, this function detects whether // the predicates are complements bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1, MachineInstr* MI2, std::map MIToSUnit) { const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; - // Currently can only reason about conditional transfers - if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) { + + // If we don't know the predicate sense of the instructions bail out early, we + // need it later. + if (getPredicateSense(MI1, QII) == PK_Unknown || + getPredicateSense(MI2, QII) == PK_Unknown) return false; - } // Scheduling unit for candidate SUnit* SU = MIToSUnit[MI1]; @@ -885,9 +907,9 @@ bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1, // there already exist anti dep on the same pred in // the packet. if (PacketSU->Succs[i].getSUnit() == SU && + PacketSU->Succs[i].getKind() == SDep::Data && Hexagon::PredRegsRegClass.contains( PacketSU->Succs[i].getReg()) && - PacketSU->Succs[i].getKind() == SDep::Data && // Here I know that *VIN is predicate setting instruction // with true data dep to candidate on the register // we care about - c) in the above example. @@ -908,7 +930,11 @@ bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1, // that the predicate sense is different // We also need to differentiate .old vs. .new: // !p0 is not complimentary to p0.new - return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) && + unsigned PReg1 = getPredicatedRegister(MI1, QII); + unsigned PReg2 = getPredicatedRegister(MI2, QII); + return ((PReg1 == PReg2) && + Hexagon::PredRegsRegClass.contains(PReg1) && + Hexagon::PredRegsRegClass.contains(PReg2) && (getPredicateSense(MI1, QII) != getPredicateSense(MI2, QII)) && (QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2))); } diff --git a/test/CodeGen/Hexagon/packetize_cond_inst.ll b/test/CodeGen/Hexagon/packetize_cond_inst.ll new file mode 100644 index 0000000000..a48a9f62ec --- /dev/null +++ b/test/CodeGen/Hexagon/packetize_cond_inst.ll @@ -0,0 +1,32 @@ +; RUN: llc -mcpu=hexagonv4 -tail-dup-size=1 < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon-unknown--elf" + +; Make sure we put the two conditionally executed adds in a packet. +; ifcnv_add: +; { +; p0 = cmp.gt(r2, r1) +; if (!p0.new) r0 = add(r2, r1) +; if (p0.new) r0 = add(r0, #10) +; } +; CHECK: cmp +; CHECK-NEXT: add +; CHECH-NEXT: add +define i32 @ifcnv_add(i32, i32, i32) nounwind readnone { + %4 = icmp sgt i32 %2, %1 + br i1 %4, label %5, label %7 + +;