From ba7183bc5284a0e4254ad12b78e2ea61e291dd88 Mon Sep 17 00:00:00 2001 From: Roman Divacky Date: Thu, 12 Sep 2013 17:50:54 +0000 Subject: Implement asm support for a few PowerPC bookIII that are needed for assembling FreeBSD kernel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190618 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 2 + lib/Target/PowerPC/PPCInstrFormats.td | 33 ++++++++ lib/Target/PowerPC/PPCInstrInfo.td | 69 +++++++++++++++++ lib/Target/PowerPC/PPCSchedule.td | 8 ++ test/MC/PowerPC/ppc64-encoding-bookIII.s | 107 ++++++++++++++++++++++++++ 5 files changed, 219 insertions(+) create mode 100644 test/MC/PowerPC/ppc64-encoding-bookIII.s diff --git a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 6896e7a10f..c2ea6163e9 100644 --- a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -1360,6 +1360,8 @@ unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp, switch (Kind) { case MCK_0: ImmVal = 0; break; case MCK_1: ImmVal = 1; break; + case MCK_2: ImmVal = 2; break; + case MCK_3: ImmVal = 3; break; default: return Match_InvalidOperand; } diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 42adc02595..29233d4914 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -398,6 +398,13 @@ class XForm_1a opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, let RST = 0; } +class XForm_rs opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list pattern> + : XForm_base_r3xo { + let A = 0; + let B = 0; +} + class XForm_6 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : XForm_base_r3xo_swapped { @@ -438,6 +445,17 @@ class XForm_16 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, let Inst{31} = 0; } +class XForm_mtmsr opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : I { + bits<5> RS; + bits<1> L; + + let Inst{6-10} = RS; + let Inst{15} = L; + let Inst{21-30} = xo; +} + class XForm_16_ext opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : XForm_16 { @@ -534,6 +552,21 @@ class XForm_43 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, let Inst{31} = RC; } +class XForm_0 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list pattern> + : XForm_base_r3xo { + let RST = 0; + let A = 0; + let B = 0; +} + +class XForm_16b opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list pattern> + : XForm_base_r3xo { + let RST = 0; + let A = 0; +} + // DCB_Form - Form X instruction, used for dcb* instructions. class DCB_Form xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index df618445b3..a9c916f015 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -2319,6 +2319,35 @@ def EIEIO : XForm_24_eieio<31, 854, (outs), (ins), def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L), "wait $L", LdStLoad, []>; +def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L), + "mtmsr $RS, $L", SprMTMSR>; + +def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), + "mfmsr $RT", SprMFMSR, []>; + +def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L), + "mtmsrd $RS, $L", SprMTMSRD>; + +def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), + "slbie $RB", SprSLBIE, []>; + +def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), + "slbmte $RS, $RB", SprSLBMTE, []>; + +def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), + "slbmfee $RT, $RB", SprSLBMFEE, []>; + +def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", SprSLBIA, []>; + +def TLBSYNC : XForm_0<31, 566, (outs), (ins), + "tlbsync", SprTLBSYNC, []>; + +def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), + "tlbiel $RB", SprTLBIEL, []>; + +def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), + "tlbie $RB,$RS", SprTLBIE, []>; + //===----------------------------------------------------------------------===// // PowerPC Assembler Instruction Aliases // @@ -2387,6 +2416,46 @@ def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; +def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; +def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; + +def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>; +def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>; +def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>; +def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>; + +def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>; +def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>; +def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>; +def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>; + +def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>; +def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>; +def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>; +def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>; + +def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>; +def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>; +def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>; +def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>; + +def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>; + +def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>; +def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>; + +def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; + +def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>; +def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>; + +def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>; +def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>; +def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>; +def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>; + +def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; + def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", diff --git a/lib/Target/PowerPC/PPCSchedule.td b/lib/Target/PowerPC/PPCSchedule.td index 660c0c3b63..92ba69c2c6 100644 --- a/lib/Target/PowerPC/PPCSchedule.td +++ b/lib/Target/PowerPC/PPCSchedule.td @@ -108,6 +108,14 @@ def VecPerm : InstrItinClass; def VecFPRound : InstrItinClass; def VecVSL : InstrItinClass; def VecVSR : InstrItinClass; +def SprMTMSRD : InstrItinClass; +def SprSLIE : InstrItinClass; +def SprSLBIE : InstrItinClass; +def SprSLBMTE : InstrItinClass; +def SprSLBMFEE : InstrItinClass; +def SprSLBIA : InstrItinClass; +def SprTLBIEL : InstrItinClass; +def SprTLBIE : InstrItinClass; //===----------------------------------------------------------------------===// // Processor instruction itineraries. diff --git a/test/MC/PowerPC/ppc64-encoding-bookIII.s b/test/MC/PowerPC/ppc64-encoding-bookIII.s new file mode 100644 index 0000000000..318c30b04d --- /dev/null +++ b/test/MC/PowerPC/ppc64-encoding-bookIII.s @@ -0,0 +1,107 @@ +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s + +# CHECK: mtmsr 4, 0 # encoding: [0x7c,0x80,0x01,0x24] + mtmsr %r4 + +# CHECK: mtmsr 4, 1 # encoding: [0x7c,0x81,0x01,0x24] + mtmsr %r4, 1 + +# CHECK: mfmsr 4 # encoding: [0x7c,0x80,0x00,0xa6] + mfmsr %r4 + +# CHECK: mtmsrd 4, 0 # encoding: [0x7c,0x80,0x01,0x64] + mtmsrd %r4 + +# CHECK: mtmsrd 4, 1 # encoding: [0x7c,0x81,0x01,0x64] + mtmsrd %r4, 1 + +# CHECK: mfspr 4, 272 # encoding: [0x7c,0x90,0x42,0xa6] + mfsprg %r4, 0 + +# CHECK: mfspr 4, 273 # encoding: [0x7c,0x91,0x42,0xa6] + mfsprg %r4, 1 + +# CHECK: mfspr 4, 274 # encoding: [0x7c,0x92,0x42,0xa6] + mfsprg %r4, 2 + +# CHECK: mfspr 4, 275 # encoding: [0x7c,0x93,0x42,0xa6] + mfsprg %r4, 3 + +# CHECK: mtspr 272, 4 # encoding: [0x7c,0x90,0x43,0xa6] + mtsprg 0, %r4 + +# CHECK: mtspr 273, 4 # encoding: [0x7c,0x91,0x43,0xa6] + mtsprg 1, %r4 + +# CHECK: mtspr 274, 4 # encoding: [0x7c,0x92,0x43,0xa6] + mtsprg 2, %r4 + +# CHECK: mtspr 275, 4 # encoding: [0x7c,0x93,0x43,0xa6] + mtsprg 3, %r4 + +# CHECK: mtspr 272, 4 # encoding: [0x7c,0x90,0x43,0xa6] + mtsprg0 %r4 + +# CHECK: mtspr 273, 4 # encoding: [0x7c,0x91,0x43,0xa6] + mtsprg1 %r4 + +# CHECK: mtspr 274, 4 # encoding: [0x7c,0x92,0x43,0xa6] + mtsprg2 %r4 + +# CHECK: mtspr 275, 4 # encoding: [0x7c,0x93,0x43,0xa6] + mtsprg3 %r4 + +# CHECK: mtspr 280, 4 # encoding: [0x7c,0x98,0x43,0xa6] + mtasr %r4 + +# CHECK: mfspr 4, 22 # encoding: [0x7c,0x96,0x02,0xa6] + mfdec %r4 + +# CHECK: mtspr 22, 4 # encoding: [0x7c,0x96,0x03,0xa6] + mtdec %r4 + +# CHECK: mfspr 4, 287 # encoding: [0x7c,0x9f,0x42,0xa6] + mfpvr %r4 + +# CHECK: mfspr 4, 25 # encoding: [0x7c,0x99,0x02,0xa6] + mfsdr1 %r4 + +# CHECK: mtspr 25, 4 # encoding: [0x7c,0x99,0x03,0xa6] + mtsdr1 %r4 + +# CHECK: mfspr 4, 26 # encoding: [0x7c,0x9a,0x02,0xa6] + mfsrr0 %r4 + +# CHECK: mtspr 26, 4 # encoding: [0x7c,0x9a,0x03,0xa6] + mtsrr0 %r4 + +# CHECK: mfspr 4, 27 # encoding: [0x7c,0x9b,0x02,0xa6] + mfsrr1 %r4 + +# CHECK: mtspr 27, 4 # encoding: [0x7c,0x9b,0x03,0xa6] + mtsrr1 %r4 + +# CHECK: slbie 4 # encoding: [0x7c,0x00,0x23,0x64] + slbie %r4 + +# CHECK: slbmte 4, 5 # encoding: [0x7c,0x80,0x2b,0x24] + slbmte %r4, %r5 + +# CHECK: slbmfee 4, 5 # encoding: [0x7c,0x80,0x2f,0x26] + slbmfee %r4, %r5 + +# CHECK: slbia # encoding: [0x7c,0x00,0x03,0xe4] + slbia + +# CHECK: tlbsync # encoding: [0x7c,0x00,0x04,0x6c] + tlbsync + +# CHECK: tlbiel 4 # encoding: [0x7c,0x00,0x22,0x24] + tlbiel %r4 + +# CHECK: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64] + tlbie %r4, 0 + +# CHECK: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64] + tlbie %r4 + -- cgit v1.2.3