From ded53bf4dd499f213334400fa870d0c7896d1d0d Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 14 May 2013 16:08:32 +0000 Subject: PPC32: Fix stack collision between FP and CR save areas. The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181800 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCFrameLowering.cpp | 1 + test/CodeGen/PowerPC/crsave.ll | 12 ++++++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp index cd70aeed87..1f0c3c4b5d 100644 --- a/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1168,6 +1168,7 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, FuncInfo->addMustSaveCR(Reg); } else { CRSpilled = true; + FuncInfo->setSpillsCR(); // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll index d698ab031d..f1cbc5afa8 100644 --- a/test/CodeGen/PowerPC/crsave.ll +++ b/test/CodeGen/PowerPC/crsave.ll @@ -13,9 +13,11 @@ entry: ret i32 %1 } +; PPC32: stw 31, -4(1) +; PPC32: stwu 1, -32(1) ; PPC32: mfcr 12 -; PPC32-NEXT: stw 12, {{[0-9]+}}(31) -; PPC32: lwz 12, {{[0-9]+}}(31) +; PPC32-NEXT: stw 12, 24(31) +; PPC32: lwz 12, 24(31) ; PPC32-NEXT: mtcrf 32, 12 ; PPC64: mfcr 12 @@ -35,9 +37,11 @@ entry: ret i32 %1 } +; PPC32: stw 31, -4(1) +; PPC32: stwu 1, -32(1) ; PPC32: mfcr 12 -; PPC32-NEXT: stw 12, {{[0-9]+}}(31) -; PPC32: lwz 12, {{[0-9]+}}(31) +; PPC32-NEXT: stw 12, 24(31) +; PPC32: lwz 12, 24(31) ; PPC32-NEXT: mtcrf 32, 12 ; PPC32-NEXT: mtcrf 16, 12 ; PPC32-NEXT: mtcrf 8, 12 -- cgit v1.2.3