From eb97c0499bda650d84bba2079d4007a4d3ec0246 Mon Sep 17 00:00:00 2001 From: Venkatraman Govindaraju Date: Sat, 1 Feb 2014 18:54:16 +0000 Subject: [Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200617 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Sparc/MCTargetDesc/SparcMCTargetDesc.cpp | 25 +++++++++++++++++++--- lib/Target/Sparc/SparcRegisterInfo.cpp | 2 +- test/CodeGen/SPARC/exception.ll | 8 +++++++ 3 files changed, 31 insertions(+), 4 deletions(-) diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index cc2ba02c52..e66b74d08a 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -33,6 +33,25 @@ using namespace llvm; + +static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, + StringRef TT) { + MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); + unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0); + MAI->addInitialFrameState(Inst); + return MAI; +} + +static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, + StringRef TT) { + MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); + unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 2047); + MAI->addInitialFrameState(Inst); + return MAI; +} + static MCInstrInfo *createSparcMCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitSparcMCInstrInfo(X); @@ -41,7 +60,7 @@ static MCInstrInfo *createSparcMCInstrInfo() { static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) { MCRegisterInfo *X = new MCRegisterInfo(); - InitSparcMCRegisterInfo(X, SP::I7); + InitSparcMCRegisterInfo(X, SP::O7); return X; } @@ -136,8 +155,8 @@ static MCInstPrinter *createSparcMCInstPrinter(const Target &T, extern "C" void LLVMInitializeSparcTargetMC() { // Register the MC asm info. - RegisterMCAsmInfo X(TheSparcTarget); - RegisterMCAsmInfo Y(TheSparcV9Target); + RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo); + RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget, diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index c98613aa12..f222382a6b 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -35,7 +35,7 @@ ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false), cl::desc("Reserve application registers (%g2-%g4)")); SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st) - : SparcGenRegisterInfo(SP::I7), Subtarget(st) { + : SparcGenRegisterInfo(SP::O7), Subtarget(st) { } const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) diff --git a/test/CodeGen/SPARC/exception.ll b/test/CodeGen/SPARC/exception.ll index fd9e871dd9..b45d998a9c 100644 --- a/test/CodeGen/SPARC/exception.ll +++ b/test/CodeGen/SPARC/exception.ll @@ -56,7 +56,11 @@ ; V8PIC_NOCFI-NEXT: .word _ZTIi ; V8PIC_NOCFI: .section .eh_frame ; V8PIC_NOCFI-NOT: .section +; V8PIC_NOCFI: .byte 15 ! CIE Return Address Column ; V8PIC_NOCFI: .word %r_disp32(DW.ref.__gxx_personality_v0) +; V8PIC_NOCFI: .byte 12 ! DW_CFA_def_cfa +; V8PIC_NOCFI: .byte 14 ! Reg 14 +; V8PIC_NOCFI-NEXT: .byte 0 ! Offset 0 ; V8PIC_NOCFI: .word %r_disp32(.Ltmp{{.+}}) ! FDE initial location @@ -94,7 +98,11 @@ ; V9PIC_NOCFI-NEXT: .xword _ZTIi ; V9PIC_NOCFI: .section .eh_frame ; V9PIC_NOCFI-NOT: .section +; V9PIC_NOCFI: .byte 15 ! CIE Return Address Column ; V9PIC_NOCFI: .word %r_disp32(DW.ref.__gxx_personality_v0) +; V9PIC_NOCFI: .byte 12 ! DW_CFA_def_cfa +; V9PIC_NOCFI-NEXT: .byte 14 ! Reg 14 +; V9PIC_NOCFI: .ascii "\377\017" ! Offset 2047 ; V9PIC_NOCFI: .word %r_disp32(.Ltmp{{.+}}) ! FDE initial location define i32 @main(i32 %argc, i8** nocapture readnone %argv) unnamed_addr #0 { -- cgit v1.2.3