From 727273b11c315b0ba5ef9cbf4df442ce627045ef Mon Sep 17 00:00:00 2001 From: Alp Toker Date: Thu, 15 May 2014 01:52:21 +0000 Subject: Fix typos git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208839 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/BigEndianNEON.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs/BigEndianNEON.rst') diff --git a/docs/BigEndianNEON.rst b/docs/BigEndianNEON.rst index 4dc1628a0e..242eb0e73d 100644 --- a/docs/BigEndianNEON.rst +++ b/docs/BigEndianNEON.rst @@ -58,7 +58,7 @@ A "little endian" layout has the least significant byte first (lowest in memory Big endian vector load using ``LDR``. -A vector is a consecutive sequence of items that are operated on simultaneously. To load a 64-bit vector, 64 bits need to be read from memory. In little endian mode, we can do this by just performing a 64-bit load - ``LDR q0, [foo]``. However if we try this in big endian mode, because of the byte swapping the lane indices end up being swapped! The zero'th item as layed out in memory becomes the n'th lane in the vector. +A vector is a consecutive sequence of items that are operated on simultaneously. To load a 64-bit vector, 64 bits need to be read from memory. In little endian mode, we can do this by just performing a 64-bit load - ``LDR q0, [foo]``. However if we try this in big endian mode, because of the byte swapping the lane indices end up being swapped! The zero'th item as laid out in memory becomes the n'th lane in the vector. .. figure:: ARM-BE-ld1.png :align: right -- cgit v1.2.3