From 6805b56e7786f754756526e82e5a29bc77d97e9e Mon Sep 17 00:00:00 2001 From: Anshuman Dasgupta Date: Tue, 6 Dec 2011 23:12:42 +0000 Subject: Add documentation for machine-independent DFA packetizer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145988 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/CodeGenerator.html | 75 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) (limited to 'docs/CodeGenerator.html') diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index 6d7b2ae59a..4f762dc956 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -97,6 +97,14 @@
  • Built in register allocators
  • Code Emission
    • +
  • VLIW Packetizer + +
  • Implementing a Native Assembler
    • @@ -2001,6 +2009,73 @@ to implement an assembler for your target.

    + +

    + VLIW Packetizer +

    + +
    + +

    In a Very Long Instruction Word (VLIW) architecture, the compiler is + responsible for mapping instructions to functional-units available on + the architecture. To that end, the compiler creates groups of instructions + called packets or bundles. The VLIW packetizer in LLVM is + a target-independent mechanism to enable the packetization of machine + instructions.

    + + + +

    + Mapping from instructions to functional units +

    + +
    + +

    Instructions in a VLIW target can typically be mapped to multiple functional +units. During the process of packetizing, the compiler must be able to reason +about whether an instruction can be added to a packet. This decision can be +complex since the compiler has to examine all possible mappings of instructions +to functional units. Therefore to alleviate compilation-time complexity, the +VLIW packetizer parses the instruction classes of a target and generates tables +at compiler build time. These tables can then be queried by the provided +machine-independent API to determine if an instruction can be accommodated in a +packet.

    +
    + + +

    + + How the packetization tables are generated and used + +

    + +
    + +

    The packetizer reads instruction classes from a target's itineraries and +creates a deterministic finite automaton (DFA) to represent the state of a +packet. A DFA consists of three major elements: inputs, states, and +transitions. The set of inputs for the generated DFA represents the instruction +being added to a packet. The states represent the possible consumption +of functional units by instructions in a packet. In the DFA, transitions from +one state to another occur on the addition of an instruction to an existing +packet. If there is a legal mapping of functional units to instructions, then +the DFA contains a corresponding transition. The absence of a transition +indicates that a legal mapping does not exist and that the instruction cannot +be added to the packet.

    + +

    To generate tables for a VLIW target, add TargetGenDFAPacketizer.inc +as a target to the Makefile in the target directory. The exported API provides +three functions: DFAPacketizer::clearResources(), +DFAPacketizer::reserveResources(MachineInstr *MI), and +DFAPacketizer::canReserveResources(MachineInstr *MI). These functions +allow a target packetizer to add an instruction to an existing packet and to +check whether an instruction can be added to a packet. See +llvm/CodeGen/DFAPacketizer.h for more information.

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    + -- cgit v1.2.3