From fd80072059bcbbcaa559cfb5bab999ca5a73e5e9 Mon Sep 17 00:00:00 2001
From: Dan Gohman Portions of the DAG instruction selector are generated from the target
description (*.td) files. Our goal is for the entire instruction
-selector to be generated from these .td files.
The X86 code generator lives in the lib/Target/X86 directory. This -code generator currently targets a generic P6-like processor. As such, it -produces a few P6-and-above instructions (like conditional moves), but it does -not make use of newer features like MMX or SSE. In the future, the X86 backend -will have sub-target support added for specific processor families and -implementations.
+code generator is capable of targeting a variety of x86-32 and x86-64 +processors, and includes support for ISA extensions such as MMX and SSE. +