From f067d584a81ae771d301304ea885e55e2de8ee9a Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 7 Feb 2011 16:40:21 +0000 Subject: implement .ll and .bc support for nsw/nuw on shl and exact on lshr/ashr. Factor some code better. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125006 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/LangRef.html | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) (limited to 'docs/LangRef.html') diff --git a/docs/LangRef.html b/docs/LangRef.html index f7997495e0..dbe385387a 100644 --- a/docs/LangRef.html +++ b/docs/LangRef.html @@ -3684,7 +3684,10 @@ Instruction
Syntax:
-  <result> = shl <ty> <op1>, <op2>   ; yields {ty}:result
+  <result> = shl <ty> <op1>, <op2>           ; yields {ty}:result
+  <result> = shl nuw <ty> <op1>, <op2>       ; yields {ty}:result
+  <result> = shl nsw <ty> <op1>, <op2>       ; yields {ty}:result
+  <result> = shl nuw nsw <ty> <op1>, <op2>   ; yields {ty}:result
Overview:
@@ -3704,6 +3707,14 @@ Instruction vectors, each vector element of op1 is shifted by the corresponding shift amount in op2.

+

If the nuw keyword is present, then the shift produces a + trap value if it shifts out any non-zero bits. If + the nsw keywrod is present, then the shift produces a + trap value if it shifts out any bits that disagree + with the resultant sign bit. As such, NUW/NSW have the same semantics as + they would if the shift were expressed as a mul instruction with the same + nsw/nuw bits in (mul %op1, (shl 1, %op2)).

+
Example:
   <result> = shl i32 4, %var   ; yields {i32}: 4 << %var
@@ -3723,7 +3734,8 @@ Instruction 
 
 
Syntax:

 
-  <result> = lshr <ty> <op1>, <op2>   ; yields {ty}:result
+  <result> = lshr <ty> <op1>, <op2>         ; yields {ty}:result
+  <result> = lshr exact <ty> <op1>, <op2>   ; yields {ty}:result
 

 
 
Overview:

@@ -3743,6 +3755,11 @@ Instruction 
    vectors, each vector element of op1 is shifted by the corresponding
    shift amount in op2.

 
+
If the exact keyword is present, the result value of the
+   lshr is a trap value if any of the bits
+   shifted out are non-zero.

+
+
 
Example:

 
   <result> = lshr i32 4, 1   ; yields {i32}:result = 2
@@ -3762,7 +3779,8 @@ Instruction 
 
 
Syntax:

 
-  <result> = ashr <ty> <op1>, <op2>   ; yields {ty}:result
+  <result> = ashr <ty> <op1>, <op2>         ; yields {ty}:result
+  <result> = ashr exact <ty> <op1>, <op2>   ; yields {ty}:result
 

 
 
Overview:

@@ -3783,6 +3801,10 @@ Instruction 
    the arguments are vectors, each vector element of op1 is shifted by
    the corresponding shift amount in op2.

 
+
If the exact keyword is present, the result value of the
+   ashr is a trap value if any of the bits
+   shifted out are non-zero.

+
 
Example:

 
   <result> = ashr i32 4, 1   ; yields {i32}:result = 2
-- 
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