From c1922c72adedadb414a3d19c3f150bfe1bc755a5 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 19 Apr 2012 23:59:23 +0000 Subject: TableGen support for auto-generating assembly two-operand aliases. Assembly matchers for instructions with a two-operand form. ARM is full of these, for example: add {Rd}, Rn, Rm // Rd is optional and is the same as Rn if omitted. The property TwoOperandAliasConstraint on the instruction definition controls when, and if, an alias will be formed. No explicit InstAlias definitions are required. rdar://11255754 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155172 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/Target.td | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/llvm/Target/Target.td') diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index fa1ec55945..6a321ea2cf 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -402,6 +402,8 @@ class Instruction { string AsmMatchConverter = ""; + string TwoOperandAliasConstraint = ""; + ///@} } -- cgit v1.2.3