From 5a4cbea3120f5e921849bd89c0b43096ef65787f Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 1 Sep 2010 21:34:41 +0000 Subject: cleanup per feedback. use a helper function for getting the first non-reserved physical register in a register class. Make sure to assert if the register class is empty. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112743 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocLinearScan.cpp | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) (limited to 'lib/CodeGen/RegAllocLinearScan.cpp') diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index a667f97a4e..23ec2d7676 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -336,6 +336,17 @@ namespace { SmallVector &inactiveCounts, bool SkipDGRegs); + /// getFirstNonReservedPhysReg - return the first non-reserved physical + /// register in the register class. + unsigned getFirstNonReservedPhysReg(const TargetRegisterClass *RC) { + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); + while (i != aoe && reservedRegs_.test(*i)) + ++i; + assert(i != aoe && "All registers reserved?!"); + return *i; + } + void ComputeRelatedRegClasses(); template @@ -951,14 +962,8 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) { const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); if (cur->empty()) { unsigned physReg = vrm_->getRegAllocPref(cur->reg); - if (!physReg) { - TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); - TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); - while (reservedRegs_.test(*i) && i != aoe) - ++i; - assert(i != aoe && "All registers reserved?!"); - physReg = *i; - } + if (!physReg) + physReg = getFirstNonReservedPhysReg(RC); DEBUG(dbgs() << tri_->getName(physReg) << '\n'); // Note the register is not really in use. vrm_->assignVirt2Phys(cur->reg, physReg); @@ -1168,15 +1173,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) { minWeight = RegsWeights[0].second; if (minWeight == HUGE_VALF) { // All registers must have inf weight. Just grab one! - if (BestPhysReg == 0) { - TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); - TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); - while (reservedRegs_.test(*i) && i != aoe) - ++i; - assert(i != aoe && "All registers reserved?!"); - minReg = *i; - } else - minReg = BestPhysReg; + minReg = BestPhysReg ? BestPhysReg : getFirstNonReservedPhysReg(RC); if (cur->weight == HUGE_VALF || li_->getApproximateInstructionCount(*cur) == 0) { // Spill a physical register around defs and uses. -- cgit v1.2.3