From 45a31492d5475a1744966a0cd5e631694b29f953 Mon Sep 17 00:00:00 2001 From: Artyom Skrobov Date: Tue, 10 Jun 2014 13:11:35 +0000 Subject: Condition codes AL and NV are invalid in the aliases that use inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM). Matching aliases based on "immediate classes", when disassembling, wasn't previously supported, hence adding MCOperandPredicate into class Operand, and implementing the support for it in AsmWriterEmitter. The parsing for those aliases was already custom, so just adding the missing condition into AArch64AsmParser::parseCondCode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210528 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64InstrFormats.td | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'lib/Target/AArch64/AArch64InstrFormats.td') diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 42326fc182..446149b4fb 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -963,8 +963,14 @@ def ccode : Operand { let ParserMatchClass = CondCode; } def inv_ccode : Operand { + // AL and NV are invalid in the aliases which use inv_ccode let PrintMethod = "printInverseCondCode"; let ParserMatchClass = CondCode; + let MCOperandPredicate = [{ + return MCOp.isImm() && + MCOp.getImm() != AArch64CC::AL && + MCOp.getImm() != AArch64CC::NV; + }]; } // Conditional branch target. 19-bit immediate. The low two bits of the target -- cgit v1.2.3