From 57148c166ab232191098492633c924fad9c44ef3 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Fri, 7 Jun 2013 05:54:19 +0000 Subject: Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseInstrInfo.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'lib/Target/ARM/ARMBaseInstrInfo.cpp') diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index b530515cdd..ad1447503f 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -113,8 +113,7 @@ ScheduleHazardRecognizer *ARMBaseInstrInfo:: CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const { if (Subtarget.isThumb2() || Subtarget.hasVFP2()) - return (ScheduleHazardRecognizer *) - new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); + return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG); return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG); } -- cgit v1.2.3