From 420761a0f193e87d08ee1c51b26bba23ab4bac7f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 20 Apr 2012 07:30:17 +0000 Subject: Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp') diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 3907f75352..2a09b20b9c 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -258,7 +258,7 @@ ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const TargetRegisterClass * ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { - return ARM::GPRRegisterClass; + return &ARM::GPRRegClass; } const TargetRegisterClass * @@ -369,7 +369,7 @@ ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, }; // We only support even/odd hints for GPR and rGPR. - if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass) + if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass) return RC->getRawAllocationOrder(MF); if (HintType == ARMRI::RegPairEven) { @@ -1110,7 +1110,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Must be addrmode4/6. MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); else { - ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); + ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); if (!AFI->isThumbFunction()) emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, Pred, PredReg, TII); -- cgit v1.2.3