From dd364419ee64cd5bb234af006ce0cb285e4a84ca Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 27 Aug 2012 23:58:52 +0000 Subject: Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM. It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp') diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 9deb96ea9e..828e7d4e95 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -870,10 +870,14 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { // return false for everything else. unsigned Opc = MI->getOpcode(); switch (Opc) { - case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: + case ARM::LDRi12: case ARM::ATOMIC_LDRi12: + case ARM::LDRH: case ARM::ATOMIC_LDRH: + case ARM::LDRBi12: case ARM::ATOMIC_LDRBi12: case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: - case ARM::t2LDRi12: case ARM::t2LDRi8: - case ARM::t2STRi12: case ARM::t2STRi8: + case ARM::t2LDRi12: case ARM::ATOMIC_t2LDRi12: + case ARM::t2LDRi8: case ARM::ATOMIC_t2LDRi8: + case ARM::t2STRi12: + case ARM::t2STRi8: case ARM::VLDRS: case ARM::VLDRD: case ARM::VSTRS: case ARM::VSTRD: case ARM::tSTRspi: case ARM::tLDRspi: -- cgit v1.2.3