From 6849f102ca2a3d2dcb252dd4f997db6f92443688 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Tue, 14 Jan 2014 13:05:47 +0000 Subject: ARM: add constraint that RdLo != Rn != RdHi for v5 MLA insts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199212 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/Target/ARM/ARMInstrInfo.td') diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 334d75fd53..05c3859b4b 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3714,7 +3714,8 @@ def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), let Inst{3-0} = Rn; } -let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in { +let Constraints = + "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4, IIC_iMAC64, [], -- cgit v1.2.3