From c92ba4e90501e407c8f71a18e62b8858513085ed Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Mon, 23 Apr 2012 22:04:10 +0000 Subject: Tidy up. 80 columns, whitespace, et. al. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155399 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrVFP.td | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'lib/Target/ARM/ARMInstrVFP.td') diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 3523655410..f447e304b4 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -827,9 +827,9 @@ let Constraints = "$a = $dst" in { // FP to Fixed-Point: // Single Precision register -class AVConv1XInsS_Encode op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, - dag oops, dag iops, InstrItinClass itin, string opc, string asm, - list pattern> +class AVConv1XInsS_Encode op1, bits<2> op2, bits<4> op3, bits<4> op4, + bit op5, dag oops, dag iops, InstrItinClass itin, + string opc, string asm, list pattern> : AVConv1XI { bits<5> dst; // if dp_operation then UInt(D:Vd) else UInt(Vd:D); @@ -838,9 +838,9 @@ class AVConv1XInsS_Encode op1, bits<2> op2, bits<4> op3, bits<4> op4, bi } // Double Precision register -class AVConv1XInsD_Encode op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, - dag oops, dag iops, InstrItinClass itin, string opc, string asm, - list pattern> +class AVConv1XInsD_Encode op1, bits<2> op2, bits<4> op3, bits<4> op4, + bit op5, dag oops, dag iops, InstrItinClass itin, + string opc, string asm, list pattern> : AVConv1XI { bits<5> dst; // if dp_operation then UInt(D:Vd) else UInt(Vd:D); -- cgit v1.2.3