From 6c4ec69c6be8b0003b420b58df585caa0563ef70 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Fri, 18 Apr 2014 21:22:04 +0000 Subject: [ARM64] Ports the Cortex-A53 Machine Model description from AArch64. Summary: This port includes the rudimentary latencies that were provided for the Cortex-A53 Machine Model in the AArch64 backend. It also changes the SchedAlias for COPY in the Cyclone model to an explicit WriteRes mapping to avoid conflicts in other subtargets. Differential Revision: http://reviews.llvm.org/D3427 Patch by Dave Estes ! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206652 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/ARM64SchedCyclone.td | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'lib/Target/ARM64/ARM64SchedCyclone.td') diff --git a/lib/Target/ARM64/ARM64SchedCyclone.td b/lib/Target/ARM64/ARM64SchedCyclone.td index 65c68b3f05..8b3a7592af 100644 --- a/lib/Target/ARM64/ARM64SchedCyclone.td +++ b/lib/Target/ARM64/ARM64SchedCyclone.td @@ -342,7 +342,9 @@ def : InstRW<[WriteVMov], (instrs ORRv16i8)>; // INS V[x],V[y] is a WriteV. // FMOVWSr,FMOVXDr,FMOVXDHighr -def : SchedAlias; +def : WriteRes { + let Latency = 5; +} // FMOVSWr,FMOVDXr def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>; -- cgit v1.2.3