From 84a2c2bbb58dd0f91608d8d14b3139b9295ca036 Mon Sep 17 00:00:00 2001 From: Jyotsna Verma Date: Thu, 14 Feb 2013 19:57:17 +0000 Subject: Hexagon: Change insn class to support instruction encoding. This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175205 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrFormats.td | 412 ++++++++++++++---------------- 1 file changed, 193 insertions(+), 219 deletions(-) (limited to 'lib/Target/Hexagon/HexagonInstrFormats.td') diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index 71c620b131..587fa7d7f1 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -13,19 +13,19 @@ // *** Must match HexagonBaseInfo.h *** //===----------------------------------------------------------------------===// -class Type t> { +class IType t> { bits<5> Value = t; } -def TypePSEUDO : Type<0>; -def TypeALU32 : Type<1>; -def TypeCR : Type<2>; -def TypeJR : Type<3>; -def TypeJ : Type<4>; -def TypeLD : Type<5>; -def TypeST : Type<6>; -def TypeSYSTEM : Type<7>; -def TypeXTYPE : Type<8>; -def TypeMARKER : Type<31>; +def TypePSEUDO : IType<0>; +def TypeALU32 : IType<1>; +def TypeCR : IType<2>; +def TypeJR : IType<3>; +def TypeJ : IType<4>; +def TypeLD : IType<5>; +def TypeST : IType<6>; +def TypeSYSTEM : IType<7>; +def TypeXTYPE : IType<8>; +def TypeENDLOOP: IType<31>; // Maintain list of valid subtargets for each instruction. class SubTarget value> { @@ -44,8 +44,8 @@ def HasV5SubT : SubTarget<0x8>; def NoV5SubT : SubTarget<0x7>; // Addressing modes for load/store instructions -class AddrModeType value> { - bits<4> Value = value; +class AddrModeType value> { + bits<3> Value = value; } def NoAddrMode : AddrModeType<0>; // No addressing mode @@ -55,14 +55,35 @@ def BaseImmOffset : AddrModeType<3>; // Indirect with offset def BaseLongOffset : AddrModeType<4>; // Indirect with long offset def BaseRegOffset : AddrModeType<5>; // Indirect with register offset +class MemAccessSize value> { + bits<3> Value = value; +} + +def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction. +def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb). +def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh). +def WordAccess : MemAccessSize<3>;// Word access instrution (memw). +def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd) + + //===----------------------------------------------------------------------===// // Intruction Class Declaration + //===----------------------------------------------------------------------===// -class InstHexagon pattern, - string cstr, InstrItinClass itin, Type type> : Instruction { - field bits<32> Inst; +class OpcodeHexagon { + field bits<32> Inst = ?; // Default to an invalid insn. + bits<4> IClass = 0; // ICLASS + bits<2> IParse = 0; // Parse bits. + + let Inst{31-28} = IClass; + let Inst{15-14} = IParse; + + bits<1> zero = 0; +} +class InstHexagon pattern, + string cstr, InstrItinClass itin, IType type> + : Instruction, OpcodeHexagon { let Namespace = "Hexagon"; dag OutOperandList = outs; @@ -73,48 +94,63 @@ class InstHexagon pattern, let Itinerary = itin; let Size = 4; - // *** Must match HexagonBaseInfo.h *** + // *** Must match MCTargetDesc/HexagonBaseInfo.h *** + // Instruction type according to the ISA. - Type HexagonType = type; - let TSFlags{4-0} = HexagonType.Value; + IType Type = type; + let TSFlags{4-0} = Type.Value; + // Solo instructions, i.e., those that cannot be in a packet with others. - bits<1> isHexagonSolo = 0; - let TSFlags{5} = isHexagonSolo; + bits<1> isSolo = 0; + let TSFlags{5} = isSolo; + // Predicated instructions. bits<1> isPredicated = 0; let TSFlags{6} = isPredicated; + bits<1> isPredicatedFalse = 0; + let TSFlags{7} = isPredicatedFalse; bits<1> isPredicatedNew = 0; - let TSFlags{7} = isPredicatedNew; - - // Stores that can be newified. + let TSFlags{8} = isPredicatedNew; + + // New-value insn helper fields. + bits<1> isNewValue = 0; + let TSFlags{9} = isNewValue; // New-value consumer insn. + bits<1> hasNewValue = 0; + let TSFlags{10} = hasNewValue; // New-value producer insn. + bits<3> opNewValue = 0; + let TSFlags{13-11} = opNewValue; // New-value produced operand. + bits<2> opNewBits = 0; + let TSFlags{15-14} = opNewBits; // New-value opcode bits location: 0, 8, 16. bits<1> isNVStorable = 0; - let TSFlags{8} = isNVStorable; - - // New-value store instructions. + let TSFlags{16} = isNVStorable; // Store that can become new-value store. bits<1> isNVStore = 0; - let TSFlags{9} = isNVStore; + let TSFlags{17} = isNVStore; // New-value store insn. // Immediate extender helper fields. bits<1> isExtendable = 0; - let TSFlags{10} = isExtendable; // Insn may be extended. + let TSFlags{18} = isExtendable; // Insn may be extended. bits<1> isExtended = 0; - let TSFlags{11} = isExtended; // Insn must be extended. + let TSFlags{19} = isExtended; // Insn must be extended. bits<3> opExtendable = 0; - let TSFlags{14-12} = opExtendable; // Which operand may be extended. + let TSFlags{22-20} = opExtendable; // Which operand may be extended. bits<1> isExtentSigned = 0; - let TSFlags{15} = isExtentSigned; // Signed or unsigned range. + let TSFlags{23} = isExtentSigned; // Signed or unsigned range. bits<5> opExtentBits = 0; - let TSFlags{20-16} = opExtentBits; //Number of bits of range before extending. + let TSFlags{28-24} = opExtentBits; //Number of bits of range before extending. // If an instruction is valid on a subtarget (v2-v5), set the corresponding // bit from validSubTargets. v2 is the least significant bit. // By default, instruction is valid on all subtargets. SubTarget validSubTargets = HasV2SubT; - let TSFlags{24-21} = validSubTargets.Value; + let TSFlags{32-29} = validSubTargets.Value; - // Addressing mode for load/store instrutions. + // Addressing mode for load/store instructions. AddrModeType addrMode = NoAddrMode; - let TSFlags{28-25} = addrMode.Value; + let TSFlags{35-33} = addrMode.Value; + + // Memory access size for mem access instructions (load/store) + MemAccessSize accessSize = NoMemAccess; + let TSFlags{38-36} = accessSize.Value; // Fields used for relation models. string BaseOpcode = ""; @@ -124,6 +160,11 @@ class InstHexagon pattern, string InputType = ""; // Input is "imm" or "reg" type. string isMEMri = "false"; // Set to "true" for load/store with MEMri operand. string isFloat = "false"; // Set to "true" for the floating-point load/store. + string isBrTaken = ""; // Set to "true"/"false" for jump instructions + + let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"), + ""); + let PNewValue = !if(isPredicatedNew, "new", ""); // *** Must match MCTargetDesc/HexagonBaseInfo.h *** } @@ -134,187 +175,143 @@ class InstHexagon pattern, // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. -class LDInst pattern> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<13> imm13; -} +class LDInst pattern = [], + string cstr = ""> + : InstHexagon; -class LDInst2 pattern> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<13> imm13; - let mayLoad = 1; -} +let mayLoad = 1 in +class LDInst2 pattern = [], + string cstr = ""> + : LDInst; + +class CONSTLDInst pattern = [], + string cstr = ""> + : LDInst; // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. -class LDInstPost pattern, - string cstr> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<5> rt; - bits<13> imm13; -} +class LDInstPost pattern = [], + string cstr = ""> + : LDInst; + +let mayLoad = 1 in +class LD0Inst pattern = [], + string cstr = ""> + : LDInst; // ST Instruction Class in V2/V3 can take SLOT0 only. // ST Instruction Class in V4 can take SLOT0 & SLOT1. // Definition of the instruction class CHANGED from V2/V3 to V4. -class STInst pattern> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<13> imm13; -} +let mayStore = 1 in +class STInst pattern = [], + string cstr = ""> + : InstHexagon; -class STInst2 pattern> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<13> imm13; - let mayStore = 1; -} +class STInst2 pattern = [], + string cstr = ""> + : STInst; -// SYSTEM Instruction Class in V4 can take SLOT0 only -// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. -class SYSInst pattern> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<13> imm13; -} +let mayStore = 1 in +class ST0Inst pattern = [], + string cstr = ""> + : InstHexagon; // ST Instruction Class in V2/V3 can take SLOT0 only. // ST Instruction Class in V4 can take SLOT0 & SLOT1. // Definition of the instruction class CHANGED from V2/V3 to V4. -class STInstPost pattern, - string cstr> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<5> rt; - bits<13> imm13; -} +class STInstPost pattern = [], + string cstr = ""> + : STInst; + +// SYSTEM Instruction Class in V4 can take SLOT0 only +// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. +class SYSInst pattern = [], + string cstr = ""> + : InstHexagon; // ALU32 Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. -class ALU32Type pattern> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<5> rt; - bits<16> imm16; - bits<16> imm16_2; -} +class ALU32Inst pattern = [], + string cstr = ""> + : InstHexagon; // ALU64 Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. -class ALU64Type pattern> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<5> rt; - bits<16> imm16; - bits<16> imm16_2; -} +class ALU64Inst pattern = [], + string cstr = ""> + : InstHexagon; + +class ALU64_acc pattern = [], + string cstr = ""> + : ALU64Inst; -class ALU64_acc pattern, - string cstr> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<5> rt; - bits<16> imm16; - bits<16> imm16_2; -} // M Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. -class MInst pattern> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<5> rt; -} +class MInst pattern = [], + string cstr = ""> + : InstHexagon; // M Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. -class MInst_acc pattern, - string cstr> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<5> rt; -} +class MInst_acc pattern = [], + string cstr = ""> + : MInst; // S Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. -class SInst pattern> - : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<5> rt; -} +class SInst pattern = [], + string cstr = ""> + : InstHexagon; // S Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. -class SInst_acc pattern, - string cstr> - : InstHexagon { -// : InstHexagon { -// : InstHexagon { - bits<5> rd; - bits<5> rs; - bits<5> rt; -} +class SInst_acc pattern = [], + string cstr = ""> + : SInst; // J Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. -class JType pattern> - : InstHexagon { - bits<16> imm16; -} +class JInst pattern = [], + string cstr = ""> + : InstHexagon; // JR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. -class JRType pattern> - : InstHexagon { - bits<5> rs; - bits<5> pu; // Predicate register -} +class JRInst pattern = [], + string cstr = ""> + : InstHexagon; // CR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. -class CRInst pattern> - : InstHexagon { - bits<5> rs; - bits<10> imm10; -} +class CRInst pattern = [], + string cstr = ""> + : InstHexagon; -class Marker pattern> - : InstHexagon { - let isCodeGenOnly = 1; - let isPseudo = 1; -} +let isCodeGenOnly = 1, isPseudo = 1 in +class Endloop pattern = [], + string cstr = ""> + : InstHexagon; -class Pseudo pattern> - : InstHexagon { - let isCodeGenOnly = 1; - let isPseudo = 1; -} +let isCodeGenOnly = 1, isPseudo = 1 in +class Pseudo pattern = [], + string cstr = ""> + : InstHexagon; + +let isCodeGenOnly = 1, isPseudo = 1 in +class PseudoM pattern = [], + string cstr=""> + : InstHexagon; //===----------------------------------------------------------------------===// // Intruction Classes Definitions - @@ -324,75 +321,52 @@ class Pseudo pattern> // // ALU32 patterns //. -class ALU32_rr pattern> - : ALU32Type { -} +class ALU32_rr pattern, + string cstr = ""> + : ALU32Inst; -class ALU32_ir pattern> - : ALU32Type { - let rt{0-4} = 0; -} +class ALU32_ir pattern, + string cstr = ""> + : ALU32Inst; -class ALU32_ri pattern> - : ALU32Type { - let rt{0-4} = 0; -} +class ALU32_ri pattern, + string cstr = ""> + : ALU32Inst; -class ALU32_ii pattern> - : ALU32Type { - let rt{0-4} = 0; -} +class ALU32_ii pattern, + string cstr = ""> + : ALU32Inst; // // ALU64 patterns. // -class ALU64_rr pattern> - : ALU64Type { -} - -class ALU64_ri pattern> - : ALU64Type { - let rt{0-4} = 0; -} - -// J Type Instructions. -class JInst pattern> - : JType { -} - -// JR type Instructions. -class JRInst pattern> - : JRType { -} +class ALU64_rr pattern, + string cstr = ""> + : ALU64Inst; +class ALU64_ri pattern, + string cstr = ""> + : ALU64Inst; // Post increment ST Instruction. -class STInstPI pattern, - string cstr> - : STInstPost { - let rt{0-4} = 0; -} +class STInstPI pattern = [], + string cstr = ""> + : STInst; -class STInst2PI pattern, - string cstr> - : STInstPost { - let rt{0-4} = 0; - let mayStore = 1; -} +let mayStore = 1 in +class STInst2PI pattern = [], + string cstr = ""> + : STInst; // Post increment LD Instruction. -class LDInstPI pattern, - string cstr> - : LDInstPost { - let rt{0-4} = 0; -} - -class LDInst2PI pattern, - string cstr> - : LDInstPost { - let rt{0-4} = 0; - let mayLoad = 1; -} +class LDInstPI pattern = [], + string cstr = ""> + : LDInst; + +let mayLoad = 1 in +class LDInst2PI pattern = [], + string cstr = ""> + : LDInst; //===----------------------------------------------------------------------===// // V4 Instruction Format Definitions + -- cgit v1.2.3