From 65502aa5fd1a6581909ee410d177a775789af540 Mon Sep 17 00:00:00 2001 From: Jyotsna Verma Date: Fri, 30 Nov 2012 04:19:09 +0000 Subject: Use multiclass for the load instructions with 'base + register offset' addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168976 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrInfoV4.td | 374 ++++++++----------------------- 1 file changed, 97 insertions(+), 277 deletions(-) (limited to 'lib/Target/Hexagon/HexagonInstrInfoV4.td') diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index b40fc418c1..22aeac4de9 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -415,15 +415,103 @@ def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst), (i32 IntRegs:$src2)))))]>, Requires<[HasV4T]>; -let AddedComplexity = 40, isPredicable = 1 in -def LDrid_indexed_shl_V4 : LDInst<(outs DoubleRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), - "$dst=memd($src1+$src2<<#$offset)", - [(set (i64 DoubleRegs:$dst), - (i64 (load (add (i32 IntRegs:$src1), - (shl (i32 IntRegs:$src2), - u2ImmPred:$offset)))))]>, - Requires<[HasV4T]>; +// multiclass for load instructions with base + register offset +// addressing mode +multiclass ld_idxd_shl_pbase { + let PNewValue = #!if(isPredNew, "new", "") in + def #NAME# : LDInst2<(outs RC:$dst), + (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), + !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", + ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)", + []>, Requires<[HasV4T]>; +} + +multiclass ld_idxd_shl_pred { + let PredSense = #!if(PredNot, "false", "true") in { + defm _c#NAME# : ld_idxd_shl_pbase; + // Predicate new + defm _cdn#NAME# : ld_idxd_shl_pbase; + } +} + +let neverHasSideEffects = 1 in +multiclass ld_idxd_shl { + let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in { + let isPredicable = 1 in + def #NAME#_V4 : LDInst2<(outs RC:$dst), + (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), + "$dst = "#mnemonic#"($src1+$src2<<#$offset)", + []>, Requires<[HasV4T]>; + + let isPredicated = 1 in { + defm Pt_V4 : ld_idxd_shl_pred; + defm NotPt_V4 : ld_idxd_shl_pred; + } + } +} + +let addrMode = BaseRegOffset in { + defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel; + defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel; + defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel; + defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel; + defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel; + defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel; +} + +// 'def pats' for load instructions with base + register offset and non-zero +// immediate value. Immediate value is used to left-shift the second +// register operand. +let AddedComplexity = 40 in { +def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, + (shl IntRegs:$src2, u2ImmPred:$offset)))), + (LDrib_indexed_shl_V4 IntRegs:$src1, + IntRegs:$src2, u2ImmPred:$offset)>, + Requires<[HasV4T]>; + +def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, + (shl IntRegs:$src2, u2ImmPred:$offset)))), + (LDriub_indexed_shl_V4 IntRegs:$src1, + IntRegs:$src2, u2ImmPred:$offset)>, + Requires<[HasV4T]>; + +def : Pat <(i32 (extloadi8 (add IntRegs:$src1, + (shl IntRegs:$src2, u2ImmPred:$offset)))), + (LDriub_indexed_shl_V4 IntRegs:$src1, + IntRegs:$src2, u2ImmPred:$offset)>, + Requires<[HasV4T]>; + +def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, + (shl IntRegs:$src2, u2ImmPred:$offset)))), + (LDrih_indexed_shl_V4 IntRegs:$src1, + IntRegs:$src2, u2ImmPred:$offset)>, + Requires<[HasV4T]>; + +def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, + (shl IntRegs:$src2, u2ImmPred:$offset)))), + (LDriuh_indexed_shl_V4 IntRegs:$src1, + IntRegs:$src2, u2ImmPred:$offset)>, + Requires<[HasV4T]>; + +def : Pat <(i32 (extloadi16 (add IntRegs:$src1, + (shl IntRegs:$src2, u2ImmPred:$offset)))), + (LDriuh_indexed_shl_V4 IntRegs:$src1, + IntRegs:$src2, u2ImmPred:$offset)>, + Requires<[HasV4T]>; + +def : Pat <(i32 (load (add IntRegs:$src1, + (shl IntRegs:$src2, u2ImmPred:$offset)))), + (LDriw_indexed_shl_V4 IntRegs:$src1, + IntRegs:$src2, u2ImmPred:$offset)>, + Requires<[HasV4T]>; + +def : Pat <(i64 (load (add IntRegs:$src1, + (shl IntRegs:$src2, u2ImmPred:$offset)))), + (LDrid_indexed_shl_V4 IntRegs:$src1, + IntRegs:$src2, u2ImmPred:$offset)>, + Requires<[HasV4T]>; +} //// Load doubleword conditionally. // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2) @@ -459,42 +547,6 @@ def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), []>, Requires<[HasV4T]>; -// if (Pv) Rd=memd(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrid_indexed_shl_cPt_V4 : LDInst2<(outs DoubleRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1) $dst=memd($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (Pv.new) Rd=memd(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrid_indexed_shl_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1.new) $dst=memd($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv) Rd=memd(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrid_indexed_shl_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1) $dst=memd($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv.new) Rd=memd(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrid_indexed_shl_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1.new) $dst=memd($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - // Rdd=memd(Rt<<#u2+#U6) //// Load byte. @@ -526,26 +578,6 @@ def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst), (i32 IntRegs:$src2)))))]>, Requires<[HasV4T]>; -let AddedComplexity = 40, isPredicable = 1 in -def LDrib_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), - "$dst=memb($src1+$src2<<#$offset)", - [(set (i32 IntRegs:$dst), - (i32 (sextloadi8 (add (i32 IntRegs:$src1), - (shl (i32 IntRegs:$src2), - u2ImmPred:$offset)))))]>, - Requires<[HasV4T]>; - -let AddedComplexity = 40, isPredicable = 1 in -def LDriub_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), - "$dst=memub($src1+$src2<<#$offset)", - [(set (i32 IntRegs:$dst), - (i32 (zextloadi8 (add (i32 IntRegs:$src1), - (shl (i32 IntRegs:$src2), - u2ImmPred:$offset)))))]>, - Requires<[HasV4T]>; - let AddedComplexity = 40, isPredicable = 1 in def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), @@ -590,42 +622,6 @@ def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), []>, Requires<[HasV4T]>; -// if (Pv) Rd=memb(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrib_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1) $dst=memb($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (Pv.new) Rd=memb(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrib_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1.new) $dst=memb($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv) Rd=memb(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrib_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1) $dst=memb($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv.new) Rd=memb(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrib_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1.new) $dst=memb($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - //// Load unsigned byte conditionally. // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2) // if (Pv) Rd=memub(Rs+Rt<<#u2) @@ -660,42 +656,6 @@ def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), []>, Requires<[HasV4T]>; -// if (Pv) Rd=memub(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriub_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1) $dst=memub($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (Pv.new) Rd=memub(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriub_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1.new) $dst=memub($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv) Rd=memub(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriub_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1) $dst=memub($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv.new) Rd=memub(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriub_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1.new) $dst=memub($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - // Rd=memb(Rt<<#u2+#U6) //// Load halfword @@ -727,27 +687,6 @@ def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst), (i32 IntRegs:$src2)))))]>, Requires<[HasV4T]>; -// Rd=memh(Rs+Rt<<#u2) -let AddedComplexity = 40, isPredicable = 1 in -def LDrih_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), - "$dst=memh($src1+$src2<<#$offset)", - [(set (i32 IntRegs:$dst), - (i32 (sextloadi16 (add (i32 IntRegs:$src1), - (shl (i32 IntRegs:$src2), - u2ImmPred:$offset)))))]>, - Requires<[HasV4T]>; - -let AddedComplexity = 40, isPredicable = 1 in -def LDriuh_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), - "$dst=memuh($src1+$src2<<#$offset)", - [(set (i32 IntRegs:$dst), - (i32 (zextloadi16 (add (i32 IntRegs:$src1), - (shl (i32 IntRegs:$src2), - u2ImmPred:$offset)))))]>, - Requires<[HasV4T]>; - let AddedComplexity = 40, isPredicable = 1 in def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), @@ -792,42 +731,6 @@ def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), []>, Requires<[HasV4T]>; -// if (Pv) Rd=memh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrih_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1) $dst=memh($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (Pv.new) Rd=memh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrih_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1.new) $dst=memh($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv) Rd=memh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrih_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1) $dst=memh($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv.new) Rd=memh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDrih_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1.new) $dst=memh($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - //// Load unsigned halfword conditionally. // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2) // if (Pv) Rd=memuh(Rs+Rt<<#u2) @@ -862,42 +765,6 @@ def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), []>, Requires<[HasV4T]>; -// if (Pv) Rd=memuh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriuh_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1) $dst=memuh($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (Pv.new) Rd=memuh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriuh_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1.new) $dst=memuh($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv) Rd=memuh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriuh_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1) $dst=memuh($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv.new) Rd=memuh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriuh_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1.new) $dst=memuh($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - // Rd=memh(Rt<<#u2+#U6) //// Load word. @@ -921,17 +788,6 @@ def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst), (i32 IntRegs:$src2)))))]>, Requires<[HasV4T]>; -// Rd=memw(Rs+Rt<<#u2) -let AddedComplexity = 40, isPredicable = 1 in -def LDriw_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), - "$dst=memw($src1+$src2<<#$offset)", - [(set (i32 IntRegs:$dst), - (i32 (load (add (i32 IntRegs:$src1), - (shl (i32 IntRegs:$src2), - u2ImmPred:$offset)))))]>, - Requires<[HasV4T]>; - //// Load word conditionally. // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2) // if (Pv) Rd=memw(Rs+Rt<<#u2) @@ -966,42 +822,6 @@ def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), []>, Requires<[HasV4T]>; -// if (Pv) Rd=memh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriw_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1) $dst=memw($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (Pv.new) Rd=memh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriw_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if ($src1.new) $dst=memw($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv) Rd=memh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriw_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1) $dst=memw($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - -// if (!Pv.new) Rd=memh(Rs+Rt<<#u2) -let AddedComplexity = 45, isPredicated = 1 in -def LDriw_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, - u2Imm:$offset), - "if (!$src1.new) $dst=memw($src2+$src3<<#$offset)", - []>, - Requires<[HasV4T]>; - /// Load from global offset let isPredicable = 1, neverHasSideEffects = 1 in -- cgit v1.2.3