From f862a4aefe2b50bc7643d27ae6689356cb977f63 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 21 Jan 2014 15:21:14 +0000 Subject: [mips][sched] Split IILoad into II_L[BHWD], II_L[BHW]U, II_L[WD][LR], and II_RESTORE No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199749 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMipsInstrInfo.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/Mips/MicroMipsInstrInfo.td') diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 61159d94a1..639e3deb75 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -145,7 +145,7 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>; } - def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, IILoad>, LL_FM_MM<0xe>; + def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>; /// Load and Store Instructions - unaligned def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>, -- cgit v1.2.3