From 36c58aa4d6957a4ca3800c47fa241acc59d676c8 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Wed, 13 Jun 2012 02:42:47 +0000 Subject: Clean up trailing blanks in Mips16InstrFormats.td Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158382 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16InstrFormats.td | 92 +++++++++++++++++------------------ 1 file changed, 46 insertions(+), 46 deletions(-) (limited to 'lib/Target/Mips/Mips16InstrFormats.td') diff --git a/lib/Target/Mips/Mips16InstrFormats.td b/lib/Target/Mips/Mips16InstrFormats.td index d40b3dde89..add343cfea 100644 --- a/lib/Target/Mips/Mips16InstrFormats.td +++ b/lib/Target/Mips/Mips16InstrFormats.td @@ -17,7 +17,7 @@ // immediate 4-,5-,8- or 11-bit immediate, branch displacemen, or // or imm address displacement // -// op 5-bit major operation code +// op 5-bit major operation code // // rx 3-bit source or destination register // @@ -139,7 +139,7 @@ class MipsPseudo16 pattern>: //===----------------------------------------------------------------------===// class FI16 op, dag outs, dag ins, string asmstr, list pattern, - InstrItinClass itin>: MipsInst16: MipsInst16 { bits<11> imm11; @@ -304,7 +304,7 @@ class FI816 op, bits<3> _func, dag outs, dag ins, string asmstr, { bits<3> func; bits<8> imm8; - + let Opcode = op; let func = _func; @@ -324,14 +324,14 @@ class FI8_MOVR3216 op, bits<3> _func, dag outs, dag ins, string asmstr, bits<3> func; bits<4> ry; bits<4> r32; - + let Opcode = op; let func = _func; let Inst{10-8} = func; let Inst{7-4} = ry; let Inst{3-0} = r32; - + } @@ -349,19 +349,19 @@ class FI8_MOV32R16 op, bits<3> _func, dag outs, dag ins, string asmstr, bits<5> r32; bits<3> rz; - + let Opcode = op; let func = _func; let Inst{10-8} = func; - let Inst{7-5} = r32{2-0}; + let Inst{7-5} = r32{2-0}; let Inst{4-3} = r32{4-3}; let Inst{2-0} = rz; - + } //===----------------------------------------------------------------------===// -// Format i8_SVRS instruction class in Mips : +// Format i8_SVRS instruction class in Mips : // <|opcode|svrs|s|ra|s0|s1|framesize> //===----------------------------------------------------------------------===// @@ -375,7 +375,7 @@ class FI8_SVRS16 op, bits<3> _SVRS, dag outs, dag ins, string asmstr, bits<1> s0; bits<1> s1; bits<4> framesize; - + let Opcode = op; let SVRS = _SVRS; @@ -385,11 +385,11 @@ class FI8_SVRS16 op, bits<3> _SVRS, dag outs, dag ins, string asmstr, let Inst{5} = s0; let Inst{4} = s1; let Inst{3-0} = framesize; - + } //===----------------------------------------------------------------------===// -// Format JAL instruction class in Mips16 : +// Format JAL instruction class in Mips16 : // <|opcode|svrs|s|ra|s0|s1|framesize> //===----------------------------------------------------------------------===// @@ -400,7 +400,7 @@ class FJAL16 op, bits<1> _X, dag outs, dag ins, string asmstr, bits<1> X; bits<26> imm26; - + let X = _X; let Inst{31-27} = 0b00011; @@ -408,12 +408,12 @@ class FJAL16 op, bits<1> _X, dag outs, dag ins, string asmstr, let Inst{25-21} = imm26{20-16}; let Inst{20-16} = imm26{25-21}; let Inst{15-0} = imm26{15-0}; - + } //===----------------------------------------------------------------------===// -// Format EXT-I instruction class in Mips16 : +// Format EXT-I instruction class in Mips16 : // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0> //===----------------------------------------------------------------------===// @@ -423,7 +423,7 @@ class FEXT_I16 _eop, dag outs, dag ins, string asmstr, { bits<16> imm16; bits<5> eop; - + let eop = _eop; let Inst{26-21} = imm16{10-5}; @@ -431,7 +431,7 @@ class FEXT_I16 _eop, dag outs, dag ins, string asmstr, let Inst{15-11} = eop; let Inst{10-5} = 0; let Inst{4-0} = imm16{4-0}; - + } @@ -440,13 +440,13 @@ class FEXT_I16 _eop, dag outs, dag ins, string asmstr, //===----------------------------------------------------------------------===// -// Format ASMACRO instruction class in Mips16 : +// Format ASMACRO instruction class in Mips16 : // //===----------------------------------------------------------------------===// class FASMACRO16 op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND { bits<3> select; @@ -456,7 +456,7 @@ class FASMACRO16 op, dag outs, dag ins, string asmstr, bits<3> p2; bits<3> p1; bits<5> p0; - + let Inst{26-24} = select; let Inst{23-21} = p4; @@ -464,25 +464,25 @@ class FASMACRO16 op, dag outs, dag ins, string asmstr, let Inst{15-11} = RRR; let Inst{10-8} = p2; let Inst{7-5} = p1; - let Inst{4-0} = p0; - + let Inst{4-0} = p0; + } //===----------------------------------------------------------------------===// -// Format EXT-RI instruction class in Mips16 : +// Format EXT-RI instruction class in Mips16 : // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0> //===----------------------------------------------------------------------===// class FEXT_RI16 _op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND { bits<16> imm16; bits<5> op; bits<3> rx; - + let op = _op; let Inst{26-21} = imm16{10-5}; @@ -491,7 +491,7 @@ class FEXT_RI16 _op, dag outs, dag ins, string asmstr, let Inst{10-8} = rx; let Inst{7-5} = 0; let Inst{4-0} = imm16{4-0}; - + } //===----------------------------------------------------------------------===// @@ -501,7 +501,7 @@ class FEXT_RI16 _op, dag outs, dag ins, string asmstr, class FEXT_RRI16 _op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND { bits<16> imm16; @@ -515,24 +515,24 @@ class FEXT_RRI16 _op, dag outs, dag ins, string asmstr, let Inst{10-8} = rx; let Inst{7-5} = ry; let Inst{4-0} = imm16{4-0}; - + } //===----------------------------------------------------------------------===// -// Format EXT-RRI-A instruction class in Mips16 : +// Format EXT-RRI-A instruction class in Mips16 : // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0> //===----------------------------------------------------------------------===// class FEXT_RRI_A16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND { bits<15> imm15; bits<3> rx; bits<3> ry; bits<1> f; - + let f = _f; let Inst{26-20} = imm15{10-4}; @@ -542,24 +542,24 @@ class FEXT_RRI_A16 _f, dag outs, dag ins, string asmstr, let Inst{7-5} = ry; let Inst{4} = f; let Inst{3-0} = imm15{3-0}; - + } //===----------------------------------------------------------------------===// -// Format EXT-SHIFT instruction class in Mips16 : +// Format EXT-SHIFT instruction class in Mips16 : // <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f> //===----------------------------------------------------------------------===// class FEXT_SHIFT16 op, bits<2> _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND { bits<6> sa6; bits<3> rx; bits<3> ry; bits<2> f; - + let f = _f; let Inst{26-22} = sa6{4-0}; @@ -569,24 +569,24 @@ class FEXT_SHIFT16 op, bits<2> _f, dag outs, dag ins, string asmstr, let Inst{10-8} = rx; let Inst{7-5} = ry; let Inst{4-2} = 0; - let Inst{1-0} = f; - + let Inst{1-0} = f; + } //===----------------------------------------------------------------------===// -// Format EXT-I8 instruction class in Mips16 : +// Format EXT-I8 instruction class in Mips16 : // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0> //===----------------------------------------------------------------------===// class FEXT_I816 _funct, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND { bits<16> imm16; bits<5> I8; bits<3> funct; - + let funct = _funct; let Inst{26-21} = imm16{10-5}; @@ -595,17 +595,17 @@ class FEXT_I816 _funct, dag outs, dag ins, string asmstr, let Inst{10-8} = funct; let Inst{7-5} = 0; let Inst{4-0} = imm16{4-0}; - + } //===----------------------------------------------------------------------===// -// Format EXT-I8_SVRS instruction class in Mips16 : +// Format EXT-I8_SVRS instruction class in Mips16 : // <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0> //===----------------------------------------------------------------------===// class FEXT_I8_SVRS16 pattern, InstrItinClass itin>: - MipsInst16_EXTEND { bits<3> xsregs; @@ -617,7 +617,7 @@ class FEXT_I8_SVRS16 ra; bits<1> s0; bits<1> s1; - + let Inst{26-24} = xsregs; let Inst{23-20} = framesize{7-4}; @@ -630,8 +630,8 @@ class FEXT_I8_SVRS16